mem: Add a FromCache packet attribute
This patch adds a FromCache attribute to the packet, and updates a number of the existing request commands to reflect that the request originates from a cache. The attribute simplifies checking if a requests came from a cache or not, and this is used by both the cache and snoop filter in follow-on patches. Change-Id: Ib0a7a080bbe4d6036ddd84b46fd45bc7eb41cd8f Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Steve Reinhardt <stever@gmail.com>
This commit is contained in:
Andreas Hansson
parent
da07c5c26a
commit
2509553403
10
src/mem/cache/cache.cc
vendored
10
src/mem/cache/cache.cc
vendored
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@ -191,14 +191,8 @@ Cache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
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assert(pkt->hasRespData());
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pkt->setDataFromBlock(blk->data, blkSize);
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// determine if this read is from a (coherent) cache, or not
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// by looking at the command type; we could potentially add a
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// packet attribute such as 'FromCache' to make this check a
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// bit cleaner
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if (pkt->cmd == MemCmd::ReadExReq ||
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pkt->cmd == MemCmd::ReadSharedReq ||
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pkt->cmd == MemCmd::ReadCleanReq ||
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pkt->cmd == MemCmd::SCUpgradeFailReq) {
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// determine if this read is from a (coherent) cache or not
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if (pkt->fromCache()) {
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assert(pkt->getSize() == blkSize);
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// special handling for coherent block requests from
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// upper-level caches
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2011-2015 ARM Limited
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* Copyright (c) 2011-2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -65,6 +65,8 @@ using namespace std;
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#define SET4(a1, a2, a3, a4) (SET3(a1, a2, a3) | SET1(a4))
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#define SET5(a1, a2, a3, a4, a5) (SET4(a1, a2, a3, a4) | SET1(a5))
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#define SET6(a1, a2, a3, a4, a5, a6) (SET5(a1, a2, a3, a4, a5) | SET1(a6))
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#define SET7(a1, a2, a3, a4, a5, a6, a7) (SET6(a1, a2, a3, a4, a5, a6) | \
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SET1(a7))
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const MemCmd::CommandInfo
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MemCmd::commandInfo[] =
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@ -85,20 +87,20 @@ MemCmd::commandInfo[] =
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/* WriteResp */
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{ SET2(IsWrite, IsResponse), InvalidCmd, "WriteResp" },
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/* WritebackDirty */
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{ SET4(IsWrite, IsRequest, IsEviction, HasData),
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{ SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache),
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InvalidCmd, "WritebackDirty" },
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/* WritebackClean - This allows the upstream cache to writeback a
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* line to the downstream cache without it being considered
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* dirty. */
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{ SET4(IsWrite, IsRequest, IsEviction, HasData),
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{ SET5(IsWrite, IsRequest, IsEviction, HasData, FromCache),
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InvalidCmd, "WritebackClean" },
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/* CleanEvict */
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{ SET2(IsRequest, IsEviction), InvalidCmd, "CleanEvict" },
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{ SET3(IsRequest, IsEviction, FromCache), InvalidCmd, "CleanEvict" },
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/* SoftPFReq */
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{ SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse),
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SoftPFResp, "SoftPFReq" },
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/* HardPFReq */
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{ SET4(IsRead, IsRequest, IsHWPrefetch, NeedsResponse),
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{ SET5(IsRead, IsRequest, IsHWPrefetch, NeedsResponse, FromCache),
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HardPFResp, "HardPFReq" },
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/* SoftPFResp */
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{ SET4(IsRead, IsResponse, IsSWPrefetch, HasData),
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@ -110,18 +112,19 @@ MemCmd::commandInfo[] =
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{ SET5(IsWrite, NeedsWritable, IsRequest, NeedsResponse, HasData),
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WriteResp, "WriteLineReq" },
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/* UpgradeReq */
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{ SET5(IsInvalidate, NeedsWritable, IsUpgrade, IsRequest, NeedsResponse),
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{ SET6(IsInvalidate, NeedsWritable, IsUpgrade, IsRequest, NeedsResponse,
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FromCache),
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UpgradeResp, "UpgradeReq" },
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/* SCUpgradeReq: response could be UpgradeResp or UpgradeFailResp */
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{ SET6(IsInvalidate, NeedsWritable, IsUpgrade, IsLlsc,
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IsRequest, NeedsResponse),
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{ SET7(IsInvalidate, NeedsWritable, IsUpgrade, IsLlsc,
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IsRequest, NeedsResponse, FromCache),
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UpgradeResp, "SCUpgradeReq" },
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/* UpgradeResp */
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{ SET2(IsUpgrade, IsResponse),
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InvalidCmd, "UpgradeResp" },
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/* SCUpgradeFailReq: generates UpgradeFailResp but still gets the data */
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{ SET6(IsRead, NeedsWritable, IsInvalidate,
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IsLlsc, IsRequest, NeedsResponse),
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{ SET7(IsRead, NeedsWritable, IsInvalidate,
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IsLlsc, IsRequest, NeedsResponse, FromCache),
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UpgradeFailResp, "SCUpgradeFailReq" },
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/* UpgradeFailResp - Behaves like a ReadExReq, but notifies an SC
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* that it has failed, acquires line as Dirty*/
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@ -130,7 +133,8 @@ MemCmd::commandInfo[] =
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/* ReadExReq - Read issues by a cache, always cache-line aligned,
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* and the response is guaranteed to be writeable (exclusive or
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* even modified) */
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{ SET5(IsRead, NeedsWritable, IsInvalidate, IsRequest, NeedsResponse),
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{ SET6(IsRead, NeedsWritable, IsInvalidate, IsRequest, NeedsResponse,
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FromCache),
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ReadExResp, "ReadExReq" },
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/* ReadExResp - Response matching a read exclusive, as we check
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* the need for exclusive also on responses */
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@ -139,11 +143,13 @@ MemCmd::commandInfo[] =
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/* ReadCleanReq - Read issued by a cache, always cache-line
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* aligned, and the response is guaranteed to not contain dirty data
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* (exclusive or shared).*/
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{ SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadCleanReq" },
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{ SET4(IsRead, IsRequest, NeedsResponse, FromCache),
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ReadResp, "ReadCleanReq" },
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/* ReadSharedReq - Read issued by a cache, always cache-line
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* aligned, response is shared, possibly exclusive, owned or even
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* modified. */
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{ SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadSharedReq" },
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{ SET4(IsRead, IsRequest, NeedsResponse, FromCache),
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ReadResp, "ReadSharedReq" },
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/* LoadLockedReq: note that we use plain ReadResp as response, so that
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* we can also use ReadRespWithInvalidate when needed */
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{ SET4(IsRead, IsLlsc, IsRequest, NeedsResponse),
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@ -187,7 +193,7 @@ MemCmd::commandInfo[] =
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/* Flush Request */
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{ SET3(IsRequest, IsFlush, NeedsWritable), InvalidCmd, "FlushReq" },
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/* Invalidation Request */
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{ SET4(IsInvalidate, IsRequest, NeedsWritable, NeedsResponse),
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{ SET5(IsInvalidate, IsRequest, NeedsWritable, NeedsResponse, FromCache),
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InvalidateResp, "InvalidateReq" },
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/* Invalidation Response */
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{ SET2(IsInvalidate, IsResponse),
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2015 ARM Limited
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* Copyright (c) 2012-2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -151,6 +151,7 @@ class MemCmd
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IsError, //!< Error response
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IsPrint, //!< Print state matching address (for debugging)
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IsFlush, //!< Flush the address from caches
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FromCache, //!< Request originated from a caching agent
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NUM_COMMAND_ATTRIBUTES
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};
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@ -193,6 +194,7 @@ class MemCmd
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bool needsResponse() const { return testCmdAttrib(NeedsResponse); }
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bool isInvalidate() const { return testCmdAttrib(IsInvalidate); }
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bool isEviction() const { return testCmdAttrib(IsEviction); }
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bool fromCache() const { return testCmdAttrib(FromCache); }
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/**
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* A writeback is an eviction that carries data.
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@ -514,6 +516,7 @@ class Packet : public Printable
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bool needsResponse() const { return cmd.needsResponse(); }
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bool isInvalidate() const { return cmd.isInvalidate(); }
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bool isEviction() const { return cmd.isEviction(); }
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bool fromCache() const { return cmd.fromCache(); }
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bool isWriteback() const { return cmd.isWriteback(); }
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bool hasData() const { return cmd.hasData(); }
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bool hasRespData() const
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