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arm: Correctly check translation mode (aarch64/aarch32)

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According to the ARM ARM (see AArch32.TranslateAddress in the
pseudocode library), the TLB should be operating in aarch64 mode if
the EL0 is aarch32 and EL1 is aarch64. This is currently not the case
in gem5, which breaks 64/32 interprocessing. Update the check to match
the reference manual.

Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
This commit is contained in:
Andreas Sandberg 2016-05-31 12:14:37 +01:00
parent 44e9b81f74
commit 9d4a42e8c5
1 changed files with 8 additions and 4 deletions
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12
src/arch/arm/tlb.cc
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@ -1197,11 +1197,15 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
DPRINTF(TLBVerbose, "TLB variables changed!\n");
cpsr = tc->readMiscReg(MISCREG_CPSR);
// Dependencies: SCR/SCR_EL3, CPSR
isSecure = inSecureState(tc);
isSecure &= (tranType & HypMode) == 0;
isSecure &= (tranType & S1S2NsTran) == 0;
aarch64 = !cpsr.width;
isSecure = inSecureState(tc) &&
!(tranType & HypMode) && !(tranType & S1S2NsTran);
const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode;
aarch64 = opModeIs64(op_mode) ||
(opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1));
if (aarch64) { // AArch64
aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
switch (aarch64EL) {