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cpu, arch: fix the type used for the request flags

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Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Nikos Nikoleris 2016-08-15 12:00:35 +01:00
parent 608a37c844
commit 698767e538
18 changed files with 72 additions and 54 deletions
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4
src/arch/arm/isa.cc
View file

@ -1465,7 +1465,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
case MISCREG_ATS1HR:
case MISCREG_ATS1HW:
{
unsigned flags = 0;
Request::Flags flags = 0;
BaseTLB::Mode mode = BaseTLB::Read;
TLB::ArmTranslationType tranType = TLB::NormalTran;
Fault fault;
@ -1710,7 +1710,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
case MISCREG_AT_S1E3W_Xt:
{
RequestPtr req = new Request;
unsigned flags = 0;
Request::Flags flags = 0;
BaseTLB::Mode mode = BaseTLB::Read;
TLB::ArmTranslationType tranType = TLB::NormalTran;
Fault fault;

11
src/arch/arm/tlb.cc
View file

@ -64,6 +64,7 @@
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
#include "mem/page_table.hh"
#include "mem/request.hh"
#include "params/ArmTLB.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
@ -555,7 +556,7 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
else
vaddr = vaddr_tainted;
uint32_t flags = req->getFlags();
Request::Flags flags = req->getFlags();
bool is_fetch = (mode == Execute);
bool is_write = (mode == Write);
@ -588,7 +589,7 @@ Fault
TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
{
Addr vaddr = req->getVaddr(); // 32-bit don't have to purify
uint32_t flags = req->getFlags();
Request::Flags flags = req->getFlags();
bool is_fetch = (mode == Execute);
bool is_write = (mode == Write);
bool is_priv = isPriv && !(flags & UserMode);
@ -760,7 +761,7 @@ TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
Addr vaddr_tainted = req->getVaddr();
Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
uint32_t flags = req->getFlags();
Request::Flags flags = req->getFlags();
bool is_fetch = (mode == Execute);
bool is_write = (mode == Write);
bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode);
@ -967,7 +968,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
else
vaddr = vaddr_tainted;
uint32_t flags = req->getFlags();
Request::Flags flags = req->getFlags();
bool is_fetch = (mode == Execute);
bool is_write = (mode == Write);
@ -981,7 +982,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran);
DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x "
"flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2,
"flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2,
scr, sctlr, flags, tranType);
if ((req->isInstFetch() && (!sctlr.i)) ||

8
src/arch/generic/memhelpers.hh
View file

@ -54,7 +54,7 @@
template <class XC, class MemT>
Fault
initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
MemT &mem, unsigned flags)
MemT &mem, Request::Flags flags)
{
return xc->initiateMemRead(addr, sizeof(MemT), flags);
}
@ -73,7 +73,7 @@ getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
template <class XC, class MemT>
Fault
readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
unsigned flags)
Request::Flags flags)
{
memset(&mem, 0, sizeof(mem));
Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
@ -89,7 +89,7 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
template <class XC, class MemT>
Fault
writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
unsigned flags, uint64_t *res)
Request::Flags flags, uint64_t *res)
{
if (traceData) {
traceData->setData(mem);
@ -102,7 +102,7 @@ writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
template <class XC, class MemT>
Fault
writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
Addr addr, unsigned flags, uint64_t *res)
Addr addr, Request::Flags flags, uint64_t *res)
{
if (traceData) {
traceData->setData(mem);

10
src/arch/x86/memhelpers.hh
View file

@ -45,7 +45,7 @@ namespace X86ISA
template <class XC>
Fault
initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
unsigned dataSize, unsigned flags)
unsigned dataSize, Request::Flags flags)
{
return xc->initiateMemRead(addr, dataSize, flags);
}
@ -100,7 +100,7 @@ getMem(PacketPtr pkt, std::array<uint64_t, N> &mem, unsigned dataSize,
template <class XC>
Fault
readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem,
unsigned dataSize, unsigned flags)
unsigned dataSize, Request::Flags flags)
{
memset(&mem, 0, sizeof(mem));
Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
@ -142,7 +142,8 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr,
template <class XC>
Fault
writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
unsigned dataSize, Addr addr, Request::Flags flags,
uint64_t *res)
{
if (traceData) {
traceData->setData(mem);
@ -176,7 +177,8 @@ writeMemTiming(XC *xc, Trace::InstRecord *traceData,
template <class XC>
Fault
writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
unsigned dataSize, Addr addr, Request::Flags flags,
uint64_t *res)
{
if (traceData) {
traceData->setData(mem);

2
src/arch/x86/tlb.cc
View file

@ -273,7 +273,7 @@ Fault
TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
Mode mode, bool &delayedResponse, bool timing)
{
uint32_t flags = req->getFlags();
Request::Flags flags = req->getFlags();
int seg = flags & SegmentFlagMask;
bool storeCheck = flags & (StoreCheck << FlagShift);

14
src/cpu/base_dyn_inst.hh
View file

@ -65,6 +65,7 @@
#include "cpu/static_inst.hh"
#include "cpu/translation.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
@ -313,10 +314,10 @@ class BaseDynInst : public ExecContext, public RefCounted
cpu->demapPage(vaddr, asn);
}
Fault initiateMemRead(Addr addr, unsigned size, unsigned flags);
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res);
/** Splits a request in two if it crosses a dcache block. */
void splitRequest(RequestPtr req, RequestPtr &sreqLow,
@ -873,7 +874,8 @@ class BaseDynInst : public ExecContext, public RefCounted
template<class Impl>
Fault
BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, unsigned flags)
BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
Request::Flags flags)
{
instFlags[ReqMade] = true;
Request *req = NULL;
@ -925,8 +927,8 @@ BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, unsigned flags)
template<class Impl>
Fault
BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res)
{
if (traceData)
traceData->setMem(addr, size, flags);

5
src/cpu/checker/cpu.cc
View file

@ -139,7 +139,8 @@ CheckerCPU::unserialize(CheckpointIn &cp)
}
Fault
CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
Request::Flags flags)
{
Fault fault = NoFault;
int fullSize = size;
@ -225,7 +226,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
Fault
CheckerCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
Addr addr, Request::Flags flags, uint64_t *res)
{
Fault fault = NoFault;
bool checked_flags = false;

7
src/cpu/checker/cpu.hh
View file

@ -57,6 +57,7 @@
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "debug/Checker.hh"
#include "mem/request.hh"
#include "params/CheckerCPU.hh"
#include "sim/eventq.hh"
@ -374,9 +375,9 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
Fault readMem(Addr addr, uint8_t *data, unsigned size,
unsigned flags) override;
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res) override;
Request::Flags flags) override;
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res) override;
unsigned int readStCondFailures() const override {
return thread->readStCondFailures();

7
src/cpu/exec_context.hh
View file

@ -51,6 +51,7 @@
#include "cpu/base.hh"
#include "cpu/static_inst_fwd.hh"
#include "cpu/translation.hh"
#include "mem/request.hh"
/**
* The ExecContext is an abstract base class the provides the
@ -182,7 +183,7 @@ class ExecContext {
* should never be called).
*/
virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
unsigned int flags)
Request::Flags flags)
{
panic("ExecContext::readMem() should be overridden\n");
}
@ -195,7 +196,7 @@ class ExecContext {
* should never be called).
*/
virtual Fault initiateMemRead(Addr addr, unsigned int size,
unsigned int flags)
Request::Flags flags)
{
panic("ExecContext::initiateMemRead() should be overridden\n");
}
@ -205,7 +206,7 @@ class ExecContext {
* For timing-mode contexts, initiate a timing memory write operation.
*/
virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
unsigned int flags, uint64_t *res) = 0;
Request::Flags flags, uint64_t *res) = 0;
/**
* Sets the number of consecutive store conditional failures.

5
src/cpu/minor/exec_context.hh
View file

@ -58,6 +58,7 @@
#include "cpu/minor/pipeline.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "mem/request.hh"
#include "debug/MinorExecute.hh"
namespace Minor
@ -103,7 +104,7 @@ class ExecContext : public ::ExecContext
}
Fault
initiateMemRead(Addr addr, unsigned int size, unsigned int flags)
initiateMemRead(Addr addr, unsigned int size, Request::Flags flags)
{
execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
size, addr, flags, NULL);
@ -112,7 +113,7 @@ class ExecContext : public ::ExecContext
Fault
writeMem(uint8_t *data, unsigned int size, Addr addr,
unsigned int flags, uint64_t *res)
Request::Flags flags, uint64_t *res)
{
execute.getLSQ().pushRequest(inst, false /* store */, data,
size, addr, flags, res);

3
src/cpu/minor/lsq.cc
View file

@ -1471,7 +1471,8 @@ LSQ::needsToTick()
void
LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
unsigned int size, Addr addr, unsigned int flags, uint64_t *res)
unsigned int size, Addr addr, Request::Flags flags,
uint64_t *res)
{
bool needs_burst = transferNeedsBurst(addr, size, lineWidth);
LSQRequestPtr request;

3
src/cpu/minor/lsq.hh
View file

@ -712,7 +712,8 @@ class LSQ : public Named
/** Single interface for readMem/writeMem to issue requests into
* the LSQ */
void pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
unsigned int size, Addr addr, unsigned int flags, uint64_t *res);
unsigned int size, Addr addr, Request::Flags flags,
uint64_t *res);
/** Push a predicate failed-representing request into the queues just
* to maintain commit order */

11
src/cpu/simple/atomic.cc
View file

@ -334,8 +334,8 @@ AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
}
Fault
AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
unsigned size, unsigned flags)
AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
Request::Flags flags)
{
SimpleExecContext& t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
@ -422,15 +422,16 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
}
Fault
AtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
AtomicSimpleCPU::initiateMemRead(Addr addr, unsigned size,
Request::Flags flags)
{
panic("initiateMemRead() is for timing accesses, and should "
"never be called on AtomicSimpleCPU.\n");
}
Fault
AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res)
{
SimpleExecContext& t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;

8
src/cpu/simple/atomic.hh
View file

@ -45,6 +45,7 @@
#include "cpu/simple/base.hh"
#include "cpu/simple/exec_context.hh"
#include "mem/request.hh"
#include "params/AtomicSimpleCPU.hh"
#include "sim/probe/probe.hh"
@ -202,12 +203,13 @@ class AtomicSimpleCPU : public BaseSimpleCPU
void suspendContext(ThreadID thread_num) override;
Fault readMem(Addr addr, uint8_t *data, unsigned size,
unsigned flags) override;
Request::Flags flags) override;
Fault initiateMemRead(Addr addr, unsigned size, unsigned flags) override;
Fault initiateMemRead(Addr addr, unsigned size,
Request::Flags flags) override;
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res) override;
Addr addr, Request::Flags flags, uint64_t *res) override;
void regProbePoints() override;

7
src/cpu/simple/base.hh
View file

@ -143,12 +143,13 @@ class BaseSimpleCPU : public BaseCPU
void startup() override;
virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
unsigned flags) = 0;
Request::Flags flags) = 0;
virtual Fault initiateMemRead(Addr addr, unsigned size, unsigned flags) = 0;
virtual Fault initiateMemRead(Addr addr, unsigned size,
Request::Flags flags) = 0;
virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr,
unsigned flags, uint64_t* res) = 0;
Request::Flags flags, uint64_t* res) = 0;
void countInst();
Counter totalInsts() const override;

7
src/cpu/simple/exec_context.hh
View file

@ -53,6 +53,7 @@
#include "cpu/simple/base.hh"
#include "cpu/static_inst_fwd.hh"
#include "cpu/translation.hh"
#include "mem/request.hh"
class BaseSimpleCPU;
@ -286,19 +287,19 @@ class SimpleExecContext : public ExecContext {
{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
Fault readMem(Addr addr, uint8_t *data, unsigned int size,
unsigned int flags) override
Request::Flags flags) override
{
return cpu->readMem(addr, data, size, flags);
}
Fault initiateMemRead(Addr addr, unsigned int size,
unsigned int flags) override
Request::Flags flags) override
{
return cpu->initiateMemRead(addr, size, flags);
}
Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
unsigned int flags, uint64_t *res) override
Request::Flags flags, uint64_t *res) override
{
return cpu->writeMem(data, size, addr, flags, res);
}

7
src/cpu/simple/timing.cc
View file

@ -409,14 +409,15 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
Fault
TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
unsigned size, unsigned flags)
unsigned size, Request::Flags flags)
{
panic("readMem() is for atomic accesses, and should "
"never be called on TimingSimpleCPU.\n");
}
Fault
TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
Request::Flags flags)
{
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
@ -489,7 +490,7 @@ TimingSimpleCPU::handleWritePacket()
Fault
TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
Addr addr, Request::Flags flags, uint64_t *res)
{
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;

7
src/cpu/simple/timing.hh
View file

@ -279,12 +279,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
void suspendContext(ThreadID thread_num) override;
Fault readMem(Addr addr, uint8_t *data, unsigned size,
unsigned flags) override;
Request::Flags flags) override;
Fault initiateMemRead(Addr addr, unsigned size, unsigned flags) override;
Fault initiateMemRead(Addr addr, unsigned size,
Request::Flags flags) override;
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res) override;
Addr addr, Request::Flags flags, uint64_t *res) override;
void fetch();
void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);