dev, arm: Update GIC to use GICv2 register naming
The GICv2 has a new and slightly more consistent register naming. Update gem5's GIC register names to match the new documentation. Change-Id: I8ef114eee8a95bf0b88b37c18a18e137be78675a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
This commit is contained in:
Andreas Sandberg
parent
a46f77e695
commit
84cfa10b15
2 changed files with 101 additions and 95 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010, 2013, 2015 ARM Limited
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* Copyright (c) 2010, 2013, 2015-2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -144,39 +144,39 @@ Pl390::readDistributor(PacketPtr pkt)
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DPRINTF(GIC, "gic distributor read register %#x\n", daddr);
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if (daddr >= ICDISER_ST && daddr < ICDISER_ED + 4) {
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assert((daddr-ICDISER_ST) >> 2 < 32);
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pkt->set<uint32_t>(intEnabled[(daddr-ICDISER_ST)>>2]);
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if (daddr >= GICD_ISENABLER_ST && daddr < GICD_ISENABLER_ED + 4) {
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assert((daddr-GICD_ISENABLER_ST) >> 2 < 32);
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pkt->set<uint32_t>(intEnabled[(daddr-GICD_ISENABLER_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDICER_ST && daddr < ICDICER_ED + 4) {
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assert((daddr-ICDICER_ST) >> 2 < 32);
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pkt->set<uint32_t>(intEnabled[(daddr-ICDICER_ST)>>2]);
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if (daddr >= GICD_ICENABLER_ST && daddr < GICD_ICENABLER_ED + 4) {
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assert((daddr-GICD_ICENABLER_ST) >> 2 < 32);
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pkt->set<uint32_t>(intEnabled[(daddr-GICD_ICENABLER_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDISPR_ST && daddr < ICDISPR_ED + 4) {
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assert((daddr-ICDISPR_ST) >> 2 < 32);
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pkt->set<uint32_t>(pendingInt[(daddr-ICDISPR_ST)>>2]);
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if (daddr >= GICD_ISPENDR_ST && daddr < GICD_ISPENDR_ED + 4) {
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assert((daddr-GICD_ISPENDR_ST) >> 2 < 32);
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pkt->set<uint32_t>(pendingInt[(daddr-GICD_ISPENDR_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDICPR_ST && daddr < ICDICPR_ED + 4) {
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assert((daddr-ICDICPR_ST) >> 2 < 32);
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pkt->set<uint32_t>(pendingInt[(daddr-ICDICPR_ST)>>2]);
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if (daddr >= GICD_ICPENDR_ST && daddr < GICD_ICPENDR_ED + 4) {
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assert((daddr-GICD_ICPENDR_ST) >> 2 < 32);
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pkt->set<uint32_t>(pendingInt[(daddr-GICD_ICPENDR_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDABR_ST && daddr < ICDABR_ED + 4) {
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assert((daddr-ICDABR_ST) >> 2 < 32);
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pkt->set<uint32_t>(activeInt[(daddr-ICDABR_ST)>>2]);
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if (daddr >= GICD_ISACTIVER_ST && daddr < GICD_ISACTIVER_ED + 4) {
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assert((daddr-GICD_ISACTIVER_ST) >> 2 < 32);
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pkt->set<uint32_t>(activeInt[(daddr-GICD_ISACTIVER_ST)>>2]);
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goto done;
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}
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if (daddr >= ICDIPR_ST && daddr < ICDIPR_ED + 4) {
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if (daddr >= GICD_IPRIORITYR_ST && daddr < GICD_IPRIORITYR_ED + 4) {
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Addr int_num;
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int_num = daddr - ICDIPR_ST;
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int_num = daddr - GICD_IPRIORITYR_ST;
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assert(int_num < INT_LINES_MAX);
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DPRINTF(Interrupt, "Reading interrupt priority at int# %#x \n",int_num);
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@ -209,9 +209,9 @@ Pl390::readDistributor(PacketPtr pkt)
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goto done;
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}
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if (daddr >= ICDIPTR_ST && daddr < ICDIPTR_ED + 4) {
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if (daddr >= GICD_ITARGETSR_ST && daddr < GICD_ITARGETSR_ED + 4) {
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Addr int_num;
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int_num = (daddr-ICDIPTR_ST) ;
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int_num = (daddr-GICD_ITARGETSR_ST) ;
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DPRINTF(GIC, "Reading processor target register for int# %#x \n",
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int_num);
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assert(int_num < INT_LINES_MAX);
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@ -245,20 +245,20 @@ Pl390::readDistributor(PacketPtr pkt)
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goto done;
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}
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if (daddr >= ICDICFR_ST && daddr < ICDICFR_ED + 4) {
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assert((daddr-ICDICFR_ST) >> 2 < 64);
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if (daddr >= GICD_ICFGR_ST && daddr < GICD_ICFGR_ED + 4) {
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assert((daddr-GICD_ICFGR_ST) >> 2 < 64);
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/** @todo software generated interrutps and PPIs
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* can't be configured in some ways
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*/
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pkt->set<uint32_t>(intConfig[(daddr-ICDICFR_ST)>>2]);
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pkt->set<uint32_t>(intConfig[(daddr-GICD_ICFGR_ST)>>2]);
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goto done;
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}
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switch(daddr) {
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case ICDDCR:
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case GICD_CTLR:
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pkt->set<uint32_t>(enabled);
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break;
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case ICDICTR:
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case GICD_TYPER:
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uint32_t tmp;
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tmp = ((sys->numRunningContexts() - 1) << 5) |
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(itLines/INT_BITS_MAX -1) |
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@ -291,19 +291,19 @@ Pl390::readCpu(PacketPtr pkt)
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ctx_id);
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switch(daddr) {
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case ICCIIDR:
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case GICC_IIDR:
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pkt->set<uint32_t>(0);
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break;
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case ICCICR:
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case GICC_CTLR:
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pkt->set<uint32_t>(cpuEnabled[ctx_id]);
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break;
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case ICCPMR:
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case GICC_PMR:
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pkt->set<uint32_t>(cpuPriority[ctx_id]);
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break;
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case ICCBPR:
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case GICC_BPR:
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pkt->set<uint32_t>(cpuBpr[ctx_id]);
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break;
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case ICCIAR:
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case GICC_IAR:
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if (enabled && cpuEnabled[ctx_id]) {
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int active_int = cpuHighestInt[ctx_id];
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IAR iar = 0;
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@ -356,10 +356,10 @@ Pl390::readCpu(PacketPtr pkt)
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}
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break;
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case ICCRPR:
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case GICC_RPR:
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pkt->set<uint32_t>(iccrpr[0]);
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break;
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case ICCHPIR:
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case GICC_HPPIR:
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pkt->set<uint32_t>(0);
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panic("Need to implement HPIR");
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break;
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@ -399,36 +399,36 @@ Pl390::writeDistributor(PacketPtr pkt)
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DPRINTF(GIC, "gic distributor write register %#x size %#x value %#x \n",
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daddr, pkt->getSize(), pkt_data);
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if (daddr >= ICDISER_ST && daddr < ICDISER_ED + 4) {
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assert((daddr-ICDISER_ST) >> 2 < 32);
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intEnabled[(daddr-ICDISER_ST) >> 2] |= pkt->get<uint32_t>();
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if (daddr >= GICD_ISENABLER_ST && daddr < GICD_ISENABLER_ED + 4) {
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assert((daddr-GICD_ISENABLER_ST) >> 2 < 32);
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intEnabled[(daddr-GICD_ISENABLER_ST) >> 2] |= pkt->get<uint32_t>();
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goto done;
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}
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if (daddr >= ICDICER_ST && daddr < ICDICER_ED + 4) {
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assert((daddr-ICDICER_ST) >> 2 < 32);
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intEnabled[(daddr-ICDICER_ST) >> 2] &= ~pkt->get<uint32_t>();
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if (daddr >= GICD_ICENABLER_ST && daddr < GICD_ICENABLER_ED + 4) {
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assert((daddr-GICD_ICENABLER_ST) >> 2 < 32);
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intEnabled[(daddr-GICD_ICENABLER_ST) >> 2] &= ~pkt->get<uint32_t>();
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goto done;
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}
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if (daddr >= ICDISPR_ST && daddr < ICDISPR_ED + 4) {
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assert((daddr-ICDISPR_ST) >> 2 < 32);
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pendingInt[(daddr-ICDISPR_ST) >> 2] |= pkt->get<uint32_t>();
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if (daddr >= GICD_ISPENDR_ST && daddr < GICD_ISPENDR_ED + 4) {
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assert((daddr-GICD_ISPENDR_ST) >> 2 < 32);
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pendingInt[(daddr-GICD_ISPENDR_ST) >> 2] |= pkt->get<uint32_t>();
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pendingInt[0] &= SGI_MASK; // Don't allow SGIs to be changed
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updateIntState((daddr-ICDISPR_ST) >> 2);
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updateIntState((daddr-GICD_ISPENDR_ST) >> 2);
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goto done;
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}
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if (daddr >= ICDICPR_ST && daddr < ICDICPR_ED + 4) {
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assert((daddr-ICDICPR_ST) >> 2 < 32);
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pendingInt[(daddr-ICDICPR_ST) >> 2] &= ~pkt->get<uint32_t>();
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if (daddr >= GICD_ICPENDR_ST && daddr < GICD_ICPENDR_ED + 4) {
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assert((daddr-GICD_ICPENDR_ST) >> 2 < 32);
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pendingInt[(daddr-GICD_ICPENDR_ST) >> 2] &= ~pkt->get<uint32_t>();
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pendingInt[0] &= SGI_MASK; // Don't allow SGIs to be changed
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updateIntState((daddr-ICDICPR_ST) >> 2);
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updateIntState((daddr-GICD_ICPENDR_ST) >> 2);
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goto done;
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}
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if (daddr >= ICDIPR_ST && daddr < ICDIPR_ED + 4) {
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Addr int_num = daddr - ICDIPR_ST;
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if (daddr >= GICD_IPRIORITYR_ST && daddr < GICD_IPRIORITYR_ED + 4) {
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Addr int_num = daddr - GICD_IPRIORITYR_ST;
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assert(int_num < INT_LINES_MAX);
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uint8_t* int_p;
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if (int_num < (SGI_MAX + PPI_MAX))
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@ -463,8 +463,8 @@ Pl390::writeDistributor(PacketPtr pkt)
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goto done;
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}
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if (daddr >= ICDIPTR_ST && daddr < ICDIPTR_ED + 4) {
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Addr int_num = (daddr-ICDIPTR_ST) ;
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if (daddr >= GICD_ITARGETSR_ST && daddr < GICD_ITARGETSR_ED + 4) {
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Addr int_num = (daddr-GICD_ITARGETSR_ST) ;
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assert(int_num < INT_LINES_MAX);
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// First 31 interrupts only target single processor
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if (int_num >= SGI_MAX) {
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@ -480,32 +480,32 @@ Pl390::writeDistributor(PacketPtr pkt)
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cpuTarget[int_num+2] = bits(tmp, 23, 16);
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cpuTarget[int_num+3] = bits(tmp, 31, 24);
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}
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updateIntState((daddr-ICDIPTR_ST)>>2);
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updateIntState((daddr-GICD_ITARGETSR_ST)>>2);
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}
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goto done;
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}
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if (daddr >= ICDICFR_ST && daddr < ICDICFR_ED + 4) {
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assert((daddr-ICDICFR_ST) >> 2 < 64);
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intConfig[(daddr-ICDICFR_ST)>>2] = pkt->get<uint32_t>();
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if (daddr >= GICD_ICFGR_ST && daddr < GICD_ICFGR_ED + 4) {
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assert((daddr-GICD_ICFGR_ST) >> 2 < 64);
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intConfig[(daddr-GICD_ICFGR_ST)>>2] = pkt->get<uint32_t>();
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if (pkt->get<uint32_t>() & NN_CONFIG_MASK)
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warn("GIC N:N mode selected and not supported at this time\n");
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goto done;
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}
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switch(daddr) {
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case ICDDCR:
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case GICD_CTLR:
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enabled = pkt->get<uint32_t>();
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DPRINTF(Interrupt, "Distributor enable flag set to = %d\n", enabled);
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break;
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case ICDICTR:
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case GICD_TYPER:
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/* 0x200 is a made-up flag to enable gem5 extension functionality.
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* This reg is not normally written.
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*/
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gem5ExtensionsEnabled = !!(pkt->get<uint32_t>() & 0x200);
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DPRINTF(GIC, "gem5 extensions %s\n", gem5ExtensionsEnabled ? "enabled" : "disabled");
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break;
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case ICDSGIR:
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case GICD_SGIR:
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softInt(ctx_id, pkt->get<uint32_t>());
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break;
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default:
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@ -531,16 +531,16 @@ Pl390::writeCpu(PacketPtr pkt)
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ctx_id, daddr, pkt->get<uint32_t>());
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switch(daddr) {
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case ICCICR:
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case GICC_CTLR:
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cpuEnabled[ctx_id] = pkt->get<uint32_t>();
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break;
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case ICCPMR:
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case GICC_PMR:
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cpuPriority[ctx_id] = pkt->get<uint32_t>();
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break;
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case ICCBPR:
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case GICC_BPR:
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cpuBpr[ctx_id] = pkt->get<uint32_t>();
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break;
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case ICCEOIR:
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case GICC_EOIR:
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iar = pkt->get<uint32_t>();
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if (iar.ack_id < SGI_MAX) {
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// Clear out the bit that corrseponds to the cleared int
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@ -665,7 +665,7 @@ Pl390::updateIntState(int hint)
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/*@todo use hint to do less work. */
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int highest_int = SPURIOUS_INT;
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// Priorities below that set in ICCPMR can be ignored
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// Priorities below that set in GICC_PMR can be ignored
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uint8_t highest_pri = cpuPriority[cpu];
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// Check SGIs
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010, 2013, 2015 ARM Limited
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* Copyright (c) 2010, 2013, 2015-2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -65,39 +65,45 @@ class Pl390 : public BaseGic
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{
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protected:
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// distributor memory addresses
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static const int ICDDCR = 0x000; // control register
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static const int ICDICTR = 0x004; // controller type
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static const int ICDIIDR = 0x008; // implementer id
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static const int ICDISER_ST = 0x100; // interrupt set enable
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static const int ICDISER_ED = 0x17c;
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static const int ICDICER_ST = 0x180; // interrupt clear enable
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static const int ICDICER_ED = 0x1fc;
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static const int ICDISPR_ST = 0x200; // set pending interrupt
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static const int ICDISPR_ED = 0x27c;
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static const int ICDICPR_ST = 0x280; // clear pending interrupt
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static const int ICDICPR_ED = 0x2fc;
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static const int ICDABR_ST = 0x300; // active bit registers
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static const int ICDABR_ED = 0x37c;
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static const int ICDIPR_ST = 0x400; // interrupt priority registers
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static const int ICDIPR_ED = 0x7f8;
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static const int ICDIPTR_ST = 0x800; // processor target registers
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static const int ICDIPTR_ED = 0xbf8;
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static const int ICDICFR_ST = 0xc00; // interrupt config registers
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static const int ICDICFR_ED = 0xcfc;
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static const int ICDSGIR = 0xf00; // software generated interrupt
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static const int DIST_SIZE = 0xfff;
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enum {
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GICD_CTLR = 0x000, // control register
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GICD_TYPER = 0x004, // controller type
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GICD_IIDR = 0x008, // implementer id
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GICD_ISENABLER_ST = 0x100, // interrupt set enable
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GICD_ISENABLER_ED = 0x17c,
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GICD_ICENABLER_ST = 0x180, // interrupt clear enable
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GICD_ICENABLER_ED = 0x1fc,
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GICD_ISPENDR_ST = 0x200, // set pending interrupt
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GICD_ISPENDR_ED = 0x27c,
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GICD_ICPENDR_ST = 0x280, // clear pending interrupt
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GICD_ICPENDR_ED = 0x2fc,
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GICD_ISACTIVER_ST = 0x300, // active bit registers
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GICD_ISACTIVER_ED = 0x37c,
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GICD_IPRIORITYR_ST = 0x400, // interrupt priority registers
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GICD_IPRIORITYR_ED = 0x7f8,
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GICD_ITARGETSR_ST = 0x800, // processor target registers
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GICD_ITARGETSR_ED = 0xbf8,
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GICD_ICFGR_ST = 0xc00, // interrupt config registers
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GICD_ICFGR_ED = 0xcfc,
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GICD_SGIR = 0xf00, // software generated interrupt
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DIST_SIZE = 0xfff
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};
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// cpu memory addressesa
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static const int ICCICR = 0x00; // CPU control register
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static const int ICCPMR = 0x04; // Interrupt priority mask
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static const int ICCBPR = 0x08; // binary point register
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static const int ICCIAR = 0x0C; // interrupt ack register
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static const int ICCEOIR = 0x10; // end of interrupt
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static const int ICCRPR = 0x14; // runing priority
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static const int ICCHPIR = 0x18; // highest pending interrupt
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static const int ICCABPR = 0x1c; // aliased binary point
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static const int ICCIIDR = 0xfc; // cpu interface id register
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static const int CPU_SIZE = 0xff;
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enum {
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GICC_CTLR = 0x00, // CPU control register
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GICC_PMR = 0x04, // Interrupt priority mask
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GICC_BPR = 0x08, // binary point register
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GICC_IAR = 0x0C, // interrupt ack register
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GICC_EOIR = 0x10, // end of interrupt
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GICC_RPR = 0x14, // runing priority
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GICC_HPPIR = 0x18, // highest pending interrupt
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GICC_ABPR = 0x1c, // aliased binary point
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GICC_IIDR = 0xfc, // cpu interface id register
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CPU_SIZE = 0xff
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};
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static const int SGI_MAX = 16; // Number of Software Gen Interrupts
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static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
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@ -105,7 +111,7 @@ class Pl390 : public BaseGic
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/** Mask off SGI's when setting/clearing pending bits */
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static const int SGI_MASK = 0xFFFF0000;
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/** Mask for bits that config N:N mode in ICDICFR's */
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/** Mask for bits that config N:N mode in GICD_ICFGR's */
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static const int NN_CONFIG_MASK = 0x55555555;
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static const int CPU_MAX = 256; // Max number of supported CPU interfaces
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