mem: different HMC configuration
In this new hmc configuration we have used the existing components in gem5 mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different architecture for HMC. Highlights 1- It explores 3 different HMC architectures 2- It creates 4-HMC crossbars and attaches 16 vault controllers with it. This will connect vaults to serial links 3- From the previous version, HMCController with round robin funtionality is being removed and all the serial links are being accessible directly from user ports 4- Latency incorporated by HMCController (in previous version) is being added to SerialLink Committed by Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Abdul Mutaal Ahmad
parent
1051223318
commit
7cb0c7bd65
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@ -37,6 +37,7 @@
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Erfan Azarkhish
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# Abdul Mutaal Ahmad
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# A Simplified model of a complete HMC device. Based on:
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# [1] http://www.hybridmemorycube.org/specification-download/
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@ -48,6 +49,10 @@
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# (G. Kim et. al)
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# [5] Near Data Processing, Are we there yet? (M. Gokhale)
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# http://www.cs.utah.edu/wondp/gokhale.pdf
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# [6] openHMC - A Configurable Open-Source Hybrid Memory Cube Controller
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# (J. Schmidt)
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# [7] Hybrid Memory Cube performance characterization on data-centric
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# workloads (M. Gokhale)
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#
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# This script builds a complete HMC device composed of vault controllers,
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# serial links, the main internal crossbar, and an external hmc controller.
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@ -60,23 +65,62 @@
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# This component is simply an instance of the NoncoherentXBar class, and its
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# parameters are tuned to [2].
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#
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# - SERIAL LINKS:
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# - SERIAL LINKS CONTROLLER:
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# SerialLink is a simple variation of the Bridge class, with the ability to
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# account for the latency of packet serialization. We assume that the
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# serializer component at the transmitter side does not need to receive the
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# whole packet to start the serialization. But the deserializer waits for
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# the complete packet to check its integrity first.
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# * Bandwidth of the serial links is not modeled in the SerialLink component
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# itself. Instead bandwidth/port of the HMCController has been adjusted to
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# reflect the bandwidth delivered by 1 serial link.
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# account for the latency of packet serialization and controller latency. We
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# assume that the serializer component at the transmitter side does not need
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# to receive the whole packet to start the serialization. But the
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# deserializer waits for the complete packet to check its integrity first.
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#
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# * Bandwidth of the serial links is not modeled in the SerialLink component
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# itself.
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#
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# * Latency of serial link controller is composed of SerDes latency + link
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# controller
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#
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# - HMC CONTROLLER:
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# Contains a large buffer (modeled with Bridge) to hide the access latency
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# of the memory cube. Plus it simply forwards the packets to the serial
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# links in a round-robin fashion to balance load among them.
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# * It is inferred from the standard [1] and the literature [3] that serial
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# links share the same address range and packets can travel over any of
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# them so a load distribution mechanism is required among them.
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#
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# -----------------------------------------
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# | Host/HMC Controller |
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# | ---------------------- |
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# | | Link Aggregator | opt |
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# | ---------------------- |
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# | ---------------------- |
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# | | Serial Link + Ser | * 4 |
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# | ---------------------- |
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# |---------------------------------------
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# -----------------------------------------
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# | Device
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# | ---------------------- |
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# | | Xbar | * 4 |
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# | ---------------------- |
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# | ---------------------- |
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# | | Vault Controller | * 16 |
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# | ---------------------- |
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# | ---------------------- |
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# | | Memory | |
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# | ---------------------- |
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# |---------------------------------------|
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#
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# In this version we have present 3 different HMC archiecture along with
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# alongwith their corresponding test script.
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#
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# same: It has 4 crossbars in HMC memory. All the crossbars are connected
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# to each other, providing complete memory range. This archicture also covers
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# the added latency for sending a request to non-local vault(bridge in b/t
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# crossbars). All the 4 serial links can access complete memory. So each
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# link can be connected to separate processor.
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#
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# distributed: It has 4 crossbars inside the HMC. Crossbars are not
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# connected.Through each crossbar only local vaults can be accessed. But to
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# support this architecture we need a crossbar between serial links and
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# processor.
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#
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# mixed: This is a hybrid architecture. It has 4 crossbars inside the HMC.
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# 2 Crossbars are connected to only local vaults. From other 2 crossbar, a
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# request can be forwarded to any other vault.
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import optparse
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@ -107,131 +151,277 @@ class HMCSystem(SubSystem):
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# FIFOs at the input and output of the inteconnect)
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xbar_response_latency = Param.Cycles(2, "Response latency of the XBar")
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#*****************************SERIAL LINK PARAMETERS**********************
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# Number of serial links [1]
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num_serial_links = Param.Unsigned(4, "Number of serial links")
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# number of cross which connects 16 Vaults to serial link[7]
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number_mem_crossbar = Param.Unsigned(4, "Number of crossbar in HMC"
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)
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#*****************************SERIAL LINK PARAMETERS***********************
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# Number of serial links controllers [1]
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num_links_controllers = Param.Unsigned(4, "Number of serial links")
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# Number of packets (not flits) to store at the request side of the serial
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# link. This number should be adjusted to achive required bandwidth
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link_buffer_size_req = Param.Unsigned(16, "Number of packets to buffer "
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link_buffer_size_req = Param.Unsigned(10, "Number of packets to buffer "
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"at the request side of the serial link")
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# Number of packets (not flits) to store at the response side of the serial
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# link. This number should be adjusted to achive required bandwidth
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link_buffer_size_rsp = Param.Unsigned(16, "Number of packets to buffer "
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link_buffer_size_rsp = Param.Unsigned(10, "Number of packets to buffer "
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"at the response side of the serial link")
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# Latency of the serial link composed by SER/DES latency (1.6ns [4]) plus
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# the PCB trace latency (3ns Estimated based on [5])
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link_latency = Param.Latency('4.6ns', "Latency of the serial links")
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# Header overhead of the serial links: Header size is 128bits in HMC [1],
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# and we have 16 lanes, so the overhead is 8 cycles
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link_overhead = Param.Cycles(8, "The number of cycles required to"
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" transmit the packet header over the serial link")
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# Clock frequency of the serial links [1]
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# Clock frequency of the each serial link(SerDes) [1]
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link_frequency = Param.Frequency('10GHz', "Clock Frequency of the serial"
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"links")
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# Clock frequency of serial link Controller[6]
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# clk_hmc[Mhz]= num_lanes_per_link * lane_speed [Gbits/s] /
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# data_path_width * 10^6
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# clk_hmc[Mhz]= 16 * 10 Gbps / 256 * 10^6 = 625 Mhz
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link_controller_frequency = Param.Frequency('625MHz',
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"Clock Frequency of the link controller")
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# Latency of the serial link controller to process the packets[1][6]
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# (ClockDomain = 625 Mhz )
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# used here for calculations only
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link_ctrl_latency = Param.Cycles(4, "The number of cycles required for the"
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"controller to process the packet")
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# total_ctrl_latency = link_ctrl_latency + link_latency
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# total_ctrl_latency = 4(Cycles) * 1.6 ns + 4.6 ns
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total_ctrl_latency = Param.Latency('11ns', "The latency experienced by"
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"every packet regardless of size of packet")
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# Number of parallel lanes in each serial link [1]
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num_lanes_per_link = Param.Unsigned(16, "Number of lanes per each link")
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num_lanes_per_link = Param.Unsigned( 16, "Number of lanes per each link")
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# Number of serial links [1]
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num_serial_links = Param.Unsigned(4, "Number of serial links")
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num_serial_links = Param.Unsigned(4, "Number of serial links")
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#*****************************HMC CONTROLLER PARAMETERS*******************
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# Number of packets (not flits) to store at the HMC controller. This
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# number should be high enough to be able to hide the high latency of HMC
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ctrl_buffer_size_req = Param.Unsigned(256, "Number of packets to buffer "
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"at the HMC controller (request side)")
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# speed of each lane of serial link - SerDes serial interface 10 Gb/s
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serial_link_speed = Param.UInt64(10, "Gbs/s speed of each lane of"
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"serial link")
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# Number of packets (not flits) to store at the response side of the HMC
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# controller.
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ctrl_buffer_size_rsp = Param.Unsigned(256, "Number of packets to buffer "
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"at the HMC controller (response side)")
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# Latency of the HMC controller to process the packets
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# (ClockDomain = Host clock domain)
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ctrl_latency = Param.Cycles(4, "The number of cycles required for the "
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" controller to process the packet")
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# Wiring latency from the SoC crossbar to the HMC controller
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ctrl_static_latency = Param.Latency('500ps', "Static latency of the HMC"
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"controller")
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#*****************************PERFORMANCE MONITORING**********************
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#*****************************PERFORMANCE MONITORING************************
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# The main monitor behind the HMC Controller
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enable_global_monitor = Param.Bool(True, "The main monitor behind the "
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enable_global_monitor = Param.Bool(False, "The main monitor behind the "
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"HMC Controller")
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# The link performance monitors
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enable_link_monitor = Param.Bool(True, "The link monitors")
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enable_link_monitor = Param.Bool(False, "The link monitors" )
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# link aggregator enable - put a cross between buffers & links
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enable_link_aggr = Param.Bool(False, "The crossbar between port and "
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"Link Controller")
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enable_buff_div = Param.Bool(True, "Memory Range of Buffer is"
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"divided between total range")
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#*****************************HMC ARCHITECTURE ************************
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# Memory chunk for 16 vault - numbers of vault / number of crossbars
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mem_chunk = Param.Unsigned(4, "Chunk of memory range for each cross bar "
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"in arch 0")
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# size of req buffer within crossbar, used for modelling extra latency
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# when the reuqest go to non-local vault
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xbar_buffer_size_req = Param.Unsigned(10, "Number of packets to buffer "
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"at the request side of the crossbar")
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# size of response buffer within crossbar, used for modelling extra latency
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# when the response received from non-local vault
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xbar_buffer_size_resp = Param.Unsigned(10, "Number of packets to buffer "
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"at the response side of the crossbar")
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# configure host system with Serial Links
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def config_host_hmc(options, system):
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system.hmc_host=HMCSystem()
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try:
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system.hmc_host.enable_global_monitor = options.enable_global_monitor
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except:
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pass;
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try:
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system.hmc_host.enable_link_monitor = options.enable_link_monitor
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except:
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pass;
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# Serial link Controller with 16 SerDes links at 10 Gbps
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# with serial link ranges w.r.t to architecture
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system.hmc_host.seriallink = [SerialLink(ranges = options.ser_ranges[i],
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req_size=system.hmc_host.link_buffer_size_req,
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resp_size=system.hmc_host.link_buffer_size_rsp,
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num_lanes=system.hmc_host.num_lanes_per_link,
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link_speed=system.hmc_host.serial_link_speed,
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delay=system.hmc_host.total_ctrl_latency)
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for i in xrange(system.hmc_host.num_serial_links)]
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# enable global monitor
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if system.hmc_host.enable_global_monitor:
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system.hmc_host.lmonitor = [ CommMonitor()
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for i in xrange(system.hmc_host.num_serial_links)]
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# set the clock frequency for serial link
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for i in xrange(system.hmc_host.num_serial_links):
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system.hmc_host.seriallink[i].clk_domain = SrcClockDomain(clock=system.
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hmc_host.link_controller_frequency, voltage_domain=
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VoltageDomain(voltage = '1V'))
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# Connect membus/traffic gen to Serial Link Controller for differrent HMC
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# architectures
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if options.arch == "distributed":
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for i in xrange(system.hmc_host.num_links_controllers):
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if system.hmc_host.enable_global_monitor:
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system.membus.master = system.hmc_host.lmonitor[i].slave
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system.hmc_host.lmonitor[i].master = \
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system.hmc_host.seriallink[i].slave
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else:
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system.membus.master = system.hmc_host.seriallink[i].slave
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if options.arch == "mixed":
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if system.hmc_host.enable_global_monitor:
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system.membus.master = system.hmc_host.lmonitor[0].slave
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system.hmc_host.lmonitor[0].master = \
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system.hmc_host.seriallink[0].slave
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system.membus.master = system.hmc_host.lmonitor[1].slave
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system.hmc_host.lmonitor[1].master = \
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system.hmc_host.seriallink[1].slave
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system.tgen[2].port = system.hmc_host.lmonitor[2].slave
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system.hmc_host.lmonitor[2].master = \
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system.hmc_host.seriallink[2].slave
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system.tgen[3].port = system.hmc_host.lmonitor[3].slave
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system.hmc_host.lmonitor[3].master = \
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system.hmc_host.seriallink[3].slave
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else:
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system.membus.master = system.hmc_host.seriallink[0].slave
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system.membus.master = system.hmc_host.seriallink[1].slave
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system.tgen[2].port = system.hmc_host.seriallink[2].slave
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system.tgen[3].port = system.hmc_host.seriallink[3].slave
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if options.arch == "same" :
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for i in xrange(system.hmc_host.num_links_controllers):
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if system.hmc_host.enable_global_monitor:
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system.tgen[i].port = system.hmc_host.lmonitor[i].slave
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system.hmc_host.lmonitor[i].master = \
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system.hmc_host.seriallink[i].slave
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else:
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system.tgen[i].port = system.hmc_host.seriallink[i].slave
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return system
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# Create an HMC device and attach it to the current system
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def config_hmc(options, system):
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def config_hmc(options, system, hmc_host):
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system.hmc = HMCSystem()
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# Create HMC device
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system.hmc_dev = HMCSystem()
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system.buffer = Bridge(ranges=system.mem_ranges,
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req_size=system.hmc.ctrl_buffer_size_req,
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resp_size=system.hmc.ctrl_buffer_size_rsp,
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delay=system.hmc.ctrl_static_latency)
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# Global monitor
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try:
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system.hmc.enable_global_monitor = options.enable_global_monitor
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system.hmc_dev.enable_global_monitor = options.enable_global_monitor
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except:
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pass;
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try:
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system.hmc.enable_link_monitor = options.enable_link_monitor
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system.hmc_dev.enable_link_monitor = options.enable_link_monitor
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except:
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pass;
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system.membus.master = system.buffer.slave
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# The HMC controller (Clock domain is the same as the host)
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system.hmccontroller = HMCController(width=(system.hmc.num_lanes_per_link.
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value * system.hmc.num_serial_links/8),
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frontend_latency=system.hmc.ctrl_latency,
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forward_latency=system.hmc.link_overhead,
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response_latency=system.hmc.link_overhead)
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if system.hmc_dev.enable_link_monitor:
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system.hmc_dev.lmonitor = [ CommMonitor()
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for i in xrange(system.hmc_dev.num_links_controllers)]
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system.hmccontroller.clk_domain = SrcClockDomain(clock=system.hmc.
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link_frequency, voltage_domain = VoltageDomain(voltage = '1V'))
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# 4 HMC Crossbars located in its logic-base (LoB)
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system.hmc_dev.xbar = [ NoncoherentXBar(width=system.hmc_dev.xbar_width,
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frontend_latency=system.hmc_dev.xbar_frontend_latency,
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forward_latency=system.hmc_dev.xbar_forward_latency,
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response_latency=system.hmc_dev.xbar_response_latency )
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for i in xrange(system.hmc_host.number_mem_crossbar)]
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# Serial Links
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system.hmc.seriallink =[ SerialLink(ranges = system.mem_ranges,
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req_size=system.hmc.link_buffer_size_req,
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resp_size=system.hmc.link_buffer_size_rsp,
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num_lanes=system.hmc.num_lanes_per_link,
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delay=system.hmc.link_latency)
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for i in xrange(system.hmc.num_serial_links)]
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for i in xrange(system.hmc_dev.number_mem_crossbar):
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system.hmc_dev.xbar[i].clk_domain = SrcClockDomain(
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clock=system.hmc_dev.xbar_frequency,voltage_domain=
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VoltageDomain(voltage='1V'))
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if system.hmc.enable_link_monitor:
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system.hmc.lmonitor = [ CommMonitor()
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for i in xrange(system.hmc.num_serial_links)]
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# The HMC Crossbar located in its logic-base (LoB)
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system.hmc.xbar = NoncoherentXBar(width = system.hmc.xbar_width,
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frontend_latency=system.hmc.xbar_frontend_latency,
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forward_latency=system.hmc.xbar_forward_latency,
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response_latency=system.hmc.xbar_response_latency )
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system.hmc.xbar.clk_domain = SrcClockDomain(clock =
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system.hmc.xbar_frequency, voltage_domain =
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VoltageDomain(voltage = '1V'))
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if system.hmc.enable_global_monitor:
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system.gmonitor = CommMonitor()
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system.buffer.master = system.gmonitor.slave
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system.gmonitor.master = system.hmccontroller.slave
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else:
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system.hmccontroller.slave = system.buffer.master
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for i in xrange(system.hmc.num_serial_links):
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system.hmccontroller.master = system.hmc.seriallink[i].slave
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system.hmc.seriallink[i].clk_domain = system.hmccontroller.clk_domain;
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if system.hmc.enable_link_monitor:
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system.hmc.seriallink[i].master = system.hmc.lmonitor[i].slave
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system.hmc.lmonitor[i].master = system.hmc.xbar.slave
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# Attach 4 serial link to 4 crossbar/s
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for i in xrange(system.hmc_dev.num_serial_links):
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if system.hmc_dev.enable_link_monitor:
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system.hmc_host.seriallink[i].master = \
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system.hmc_dev.lmonitor[i].slave
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system.hmc_dev.lmonitor[i].master = system.hmc_dev.xbar[i].slave
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else:
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system.hmc.seriallink[i].master = system.hmc.xbar.slave
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system.hmc_host.seriallink[i].master = system.hmc_dev.xbar[i].slave
|
||||
|
||||
# Connecting xbar with each other for request arriving at the wrong xbar,
|
||||
# then it will be forward to correct xbar. Bridge is used to connect xbars
|
||||
if options.arch == "same":
|
||||
numx = len(system.hmc_dev.xbar)
|
||||
|
||||
# create a list of buffers
|
||||
system.hmc_dev.buffers = [ Bridge(
|
||||
req_size=system.hmc_dev.xbar_buffer_size_req,
|
||||
resp_size=system.hmc_dev.xbar_buffer_size_resp)
|
||||
for i in xrange(numx * (system.hmc_dev.mem_chunk - 1))]
|
||||
|
||||
# Buffer iterator
|
||||
it = iter(range(len(system.hmc_dev.buffers)))
|
||||
|
||||
# necesarry to add system_port to one of the xbar
|
||||
system.system_port = system.hmc_dev.xbar[3].slave
|
||||
|
||||
# iterate over all the crossbars and connect them as required
|
||||
for i in range(numx):
|
||||
for j in range(numx):
|
||||
# connect xbar to all other xbars except itself
|
||||
if i != j:
|
||||
# get the next index of buffer
|
||||
index = it.next()
|
||||
|
||||
# Change the default values for ranges of bridge
|
||||
system.hmc_dev.buffers[index].ranges = system.mem_ranges[
|
||||
j * int(system.hmc_dev.mem_chunk):
|
||||
(j + 1) * int(system.hmc_dev.mem_chunk)]
|
||||
|
||||
# Connect the bridge between corssbars
|
||||
system.hmc_dev.xbar[i].master = system.hmc_dev.buffers[
|
||||
index].slave
|
||||
system.hmc_dev.buffers[
|
||||
index].master = system.hmc_dev.xbar[j].slave
|
||||
else:
|
||||
# Don't connect the xbar to itself
|
||||
pass
|
||||
|
||||
# Two crossbars are connected to all other crossbars-Other 2 vault
|
||||
# can only direct traffic to it local vaults
|
||||
if options.arch == "mixed":
|
||||
|
||||
system.hmc_dev.buffer30 = Bridge(ranges=system.mem_ranges[0:4])
|
||||
system.hmc_dev.xbar[3].master = system.hmc_dev.buffer30.slave
|
||||
system.hmc_dev.buffer30.master = system.hmc_dev.xbar[0].slave
|
||||
|
||||
system.hmc_dev.buffer31 = Bridge(ranges=system.mem_ranges[4:8])
|
||||
system.hmc_dev.xbar[3].master = system.hmc_dev.buffer31.slave
|
||||
system.hmc_dev.buffer31.master = system.hmc_dev.xbar[1].slave
|
||||
|
||||
system.hmc_dev.buffer32 = Bridge(ranges=system.mem_ranges[8:12])
|
||||
system.hmc_dev.xbar[3].master = system.hmc_dev.buffer32.slave
|
||||
system.hmc_dev.buffer32.master = system.hmc_dev.xbar[2].slave
|
||||
|
||||
|
||||
system.hmc_dev.buffer20 = Bridge(ranges=system.mem_ranges[0:4])
|
||||
system.hmc_dev.xbar[2].master = system.hmc_dev.buffer20.slave
|
||||
system.hmc_dev.buffer20.master = system.hmc_dev.xbar[0].slave
|
||||
|
||||
system.hmc_dev.buffer21 = Bridge(ranges=system.mem_ranges[4:8])
|
||||
system.hmc_dev.xbar[2].master = system.hmc_dev.buffer21.slave
|
||||
system.hmc_dev.buffer21.master = system.hmc_dev.xbar[1].slave
|
||||
|
||||
system.hmc_dev.buffer23 = Bridge(ranges=system.mem_ranges[12:16])
|
||||
system.hmc_dev.xbar[2].master = system.hmc_dev.buffer23.slave
|
||||
system.hmc_dev.buffer23.master = system.hmc_dev.xbar[3].slave
|
||||
|
||||
|
|
|
|||
|
|
@ -153,9 +153,10 @@ def config_mem(options, system):
|
|||
"""
|
||||
|
||||
if ( options.mem_type == "HMC_2500_x32"):
|
||||
HMC.config_hmc(options, system)
|
||||
subsystem = system.hmc
|
||||
xbar = system.hmc.xbar
|
||||
HMChost = HMC.config_host_hmc(options, system)
|
||||
HMC.config_hmc(options, system, HMChost.hmc_host)
|
||||
subsystem = system.hmc_dev
|
||||
xbar = system.hmc_dev.xbar
|
||||
else:
|
||||
subsystem = system
|
||||
xbar = system.membus
|
||||
|
|
@ -222,4 +223,7 @@ def config_mem(options, system):
|
|||
|
||||
# Connect the controllers to the membus
|
||||
for i in xrange(len(subsystem.mem_ctrls)):
|
||||
subsystem.mem_ctrls[i].port = xbar.master
|
||||
if (options.mem_type == "HMC_2500_x32"):
|
||||
subsystem.mem_ctrls[i].port = xbar[i/4].master
|
||||
else:
|
||||
subsystem.mem_ctrls[i].port = xbar.master
|
||||
|
|
|
|||
|
|
@ -61,3 +61,5 @@ class SerialLink(MemObject):
|
|||
# link belongs to and the number of lanes:
|
||||
num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial"
|
||||
"link. (aka. lane width)")
|
||||
link_speed = Param.UInt64(1, "Gb/s Speed of each parallel lane inside the"
|
||||
"serial link. (aka. lane speed)")
|
||||
|
|
|
|||
|
|
@ -87,7 +87,9 @@ SerialLink::SerialLink(SerialLinkParams *p)
|
|||
ticksToCycles(p->delay), p->resp_size, p->ranges),
|
||||
masterPort(p->name + ".master", *this, slavePort,
|
||||
ticksToCycles(p->delay), p->req_size),
|
||||
num_lanes(p->num_lanes)
|
||||
num_lanes(p->num_lanes),
|
||||
link_speed(p->link_speed)
|
||||
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -153,8 +155,9 @@ SerialLink::SerialLinkMasterPort::recvTimingResp(PacketPtr pkt)
|
|||
// have to wait to receive the whole packet. So we only account for the
|
||||
// deserialization latency.
|
||||
Cycles cycles = delay;
|
||||
cycles += Cycles(divCeil(pkt->getSize() * 8, serial_link.num_lanes));
|
||||
Tick t = serial_link.clockEdge(cycles);
|
||||
cycles += Cycles(divCeil(pkt->getSize() * 8, serial_link.num_lanes
|
||||
* serial_link.link_speed));
|
||||
Tick t = serial_link.clockEdge(cycles);
|
||||
|
||||
//@todo: If the processor sends two uncached requests towards HMC and the
|
||||
// second one is smaller than the first one. It may happen that the second
|
||||
|
|
@ -214,7 +217,7 @@ SerialLink::SerialLinkSlavePort::recvTimingReq(PacketPtr pkt)
|
|||
// only.
|
||||
Cycles cycles = delay;
|
||||
cycles += Cycles(divCeil(pkt->getSize() * 8,
|
||||
serial_link.num_lanes));
|
||||
serial_link.num_lanes * serial_link.link_speed));
|
||||
Tick t = serial_link.clockEdge(cycles);
|
||||
|
||||
//@todo: If the processor sends two uncached requests towards HMC
|
||||
|
|
@ -301,7 +304,7 @@ SerialLink::SerialLinkMasterPort::trySendTiming()
|
|||
|
||||
// Make sure bandwidth limitation is met
|
||||
Cycles cycles = Cycles(divCeil(pkt->getSize() * 8,
|
||||
serial_link.num_lanes));
|
||||
serial_link.num_lanes * serial_link.link_speed));
|
||||
Tick t = serial_link.clockEdge(cycles);
|
||||
serial_link.schedule(sendEvent, std::max(next_req.tick, t));
|
||||
}
|
||||
|
|
@ -346,7 +349,7 @@ SerialLink::SerialLinkSlavePort::trySendTiming()
|
|||
|
||||
// Make sure bandwidth limitation is met
|
||||
Cycles cycles = Cycles(divCeil(pkt->getSize() * 8,
|
||||
serial_link.num_lanes));
|
||||
serial_link.num_lanes * serial_link.link_speed));
|
||||
Tick t = serial_link.clockEdge(cycles);
|
||||
serial_link.schedule(sendEvent, std::max(next_resp.tick, t));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -312,6 +312,9 @@ class SerialLink : public MemObject
|
|||
/** Number of parallel lanes in this serial link */
|
||||
unsigned num_lanes;
|
||||
|
||||
/** Speed of each link (Gb/s) in this serial link */
|
||||
uint64_t link_speed;
|
||||
|
||||
public:
|
||||
|
||||
virtual BaseMasterPort& getMasterPort(const std::string& if_name,
|
||||
|
|
|
|||
Loading…
Reference in a new issue