gem5/src
Mohammad Alian e5b7b6780f dist, dev: Fixed the packet ordering in etherswitch
This patch fixes the order that packets gets pushed into the output fifo
of etherswitch. If two packets arrive at the same tick to the etherswitch,
we sort and push them based on their source port id.
In dist-gem5 simulations, if there is no ordering inforced while two
packets arrive at the same tick, it can lead to non-deterministic simulations

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-06-08 09:12:41 -05:00
..
arch stats: Fixing regStats function for some SimObjects 2016-06-06 17:16:43 +01:00
base dev: Fix incorrect terminal backlog handling 2016-04-27 15:33:58 +01:00
cpu pwr: Low-power idle power state for idle CPUs 2016-06-06 17:16:43 +01:00
dev dist, dev: Fixed the packet ordering in etherswitch 2016-06-08 09:12:41 -05:00
doc sim: Adding support for power models 2016-06-06 17:16:44 +01:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
gpu-compute stats: Fixing regStats function for some SimObjects 2016-06-06 17:16:43 +01:00
kern syscall_emul: remove mmapFlagTable 2016-04-01 16:38:16 -07:00
mem stats: Fixing regStats function for some SimObjects 2016-06-06 17:16:43 +01:00
proto cpu: Support virtual addr in elastic traces 2015-12-07 16:42:16 -06:00
python power: Allow voltage to be configured via cmd line 2016-05-27 16:54:59 +01:00
sim sim: Make clang happy 2016-06-07 14:27:49 +01:00
unittest style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript scons: Bump minimum gcc version to 4.8 2016-05-30 02:10:48 -04:00