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124 commits

Author SHA1 Message Date
Andreas Hansson 726f626e87 stats: Bump stats for o3 LSQ changes 2014-12-02 06:08:05 -05:00
Andreas Hansson b0aa5a326d stats: Bump stats after static analysis fixes 
Fixing up the uninitialised values changes two of the x86 Linux boot
regressions slightly.
 2014-11-24 09:03:39 -05:00
Gabe Black 2d2a5aa410 x86: Update stats for the new Linux delay port. 2014-11-21 17:22:19 -08:00
Gabe Black 994c44035d x86: Update the stats for the x86 FS o3 boot test. 2014-11-17 00:16:36 -08:00
Andreas Hansson 4583a5114a stats: Bump regressions to match latest changes 
Updates after timezone hick-up and sorting of dictionary items in the
SimObject.
 2014-11-12 09:05:25 -05:00
Nilay Vaish 02b4605da0 stats: changes to x86 o3 fs and sparc fs regression tests. 2014-11-11 14:17:10 -06:00
Nilay Vaish a75e27b4a6 stats: updates due to changes to ruby 2014-11-06 05:42:21 -06:00
Ali Saidi ae82551496 tests: Update stats no match. 
Bootloader I had on my sytem was an older version with a couple of
instruction differences.
 2014-11-03 10:14:42 -06:00
Ali Saidi 2c2c3a4ce9 arm, tests: Forgot the system.terminal files for the new regressions. 2014-10-30 00:04:12 -05:00
Ali Saidi 29cd50e14e arm, tests: Add 64-bit ARM regression tests 2014-10-29 23:50:15 -05:00
Ali Saidi 93c0307d41 tests: Update regressions for the new kernels and various preceeding fixes. 2014-10-29 23:18:29 -05:00
Andreas Hansson a63ba6c7b7 stats: Small bump of trailing stats 
Somehow these seem to have been missed.
 2014-10-16 05:49:31 -04:00
Nilay Vaish 1efe42fa97 stats: updates due to changes to x86, stale configs. 2014-10-11 16:18:51 -05:00
Andreas Hansson 0746e92cd3 stats: Add DRAM power statistics to reference output 2014-10-09 17:52:13 -04:00
Andreas Hansson ff2d58f935 stats: Update stats to reflect ARM fixes 
As a result of the fixes, the full-system dual-core ARM regressions
are slightly changed. Hopefully this also means there will no longer
be any discrepancies between the results observed on different hosts.
 2014-09-28 16:53:48 -04:00
Steve Reinhardt 71d5f03175 stats: update t1000 stats for recent changes 2014-09-21 23:04:39 -04:00
Andreas Hansson c4e91289ae stats: Bump stats for filter, crossbar and config changes 
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
 2014-09-20 17:18:53 -04:00
Andreas Hansson 8d18713d28 stats: Minor update of Minor stats after uncacheable fix 2014-09-12 10:22:50 -04:00
Andreas Hansson a217eba078 stats: Update stats for CPU and cache changes 
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
 2014-09-03 07:42:59 -04:00
Nilay Vaish fa1fbcf020 stats: updates due to recent ruby and x86 changes 
Also updates many out of date config files.
 2014-09-01 16:55:52 -05:00
Andreas Hansson cbf417c713 stats: Bump stats for the regressions using the minor CPU 
Updating the stats to match the current behaviour.
 2014-07-28 01:48:21 -04:00
Andrew Bardsley 5d0b25ba3f cpu: Minor CPU add regression tests for ARM and ALPHA 
This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
 2014-07-23 16:09:05 -05:00
Steve Reinhardt 5b08e211ab stats: update for O3 changes 
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM.  At the other extreme, X86 70.twolf is 0.8%
slower.
 2014-06-22 14:33:09 -07:00
Nilay Vaish 2a8088f5ae stats: changes due to recent o3 patch. 2014-05-24 21:30:46 -05:00
Nilay Vaish 0aaa7d10d8 stats: changes due to o3 cpu and ruby message buffer patches 2014-05-23 06:07:02 -05:00
Steve Reinhardt 72403cb595 tests: update t1000 & pc-switcheroo-full stats 
committed reference config.json files too
 2014-05-12 17:22:17 -04:00
Andreas Hansson 57e5401d95 stats: Bump stats for the fixes, and mostly DRAM controller changes 2014-05-09 18:58:50 -04:00
Andreas Hansson 0c75581d03 stats: updates for pc-switcheroo-full due to o3 smt fix 2014-04-22 03:12:15 -04:00
Nilay Vaish 3bc5cfcc03 stats: updates due to o3 smt fix 
+ changes to one ruby regression config.ini file.
 2014-04-19 09:16:14 -05:00
Andreas Hansson 8b4b1dcb86 stats: Update stats for DRAM changes 
This patch updates the stats to reflect the changes to the DRAM
controller.
 2014-03-23 11:12:19 -04:00
Nilay Vaish 83d09ee215 stats: updates due to changes to ruby config scripts 
These updates to ruby regression stats are due to renaming piobus to iobus
and dropping piobus in the se mode.
 2014-03-20 09:16:35 -05:00
Nilay Vaish 3b404fb1a0 stats: updates due to changes to ruby pio access handling 2014-02-23 19:16:16 -06:00
Andreas Hansson fd9343eb85 arm: Bump stats after FS config script update 
This patch updates the stats to reflect the change in kernel options
needed for armv8 (but used for all FS regressions).
 2014-02-19 07:59:46 -05:00
Nilay Vaish 5abbb84f02 stats: updates due to branch predictor warming 2014-02-16 11:40:34 -06:00
Nilay Vaish fa0ff1c902 stats: update sparc fs stats 2014-01-27 13:30:37 -06:00
Ali Saidi cfb805cc71 stats: update stats for ARMv8 changes 2014-01-24 15:29:34 -06:00
Ali Saidi f3585c841e stats: update stats for cache occupancy and clock domain changes 2014-01-24 15:29:33 -06:00
Nilay Vaish fc6d1f3399 stats: updates due to changes to ruby 2014-01-10 16:19:58 -06:00
Nilay Vaish bb6d7d402b ruby: rename MESI_CMP_directory to MESI_Two_Level 
This is because the next patch introduces a three level hierarchy.

--HG--
rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level
rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py
rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm
rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm
rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm
rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm
rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm
rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
 2014-01-04 00:03:33 -06:00
Nilay Vaish e6008b6bc1 stats: updates due to bug fixed in mesi coherence protocol 2013-12-26 15:18:58 -06:00
Nilay Vaish 2823982a3c stats: updates due to changes to ticksToCycles() 2013-11-26 17:05:25 -06:00
Andreas Hansson ccfdc533b9 stats: Bump stats to match DRAM controller changes 
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
 2013-11-01 11:56:34 -04:00
Steve Reinhardt 10e6450120 test: update stats 
Update stats for recent changes.  Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
 2013-10-16 10:44:12 -04:00
Andreas Hansson a44bb59192 stats: Bump pc-simple-timing-ruby stats 
This patch simply brings the stats for the pc-simple-timing-ruby
regression up to date. The particular regression seems to give
different results on different systems unfortunately, and this update
reflects the current behaviour on zizzer.
 2013-10-09 04:41:19 -04:00
Andreas Sandberg 0438bf9389 stats: Update x86 stats after x87 fixes 
The updates to the x87 caused the stats for several regressions to
change. This was mainly caused by the addition of a working 32-bit and
80-bit FP load instruction and xsave support.
 2013-10-02 11:03:38 +02:00
Steve Reinhardt fbc1feb39a tests: update reference outputs 
Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes.  There are a few stats.txt updates too, but
they are in the minority.
 2013-09-28 15:25:17 -04:00
Nilay Vaish 143dfa31df stats: update sparc fs due to recent changes to memory class. 2013-09-15 13:45:59 -05:00
Nilay Vaish ff87a0dd9c stats: ruby: updates due to recent changes. 2013-09-06 16:21:36 -05:00
Nilay Vaish e351e846e3 stats: update ruby.stats, config.ini files for x86 fs test 2013-08-20 11:32:33 -05:00
Andreas Hansson b63631536d stats: Cumulative stats update 
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.
 2013-08-19 03:52:36 -04:00