Commit graph

8881 commits

Author SHA1 Message Date
Andreas Hansson
75681d3c1b Stats: Update stats for changeset 8868
Changeset 8868 slightly changes the statistics for the parser and
bzip2 regressions for ARM o3-timing. This patch merely updates the
statistics to reflect these changes.
2012-03-06 11:14:54 -05:00
Steve Reinhardt
3418ebb5f8 SConstruct: rename and document AddM5Option
Got rid of gratuitous M5 reference in the function name.
In the process, wondered why we have this function at all and
spent time trying to get rid of it and eventually firgured out
why it's needed.  Put the answer in a comment so we don't have
to wonder again.
2012-03-02 14:05:00 -08:00
Steve Reinhardt
f71a5c5e62 SConstruct: update comments & doc strings
Lots of references to 'M5' still, and some to SE/FS
2012-03-02 13:53:52 -08:00
Steve Reinhardt
fd2d5ae2af DynInst: get rid of dead MyHash code.
Not sure what this was ever used for, but it
doesn't seem used anymore.
2012-03-02 09:17:42 -08:00
Andreas Hansson
32eae8094d CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.

The patch also adds the "createInterruptController" call to a number
of the regression scripts.
2012-03-02 09:21:48 -05:00
Andreas Hansson
c0b9f324bf Stats: Fix the realview regression stats after nvmem move
This patch updates the realview regressions stats to reflect that nvmem
moved in the object hierarchy and is now under system.realview.
2012-03-02 09:18:50 -05:00
Andreas Hansson
adc419a13a Ruby: Rename RubyPort::sendTiming to avoid overriding base class
This patch renames the sendTiming member function in the RubyPort to
avoid inadvertently hiding Port::sendTiming (discovered through some
rather painful debugging). The RubyPort does, in fact, rely on the
functionality of the queued port and the implementation merely
schedules a send the next cycle. The new name for the member function
is sendNextCycle to better reflect this behaviour.

In the unlikely event that we ever shift to using C++11 the member
functions in Port should have a "final" identifier to prevent any
overriding in derived classes.
2012-03-02 09:16:50 -05:00
Ali Saidi
b129d7ce00 ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.
New kernel code verifies that multi-processor extensions are available
before booting secondary CPUs.
2012-03-02 08:18:19 -06:00
Ali Saidi
96e37eb17c ARM: FIx missing cf controller connection. 2012-03-01 22:43:23 -06:00
Chander Sudanthi
357fb0a185 VNC: spacing
Fixed some spacing in a switch statement
2012-03-01 17:26:36 -06:00
Ali Saidi
91b737ed48 ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
2012-03-01 17:26:31 -06:00
Ali Saidi
3876105bdb ARM: Add RTC device for ARM platforms.
This change implements a PL031 real time clock.

--HG--
rename : src/dev/arm/timer_sp804.cc => src/dev/arm/rtc_pl031.cc
rename : src/dev/arm/timer_sp804.hh => src/dev/arm/rtc_pl031.hh
2012-03-01 17:26:31 -06:00
Matt Horsnell
08187e3916 ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.
2012-03-01 17:26:31 -06:00
Ali Saidi
d907d0ec72 Cache: Fix an issue with LRU when bonus block is used to complete transaction.
The block is never inserted because it's the one extra block in the cache, but
it can be invalidated twice in a row. In that case the block doesn't have a
new master id (beacuse it was never inserted), however it is valid and
the accounting goes wrong at that point.
2012-03-01 17:26:31 -06:00
Dam Sunwoo
86d1042d9f ARM: move kernel func event to correct location.
With the recent series of patches, the symbol table loading moved from
"construct" time to "init" time, but the kernel function event
callback registration was left behind. This patch moves it to the
proper location.
2012-03-01 17:26:31 -06:00
Giacomo Gabrielli
d51478db4e ARM: fix bits-to-fp conversion function declarations.
Add extra declarations to allow the compiler to pick up the right function.
Please note that these declarations have been added as part of the
clang-related changes.
2012-03-01 17:26:30 -06:00
Nilay Vaish
4b32c9fb4d x86: Fix x86 TLB and Walker
This patch adds a function to X86 tlb that returns the
walker port. This port is required for correctly connecting
the walker ports for the cpu just switched in
2012-03-01 11:37:03 -06:00
Nilay Vaish
c80af04d7d x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for
cpus that will be switched in later
2012-03-01 11:37:02 -06:00
Nilay Vaish
e11847bfa9 Config: make option ruby available always 2012-03-01 11:36:59 -06:00
Andreas Hansson
e5ac647fc9 MEM: Make all the port proxy members const
This is a trivial patch that merely makes all the member functions of
the port proxies const. There is no good reason why they should not
be, and this change only serves to make it explicit that they are not
modified through their use.
2012-02-29 04:47:51 -05:00
Andreas Hansson
88abdc0fad SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
This patch fixes a compilation error that occurs with gcc >= 4.6.1,
caused by swig not including cstddef and not using the std:: namespace
prefix for ptrdiff_t. There is an old patch,
http://reviews.m5sim.org/r/913/ that no longer applies cleanly and
this might be re-iterating the same issue.

We work around the problem by always enforcing the inclusion of
cstddef in all swig interface declarations, and also by explicitly
using std::ptrdiff_t.
2012-02-29 04:26:58 -05:00
Steve Reinhardt
13e14ba93c EIO: update stats (mostly order change, some renames) 2012-02-29 01:51:39 -05:00
Gabe Black
5917fb3292 Make the IO bridge accept address headed to all the local APICs. 2012-02-26 15:33:07 -08:00
Gabe Black
559b43a372 X86: Use the M5PanicFault fault in execute methods instead of calling panic.
If an instruction is executed speculatively and hits a situation where it
wants to panic, it should return a fault instead. If the instruction was
misspeculated, the fault can be thrown away. If the instruction wasn't
misspeculated, the fault will be invoked and the panic will still happen.
2012-02-26 15:32:53 -08:00
Andreas Hansson
0cd0a8fdd3 MEM: Simplify cache ports preparing for master/slave split
This patch splits the two cache ports into a master (memory-side) and
slave (cpu-side) subclass of port with slightly different
functionality. For example, it is only the CPU-side port that blocks
incoming requests, and only the memory-side port that schedules send
events outside of what the transmit list dictates.

This patch simplifies the two classes by relying further on
SimpleTimingPort and also generalises the latter to better accommodate
the changes (introducing trySendTiming and scheduleSend). The
memory-side cache port overrides sendDeferredPacket to be able to not
only send responses from the transmit list, but also send requests
based on the MSHRs.

A follow on patch further simplifies the SimpleTimingPort and the
cache ports.
2012-02-24 11:52:49 -05:00
Andreas Hansson
77878d0a87 MEM: Prepare mport for master/slave split
This patch simplifies the mport in preparation for a split into a
master and slave role for the message ports. In particular,
sendMessageAtomic was only used in a single location and similarly so
sendMessageTiming. The affected interrupt device is updated
accordingly.
2012-02-24 11:50:15 -05:00
Andreas Hansson
86c2aad482 Ruby: Simplify tester ports by not using SimpleTimingPort
This patch simplfies the master ports used by RubyDirectedTester and
RubyTester by avoiding the use of SimpleTimingPort. Neither tester
made any use of the functionality offered by SimpleTimingPort besides
a trivial implementation of recvFunctional (only snoops) and
recvRangeChange (not relevant since there is only one master).

The patch does not change or add any functionality, it merely makes
the introduction of a master/slave port easier (in a future patch).
2012-02-24 11:48:48 -05:00
Andreas Hansson
485d103255 MEM: Move all read/write blob functions from Port to PortProxy
This patch moves the readBlob/writeBlob/memsetBlob from the Port class
to the PortProxy class, thus making a clear separation of the basic
port functionality (recv/send functional/atomic/timing), and the
higher-level functional accessors available on the port proxies.

There are only a few places in the code base where the blob functions
were used on ports, and they are all for peeking into the memory
system without making a normal memory access (in the memtest, and the
malta and tsunami pchip). The memtest also exemplifies how easy it is
to create a non-translating proxy if desired. The malta and tsunami
pchip used a slave port to perform a functional read, and this is now
changed to rely on the physProxy of the system (to which they already
have a pointer).
2012-02-24 11:46:39 -05:00
Andreas Hansson
9e3c8de30b MEM: Make port proxies use references rather than pointers
This patch is adding a clearer design intent to all objects that would
not be complete without a port proxy by making the proxies members
rathen than dynamically allocated. In essence, if NULL would not be a
valid value for the proxy, then we avoid using a pointer to make this
clear.

The same approach is used for the methods using these proxies, such as
loadSections, that now use references rather than pointers to better
reflect the fact that NULL would not be an acceptable value (in fact
the code would break and that is how this patch started out).

Overall the concept of "using a reference to express unconditional
composition where a NULL pointer is never valid" could be done on a
much broader scale throughout the code base, but for now it is only
done in the locations affected by the proxies.
2012-02-24 11:45:30 -05:00
Andreas Hansson
1031b824b9 MEM: Move port creation to the memory object(s) construction
This patch moves all port creation from the getPort method to be
consistently done in the MemObject's constructor. This is possible
thanks to the Swig interface passing the length of the vector ports.
Previously there was a mix of: 1) creating the ports as members (at
object construction time) and using getPort for the name resolution,
or 2) dynamically creating the ports in the getPort call. This is now
uniform. Furthermore, objects that would not be complete without a
port have these ports as members rather than having pointers to
dynamically allocated ports.

This patch also enables an elaboration-time enumeration of all the
ports in the system which can be used to determine the masterId.
2012-02-24 11:43:53 -05:00
Andreas Hansson
9f07d2ce7e CPU: Round-two unifying instr/data CPU ports across models
This patch continues the unification of how the different CPU models
create and share their instruction and data ports. Most importantly,
it forces every CPU to have an instruction and a data port, and gives
these ports explicit getters in the BaseCPU (getDataPort and
getInstPort). The patch helps in simplifying the code, make
assumptions more explicit, andfurther ease future patches related to
the CPU ports.

The biggest changes are in the in-order model (that was not modified
in the previous unification patch), which now moves the ports from the
CacheUnit to the CPU. It also distinguishes the instruction fetch and
load-store unit from the rest of the resources, and avoids the use of
indices and casting in favour of keeping track of these two units
explicitly (since they are always there anyways). The atomic, timing
and O3 model simply return references to their already existing ports.
2012-02-24 11:42:00 -05:00
Andreas Hansson
ef4af8cec8 MEM: Fatal when no port can be found for an address
This patch adds a check in the findPort method to ensure that an
invalid port id is never returned. Previously this could happen if no
default port was set, and no address matched the request, in which
case -1 was returned causing a SEGFAULT when using the id to index in
the port array. To clean things up further a symbolic name is added
for the invalid port id.
2012-02-24 11:40:29 -05:00
Steve Reinhardt
e121708e08 SimObject: make get_config_as_dict() tolerate undefined params
Without this patch, undefined params cause a cryptic KeyError
in multidict inside get_config_as_dict().  This patch lets
undefined params through get_config_as_dict() so they can
once again generate meaningful error messages later on in
the configuration process.
2012-02-20 08:11:14 -08:00
Andreas Hansson
6cf9f182f6 MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.
2012-02-14 14:15:30 -05:00
Andreas Hansson
ac91f90145 Script: Fix the scripts that use the num_cpus cache parameter
This patch merely removes the use of the num_cpus cache parameter
which no longer exists after the introduction of the masterIds. The
affected scripts fail when trying to set the parameter. Note that this
patch does not update the regression stats.
2012-02-14 12:11:18 -05:00
Andreas Hansson
00978170f3 MEM: Fix master/slave ports in Ruby and non-regression scripts
This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.
2012-02-14 03:41:53 -05:00
Ali Saidi
0d46708dc2 bp: fix up stats for changes to branch predictor 2012-02-13 12:30:30 -06:00
Mrinmoy Ghosh
9b05e96b9e BPred: Fix RAS to handle predicated call/return instructions.
Change RAS to fix issues with predicated call/return instructions.
Handled all cases in the life of a predicated call and return instruction.
2012-02-13 12:26:25 -06:00
Mrinmoy Ghosh
fd90c3676d BP: Fix several Branch Predictor issues.
1. Updates the Branch Predictor correctly to the state
   just after a mispredicted branch, if a squash occurs.
2. If a BTB does not find an entry, the branch is predicted not taken.
   The global history is modified to correctly reflect this prediction.
3. Local history is now updated at the fetch stage instead of
   execute stage.
4. In the Update stage of the branch predictor the local predictors are
   now correctly updated according to the state of local history during
   fetch stage.

This patch also improves performance by as much as 17% on some benchmarks
2012-02-13 12:26:24 -06:00
Andreas Hansson
abc212461b MEM: Explicit ports and Python binding on CopyEngine
The copy-engine ports were previously created implicitly and bound
based on the dma port peer rather than relying on the normal Python
binding (connectPorts) being called explicitly. This patch makes the
copy engine port similar to all other ports in that they are visibly
in the Python class and bound using the normal explicit calls through
Python.
2012-02-13 06:46:43 -05:00
Andreas Hansson
63777fb23f MEM: Pass the ports from Python to C++ using the Swig params
This patch adds basic information about the ports in the parameter
classes to be passed from the Python world to the corresponding C++
object. Currently, the only information passed is the number of
connected peers, which for a Port is either 0 or 1, and for a
VectorPort reflects the size of the VectorPort. The default port of
the bus had to be renamed to avoid using the name "default" as a field
in the parameter class. It is possible to extend the Swig'ed
information further and add e.g. a pair with a description and size.
2012-02-13 06:45:11 -05:00
Andreas Hansson
5a9a743cfc MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
2012-02-13 06:43:09 -05:00
Ali Saidi
8cb4a2208d tests: fix diff-out script for op/inst stat changes. 2012-02-12 18:35:59 -06:00
Gabe Black
eada4268ef X86: open flags: Another patch from Vince Weaver 2012-02-12 16:41:29 -08:00
Ali Saidi
67f16a48fb configs: fix minor config bugs posted on the mailing list 2012-02-12 17:18:53 -06:00
Ali Saidi
4f8d1a4cef stats: update stats for insts/ops and master id changes 2012-02-12 16:07:43 -06:00
Anthony Gutierrez
542d0ceebc cpu: add separate stats for insts/ops both globally and per cpu model 2012-02-12 16:07:39 -06:00
Dam Sunwoo
230540e655 mem: fix cache stats to use request ids correctly
This patch fixes the cache stats to use the new request ids.
Cache stats also display the requestor names in the vector subnames.
Most cache stats now include "nozero" and "nonan" flags to reduce the
amount of excessive cache stat dump. Also, simplified
incMissCount()/incHitCount() functions.
2012-02-12 16:07:39 -06:00
Ali Saidi
8aaa39e93d mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
2012-02-12 16:07:38 -06:00
Mrinmoy Ghosh
7e104a1af2 prefetcher: Make prefetcher a sim object instead of it being a parameter on cache 2012-02-12 16:07:38 -06:00