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MEM: Fix master/slave ports in Ruby and non-regression scripts

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This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.
This commit is contained in:
Andreas Hansson 2012-02-14 03:41:53 -05:00
parent 0d46708dc2
commit 00978170f3
13 changed files with 29 additions and 29 deletions
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4
configs/example/fs.py
View file

@ -195,8 +195,8 @@ if len(bm) == 2:
drive_sys.kernel = binary(options.kernel)
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(bm[1].mem())])
drive_sys.iobridge.slave = drive_sys.iobus.port
drive_sys.iobridge.master = drive_sys.membus.port
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave
drive_sys.init_param = options.init_param
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)

2
configs/example/ruby_direct_test.py
View file

@ -102,7 +102,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
system.tester.cpuPort = ruby_port.port
system.tester.cpuPort = ruby_port.slave
# -----------------------
# run simulation

8
configs/example/ruby_fs.py
View file

@ -125,11 +125,11 @@ for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
cpu.interrupts.pio = system.piobus.master
cpu.interrupts.int_master = system.piobus.slave
cpu.interrupts.int_slave = system.piobus.master

2
configs/example/ruby_mem_test.py
View file

@ -133,7 +133,7 @@ for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
cpu.test = system.ruby._cpu_ruby_ports[i].port
cpu.test = system.ruby._cpu_ruby_ports[i].slave
cpu.functional = system.funcmem.port
#

2
configs/example/ruby_network_test.py
View file

@ -109,7 +109,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the cpu test ports to the ruby cpu port
#
cpus[i].test = ruby_port.port
cpus[i].test = ruby_port.slave
ruby_port.access_phys_mem = False
i += 1

2
configs/example/ruby_random_test.py
View file

@ -110,7 +110,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
tester.cpuPort = ruby_port.port
tester.cpuPort = ruby_port.slave
#
# Tell each sequencer this is the ruby tester so that it

4
configs/example/se.py
View file

@ -190,8 +190,8 @@ for i in xrange(np):
system.cpu[i].workload = multiprocesses[i]
if options.ruby:
system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave
system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port

6
configs/ruby/MESI_CMP_directory.py
View file

@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
@ -180,9 +180,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1

8
configs/ruby/MI_example.py
View file

@ -95,7 +95,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@ -153,10 +153,10 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl.dma_sequencer.port = dma_device.dma
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl.dma_sequencer.slave = dma_device.dma
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1

6
configs/ruby/MOESI_CMP_directory.py
View file

@ -103,7 +103,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@ -177,9 +177,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1

6
configs/ruby/MOESI_CMP_token.py
View file

@ -125,7 +125,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@ -201,9 +201,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1

6
configs/ruby/MOESI_hammer.py
View file

@ -118,7 +118,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
cpu_seq.pio_port = piobus.slave
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
@ -213,9 +213,9 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
else:
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
if options.recycle_latency:

2
configs/ruby/Network_test.py
View file

@ -96,7 +96,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.port
cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#