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Author SHA1 Message Date
Nathan Binkert eec67312b5 attrdict: add pickle support to attrdict 2009-09-22 15:24:16 -07:00
Nathan Binkert aa78db4ada code_formatter: use __builtin__ which is correct, not __builtins__ 2009-09-22 15:24:16 -07:00
Nathan Binkert a6b39c07d9 code_formatter: Add a python class for writing code generator templates 2009-08-16 13:40:03 -07:00
Nathan Binkert 2ecaa99025 ply: add a base class called Grammar that encapsulates a ply grammar 2009-08-16 13:40:01 -07:00
Nathan Binkert 2334e6fdd5 orderdict: Use DictMixin and add orderdict to m5.util 2009-08-16 13:40:00 -07:00
Nathan Binkert 06c7ecb207 python: Make it possible to import the parts of m5 that are pure python 2009-08-16 13:39:59 -07:00
Nathan Binkert 6fd3987b3f attrdict: correct delattr 2009-07-02 16:48:22 -07:00
Nathan Binkert eef3a2e142 types: Move stuff for global types into src/base/types.hh 
--HG--
rename : src/sim/host.hh => src/base/types.hh
 2009-05-17 14:34:50 -07:00
Nathan Binkert 20f1da8b96 python: pull out common code from main that processes arguments 2009-05-11 11:18:09 -07:00
Nathan Binkert ca3d82b38a stats: remove simplescalar compatibility for printing 2009-04-22 10:25:14 -07:00
Steve Reinhardt 4f1855484c Fix up regression execution to better handle tests that end abnormally. 
E.g., mark aborts due to assertion failures as failed tests,
but those that get killed by the user as needing to be rerun, etc.
 2009-03-07 16:58:51 -08:00
Nathan Binkert 6f787e3d36 stats: create an enable phase, and a prepare phase. 
Enable more or less takes the place of check, but also allows stats to
do some other configuration.  Prepare moves all of the code that readies
a stat for dumping into a separate function in preparation for supporting
serialization of certain pieces of statistics data.
While we're at it, clean up the visitor code and some of the python code.
 2009-03-05 19:09:53 -08:00
Ali Saidi 6fd4bc34a1 CPA: Add new object for gathering critical path annotations. 2009-02-26 19:29:17 -05:00
Ali Saidi 894925f135 Trace: fix the --trace-start option 2009-02-26 19:29:16 -05:00
Nathan Binkert c41c9cf3a6 events: Make trace events happen at the right priority. 
Also, while we're at it, remember that priorities are in the Event class
and add a disable method to disable tracing.
 2009-02-18 10:00:15 -08:00
Nathan Binkert e0f425bb94 traceflags: fix --trace-help 2009-02-15 20:39:12 -08:00
Nathan Binkert 64eb0dc9cd some new files are missing copyright notices 2009-02-04 16:26:15 -08:00
Ali Saidi be5d350afc SCons: Fix how we get Mercurial revision information since internals keep changing. 2009-01-30 20:04:57 -05:00
Ali Saidi f4291aac25 Errors: Print a URL with a hash of the format string to find more information about an error. 2009-01-30 20:04:15 -05:00
Ali Saidi 35a85a4e86 Config: Cause a fatal() when a parameter without a default value isn't set(FS #315). 2009-01-30 19:08:13 -05:00
Nathan Binkert 81b8c0c79a python: add fatal() function to the m5 package and use it 2009-01-19 14:43:09 -08:00
Nathan Binkert da14789c32 python: Try to isolate the stuff that's in the m5.internal package a bit more. 2009-01-19 09:59:15 -08:00
Nathan Binkert 0876c822dd tracing: panic() if people try to use tracing, but TRACING_ON is not set. 
Also clean things up so that help strings can more easily be added.
Move the help function into trace.py
 2009-01-19 09:59:13 -08:00
Nathan Binkert f15f252d4e python: Rework how things are imported 2009-01-19 09:59:13 -08:00
Nathan Binkert 19273164da output: Change default output directory and files and update tests. 
--HG--
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
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rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
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rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
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rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr
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rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr
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rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr
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rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
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rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr
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rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr
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rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
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rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
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rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
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rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
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rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr
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rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
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rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
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rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr
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rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
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rename : tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
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rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
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rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
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rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
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rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr => tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
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rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
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rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
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rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
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rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
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rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
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rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
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rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
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rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
 2008-12-08 07:16:40 -08:00
Nathan Binkert a0d322be40 traceflags: Make "All" a valid trace flag. 2008-12-06 14:18:18 -08:00
Nathan Binkert e08c6be9fe SimObject: change naming of vectors so there are the same numbers of digits. 
i.e. we used to have Foo0, Foo1, ..., Foo10, Foo11, ..., Foo100
now we have Foo000, Foo001, ..., Foo010, Foo011, ..., Foo100
 2008-12-06 14:18:18 -08:00
Steve Reinhardt ce4c9a7c10 Sort trace flags before printing them. 2008-11-17 12:41:50 -08:00
Nathan Binkert 4e02e7c217 python: Fix the reference counting for python events placed on the eventq. 
We need to add a reference when an object is put on the C++ queue, and remove
a reference when the object is removed from the queue.  This was not happening
before and caused a memory problem.
 2008-11-10 11:51:18 -08:00
Nathan Binkert 5b07448cf1 eventq: make python events actually work 2008-10-14 09:34:11 -07:00
Nathan Binkert 70dbe61ffc jobfile: Add support for dictionaries as jobfile options. 
If the same dictionary option is seen in several options, those
dictionaries are composed.  If you define the same dictionary key in
multiple options, the system flags an error.
Also, clean up the jobfile code so that it is more debuggable.
 2008-10-10 10:15:01 -07:00
Nathan Binkert 84364f36d0 python: Add a utility for nested attribute dicts. 
Change attrdict so that attributes that begin with an underscore don't
go into the dict.
 2008-10-10 10:15:00 -07:00
Nathan Binkert 94b08bed07 SimObjects: Clean up handling of C++ namespaces. 
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.
 2008-10-09 22:19:39 -07:00
Nathan Binkert e06321091d eventq: convert all usage of events to use the new API. 
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
 2008-10-09 04:58:24 -07:00
Nathan Binkert 8291d9db0a eventq: Major API change for the Event and EventQueue structures. 
Since the early days of M5, an event needed to know which event queue
it was on, and that data was required at the time of construction of
the event object.  In the future parallelized M5, this sort of
requirement does not work well since the proper event queue will not
always be known at the time of construction of an event.  Now, events
are created, and the EventQueue itself has the schedule function,
e.g. eventq->schedule(event, when).  To simplify the syntax, I created
a class called EventManager which holds a pointer to an EventQueue and
provides the schedule interface that is a proxy for the EventQueue.
The intent is that objects that frequently schedule events can be
derived from EventManager and then they have the schedule interface.
SimObject and Port are examples of objects that will become
EventManagers.  The end result is that any SimObject can just call
schedule(event, when) and it will just call that SimObject's
eventq->schedule function.  Of course, some objects may have more than
one EventQueue, so this interface might not be perfect for those, but
they should be relatively few.
 2008-10-09 04:58:23 -07:00
Nathan Binkert 68c75c589b pdb: Try to make pdb work better. 
I've done a few things here.  First, I invoke the script a little bit
differently so that pdb doesn't get confused.  Second, I've stored the
actual filename in the module's __file__ so that pdb can find the
source file on your machine.
 2008-10-09 04:58:23 -07:00
Nathan Binkert 6b2bb53fd6 python: cleanup options parsing stuff so that it properly deals with defaults. 
While we're at it, make it possible to run main.py in a somewhat
standalone mode again so that we can test things without compiling.
 2008-10-06 09:31:51 -07:00
Steve Reinhardt 7bf6a219db Make overriding port assignments in Python work, 
and print better error messages when it doesn't.
 2008-09-29 23:30:14 -07:00
Ali Saidi 3a3e356f4e style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
Steve Reinhardt 3448a12208 Make time format in 'started' line same as 'compiled'. 
Also make -B output consistent with normal header, and
only include actual build options.
 2008-08-04 01:46:46 -04:00
Steve Reinhardt fe8aeff362 Add -r/-e options to redirect stdout/stderr. 
Better than using shell since it automatically uses -d directory
for output files (creating it as needed).
 2008-08-04 00:40:31 -04:00
Nathan Binkert 50ef39af82 sockets: Add a function to disable all listening sockets. 
When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb.  Expose a function to disable those ports, and have the
regression scripts disable them.  There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.
 2008-08-03 18:19:55 -07:00
Nathan Binkert ede89c2d54 libm5: Create a libm5 static library for embedding m5. 
This should allow m5 to be more easily embedded into other simulators.
The m5 binary adds a simple main function which then calls into the m5
libarary to start the simulation. In order to make this work
correctly, it was necessary embed python code directly into the
library instead of the zipfile hack.  This is because you can't just
append the zipfile to the end of a library the way you can a binary.
As a result, Python files that are part of the m5 simulator are now
compile, marshalled, compressed, and then inserted into the library's
data section with a certain symbol name.  Additionally, a new Importer
was needed to allow python to get at the embedded python code.

Small additional changes include:
- Get rid of the PYTHONHOME stuff since I don't think anyone ever used
it, and it just confuses things.  Easy enough to add back if I'm wrong.
- Create a few new functions that are key to initializing and running
the simulator: initSignals, initM5Python, m5Main.

The original code for creating libm5 was inspired by a patch Michael
Adler, though the code here was done by me.
 2008-08-03 18:19:54 -07:00
Michael Adler 8c4f18f6f5 RemoteGDB: add an m5 command line option for setting or disabling remote gdb. 2008-07-23 14:41:33 -07:00
Nathan Binkert c1584e4227 imported patch sim_object_params.diff 2008-06-18 12:07:15 -07:00
Nathan Binkert b429b1759d params: Prevent people from setting attributes on vector params. 2008-06-15 21:26:33 -07:00
Nathan Binkert b2036bfda8 Command line option to print out List of SimObjects and their parameters 2008-06-14 21:51:08 -07:00
Nathan Binkert bbeb8082a5 main: add .m5/options.py processing. This file is processed before 
arguments are parsed so that they can change the default options for
various config parameters.
 2008-06-14 21:16:00 -07:00
Nathan Binkert fc48d1dcf5 Add .m5 configuration directory 2008-06-14 21:15:59 -07:00
Nathan Binkert 779c31077c python: Separate the options parsing stuff. Remove options parsing stuff from 
main.py so things are a bit more obvious.
 2008-06-14 21:15:58 -07:00
Nathan Binkert 4afdc40d70 params: Fix the memory bandwidth parameter 2008-06-14 20:42:45 -07:00
Nathan Binkert 3d2e7797cc params: Fix floating point parameters 2008-06-14 20:39:31 -07:00
Nathan Binkert f82d4e2364 python: Move various utility classes into a new m5.util package so 
they're all in the same place.  This also involves having just one
jobfile.py and moving it into the utils directory to avoid
duplication.  Lots of improvements to the utility as well.

--HG--
rename : src/python/m5/attrdict.py => src/python/m5/util/attrdict.py
rename : util/pbs/jobfile.py => src/python/m5/util/jobfile.py
rename : src/python/m5/util.py => src/python/m5/util/misc.py
rename : src/python/m5/multidict.py => src/python/m5/util/multidict.py
rename : util/stats/orderdict.py => src/python/m5/util/orderdict.py
 2008-06-14 20:19:49 -07:00
Ali Saidi 907b28cc62 HG: Add compiled hg revision and date to the standard M5 output. 2008-06-13 01:09:04 -04:00
Gabe Black 7be8e671f1 Params: Allow nested namespaces in cxx_namespace 2008-06-12 01:00:29 -04:00
Gabe Black 23c04b8c66 Params: Remove an unnecessary include. 2008-06-12 00:59:58 -04:00
Ali Saidi a33a3f7c55 Update copyright dates 
--HG--
extra : convert_revision : 547e7ddff6b8005a9eaad60970bc51984e84fcd1
 2008-02-11 12:35:28 -05:00
Gabe Black 6095dceb0c Params: Fix check for cycles in the configuration and clarify the comments/error message. 
--HG--
extra : convert_revision : 8f35dde408fae874bcba1a248d32a22222d98c35
 2007-11-12 18:06:02 -08:00
Ali Saidi f4222610ea Python: Allow a range to be a python tuple/list. 
--HG--
extra : convert_revision : 81cf805055e2f4d62e56a02ac82a0b230251f40b
 2007-11-08 10:46:41 -05:00
Miles Kaufmann eddf6f1637 python: Write configuration file without reassigning sys.stdout. 
Using print >>ini_file syntax instead of reassigning sys.stdout
allows the python debugger to be used.

--HG--
extra : convert_revision : 63fc268f2e80f338ad1a7abe54b9e979e2239609
 2007-08-30 15:16:59 -04:00
Miles Kaufmann 9cb49ab9e0 python: Eliminate the Python use of eval() and frame manipulation 
--HG--
extra : convert_revision : 04520bcfab510580a1c7fb341afbd2487287d1ab
 2007-08-30 15:16:58 -04:00
Nathan Binkert 7a996ccc98 switching: Remove the drain and resume code from the switching code. 
This allows us to change memory modes as well.
Clean up the code while we're at it.

--HG--
extra : convert_revision : fc5fee9ffd08b791f0607ee2688f32aa65d15354
 2007-08-04 16:09:24 -07:00
Nathan Binkert 5a27431b96 python: use the enum values in the memory mode changing code 
--HG--
extra : convert_revision : 2e399b2b407922ad076f93d33af73e3ba4c05218
 2007-08-04 16:06:19 -07:00
Nathan Binkert 157bd25802 python: provide access to stats 
--HG--
extra : convert_revision : 18a4e9ef21bd77ec73482557e028d535f0c1f273
 2007-08-04 16:02:04 -07:00
Nathan Binkert 0536d0cde9 python: Improve support for python calling back to C++ member functions. 
Add support for declaring SimObjects to swig so their members can be wrapped.
Make sim_object.i only contain declarations for SimObject.
Create system.i to contain declarations for System.
Update python code to properly call the C++ given the new changes.

--HG--
extra : convert_revision : 82076ee69e8122d56e91b92d6767e356baae420a
 2007-08-02 22:50:02 -07:00
Nathan Binkert b367474916 python: fix m5.build_env variable. 
As it is now, some objects will get the incorrect value depending where they
were defined.

--HG--
extra : convert_revision : a11a14842f9524739cbf54a48be6ec051f371200
 2007-08-02 14:12:53 -07:00
Nathan Binkert dfa147a70a python: need to import objects to make some calls work 
--HG--
extra : convert_revision : b5eec971d76626b2f42448052ab2cb2acb652d1b
 2007-08-02 12:03:35 -07:00
Nathan Binkert 5682f4f7f9 main: expose the build information as a simple command line parameter 
--HG--
extra : convert_revision : 69189c4a2e9fa9290fe51a2a43a2b08e712c395d
 2007-08-02 11:59:02 -07:00
Nathan Binkert abc76f20cb Major changes to how SimObjects are created and initialized. Almost all 
creation and initialization now happens in python.  Parameter objects
are generated and initialized by python.  The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.

--HG--
extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
 2007-07-23 21:51:38 -07:00
Nathan Binkert 961f8382f6 Add a function to get a SimObject's memory mode and rework 
the set memory mode code to only go through the change if
it is necessary

--HG--
extra : convert_revision : 28288227bb56b0a04d756776eaf0a4ff9e1f8c20
 2007-06-10 13:52:21 -07:00
Nathan Binkert 35147170f9 Move SimObject python files alongside the C++ and fix 
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
 2007-05-27 19:21:17 -07:00
Steve Reinhardt 0305159abf PhysicalMemory has vector of uniform ports instead of one special one. 
configs/example/memtest.py:
    PhysicalMemory has vector of uniform ports instead of one special one.
    Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
    Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
    Add comment.

--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
 2007-05-19 00:24:34 -04:00
Nathan Binkert 113319a7da Float should have a c++ param type 
--HG--
extra : convert_revision : 150bbe7f31aafb43a75195fc2a365fb3c0ec5673
 2007-05-11 11:48:58 -07:00
Ali Saidi 634d2e9d83 remove hit_latency and make latency do the right thing 
set the latency parameter in terms of a latency
add caches to tsunami-simple configs

configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
    set the latency parameter in terms of a latency
configs/common/FSConfig.py:
    give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
    remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    add caches to tsunami-simple configs

--HG--
extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
 2007-05-10 18:24:48 -04:00
Ali Saidi 4a37c48e8e add/update parameters for bus bridge 
--HG--
extra : convert_revision : 063f757fbfa2c613328ffa70e556f8926623fa91
 2007-05-10 00:08:22 -04:00
Ali Saidi 0dfc29a023 fix partial writes with a functional memory hack 
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached

configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
    fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
    fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
    by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier

--HG--
extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
 2007-05-07 14:42:03 -04:00
Nathan Binkert a575fbd4aa Completely re-work how the scons framework incorporates swig 
and python code into m5 to allow swig an python code to
easily added by any SConscript instead of just the one in
src/python.  This provides SwigSource and PySource for
adding new files to m5 (similar to Source for C++).  Also
provides SimObject for including files that contain SimObject
information and build the m5.objects __init__.py file.

--HG--
extra : convert_revision : 38b50a0629846ef451ed02f96fe3633947df23eb
 2007-04-12 21:20:04 -07:00
Nathan Binkert e04208f046 Fix NextEthernetAddr. 
unproxy() needs to return a new object otherwise all
instances will use the same value.  This fix is more
or less unique to NextEthernetAddr because its use of
the proxy stuff is a bit different than everything else.

--HG--
extra : convert_revision : 2ce452e37d00b9ba76b6abfaec0ad2e0073920d7
 2007-04-12 08:37:55 -07:00
Kevin Lim 5c3f724174 Override addPrivateSplitL1Caches function in order to automatically set the tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond. 
Remove this hack once the caches eventually get fixed.

--HG--
extra : convert_revision : 8c61ac1b6182f57ebbe3bcfeddb5a4f4334d7bc0
 2007-03-29 12:25:47 -04:00
Ali Saidi e8dc1723ee first bit of life from the intel gigabit model 
--HG--
extra : convert_revision : d8944a53f6b585df21651c4e624518d5c49a7837
 2007-03-26 18:40:18 -04:00
Nathan Binkert 21391d494c Cleanup 
--HG--
extra : convert_revision : 31f1b0f760a6eb861652440f9d42aaf123ef4833
 2007-03-06 22:16:18 -08:00
Nathan Binkert 44f215f44d Python parameters types need analogous C++ types 
--HG--
extra : convert_revision : d068dfec69b28d48fc299a4108e165decfaaace7
 2007-03-06 11:16:15 -08:00
Nathan Binkert d55b25cde6 Move all of the parameters of the Root SimObject so they are 
directly configured by python.  Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.

--HG--
extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
 2007-03-06 11:13:43 -08:00
Nathan Binkert f800fddcea Python atexit handlers are called in reverse order. 
Fix things so the stats dump happens last.

--HG--
extra : convert_revision : ea842dbcbb77dd1c715c4e5b57d2470e558c4265
 2007-03-05 20:14:00 -08:00
Ali Saidi 82874eefca Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
 2007-03-03 19:03:22 -05:00
Ali Saidi 1694c65ba1 Add Iob and remove the fake device 
configs/common/FSConfig.py:
    add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy

--HG--
extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
 2007-03-03 19:02:31 -05:00
Ali Saidi 36f43ff6a5 Implement Niagara I/O interface and rework interrupts 
configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
 2007-03-03 17:22:47 -05:00
Nathan Binkert 53f5fda5de Do the default argument stuff in python 
--HG--
extra : convert_revision : 235f85e611a669401c6ddfbdf14244e80eb55888
 2007-03-03 07:45:55 -08:00
Nathan Binkert ffe6bebb05 Factor code out of main.cc and main.i into a bunch of files 
so things are organized in a more sensible manner.  Take apart
finalInit and expose the individual functions which are now
called from python.  Make checkpointing a bit easier to use.

--HG--
extra : convert_revision : f470ddabbb47103e7b4734ef753c40089f2dcd9d
 2007-03-02 22:24:00 -08:00
Nathan Binkert fa4c3d74fe Get rid of the ConsoleListener SimObject and just fold the 
relevant code directly into the SimConsole object.  Now,
you can easily turn off the listen port by just specifying
0 as the port.

--HG--
extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
 2007-02-21 22:14:11 -08:00
Nathan Binkert 2a67f2b08c Fix tracing so it starts right away if --trace-start is not 
specified.

--HG--
extra : convert_revision : 49c1ea0b8c313949124aed84b1055db0b3c55bd8
 2007-02-21 14:08:13 -08:00
Nathan Binkert 4e7f8c0885 Get rid of the stand alone ParamContext since all of the 
relevant stuff has now been moved to python.

--HG--
extra : convert_revision : 608e5ffd0e2b33949a2b183117216f136cfa4484
 2007-02-18 09:31:25 -08:00
Nathan Binkert ee93b48314 Get rid of the Serialize and IntervalStats Param contexts 
since they're no longer used

--HG--
extra : convert_revision : e39590aa03cc4c961d2eb5dab57862811f431e4d
 2007-02-18 09:08:32 -08:00
Nathan Binkert e94103397c Get rid of the Statistics and Statreset ParamContexts, and 
expose all of the relevant functionality to python.  Clean
up the mysql code while we're at it.

--HG--
extra : convert_revision : 5b711202a5a452b8875ebefb136a156b65c24279
 2007-02-17 22:52:32 -08:00
Nathan Binkert 08f024d3ff Default to tracing being disabled in C++, it will be turned 
on in python.  Fix the trace start code so it actually starts
when it is suppsed to.  Make the Exec tracing stuff obey the
trace enabled flag.

--HG--
extra : convert_revision : 634ba0b4f52345d4bf40d43e239cef7ef43e7691
 2007-02-17 20:32:39 -08:00
Ali Saidi e3dcbc94f7 Make mulitple consoles work and be distinguishable from each other 
src/dev/alpha/tsunamireg.h:
    get rid of things that aren't really tsunami registers
src/dev/platform.hh:
src/dev/uart.cc:
    the uart pointer isn't used anymore
src/dev/simconsole.cc:
    make the simconsole print something more useful to distinguish between various consoles in a single system
src/dev/uart8250.hh:
    put the needed uart defines in here rather than including them from tsunamireg
src/python/m5/objects/T1000.py:
    add a console to the T1000 config for the hypervisor

--HG--
extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
 2007-02-13 15:58:06 -05:00
Nathan Binkert d8c7ebf904 Merge all of the execution trace configuration stuff into 
the traceflags infrastructure.  InstExec is now just Exec
and all of the command line options are now trace options.

--HG--
extra : convert_revision : 4adfa9dfbb32622d30ef4e63c06c7d87da793c8f
 2007-02-13 00:59:01 -08:00
Nathan Binkert d7c1436a44 Rearrange traceflags.py so that the file generation only happens if 
the script is invoked as main.  This allows us to import traceflags.py
if we just want the list of available flags.
Embed traceflags.py into the zipfile so it can be accessed from the
python side of things.  With this, print an error on invalid flags and
add --trace-help option that will print out the list of trace flags
that are compiled in.  If a flag is prefixed with a '-', now that flag
will be disabled.

--HG--
extra : convert_revision : 2260a596b07d127c582ff73474dbbdb0583db524
 2007-02-13 00:16:41 -08:00
Nathan Binkert 184decd196 Clean up tracing stuff more, get rid of the trace log since 
its not all that useful. Fix a few bugs with python/C++
integration.

--HG--
extra : convert_revision : a706512f7dc8b0c88f1ff96fe35ab8fbf9548b78
 2007-02-10 15:14:50 -08:00
Nathan Binkert 81c5d0e3d8 Clean up from my last commit to the trace stuff. 
--HG--
extra : convert_revision : b6a975d1c4195a764ba875bc3aaaa064be4955b7
 2007-02-09 16:30:06 -08:00
Nathan Binkert a24ccc1ef2 Get rid of the Trace ParamContext and give python direct 
access to enabling/disabling tracing.  Command line is
unchanged except for the removal of --trace-cycle since
it's not so clear what that means.

--HG--
extra : convert_revision : c0164d92d3615d76d0c6acaabaafd92a9278212a
 2007-02-09 14:39:56 -08:00
Ali Saidi 5c7192daed make sparc fs less chatty 
src/SConscript:
    strip doesn't take a src and dest in solaris

--HG--
extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
 2007-01-31 18:32:27 -05:00
Nathan Binkert cf72942506 Move time forward to Jan 1, 2009 and update stats 
--HG--
extra : convert_revision : 9398362237443dc659f423a342bd27c923e90aea
 2007-01-25 19:14:05 -05:00
Nathan Binkert 73dd0ea357 Instead of passing an int to represent time between python and C++ 
pass the tuple of python's struct_time and interpret that.
Fixes a problem where the local timezone leaked into the time
calculation.  Also fix things so that the unix, python, and RTC
data sheets all get the right time.  Provide both years since 1900
and BCD two digit year.
Put the date back at 1/1/2006 for now.

--HG--
extra : convert_revision : 473244572f468de2cb579a3dd7ae296a6f81f5d7
 2007-01-25 14:59:41 -05:00
Ali Saidi 3af3610c62 add dumb time of day device 
--HG--
extra : convert_revision : 52e51ff49f7ed73065f04707ded06dc7254292c4
 2007-01-21 18:04:40 -05:00
Ali Saidi 7933aade85 add memory mapped disk device 
configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
    add configuration for memory mapped disk
src/dev/sparc/SConscript:
    add memory mapped disk to sconscript

--HG--
extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
 2007-01-09 22:16:49 -05:00
Nathan Binkert e6b4fed75d set __name__ in the root m5 script to __m5_main__ so we can 
tell if the script is run from m5 as the m5 script

--HG--
extra : convert_revision : 06f646cbb8c82444ef345115aa49324a4d3a2c9f
 2007-01-03 10:16:22 -08:00
Nathan Binkert fc45d42d01 Add 'Time' as a parameter type that can accept various 
formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit

--HG--
extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
 2007-01-03 10:12:55 -08:00
Nathan Binkert f6aa2ed47b Merge zizzer.eecs.umich.edu:/bk/newmem 
into  iceaxe.:/Volumes/work/m5/incoming

--HG--
extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
 2006-12-29 16:58:08 -08:00
Nathan Binkert 81e0ac3000 Formatting 
--HG--
extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
 2006-12-29 16:57:45 -08:00
Ali Saidi ba14d6d0e1 Bug fixes in the TLB 
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48

src/arch/sparc/tlb.cc:
    Bug fixes in the TLB
    Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
    Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
    itb should be 64 entries too

--HG--
extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
 2006-12-27 14:38:07 -05:00
Lisa Hsu 385a3ff054 small change to eliminate address range overlap. 
--HG--
extra : convert_revision : c8309a8774265a707c87c4f516bec1f81aff4a79
 2006-12-15 17:58:20 -05:00
Lisa Hsu 5d42fd836b Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
 2006-12-12 21:19:51 -05:00
Ali Saidi ed22eb781d get legion/m5 to first tlb miss fault 
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add sparc error asi
src/arch/sparc/faults.cc:
    put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
    Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
    warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
    add sparc error register code that just does nothing
    fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
    fix implementation of HPSTATE  write
src/cpu/exetrace.cc:
    let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
    add l2 error status register fake devices

--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
 2006-12-07 18:50:33 -05:00
Ali Saidi 92c5a5c8cb More changes to get SPARC fs closer. Now at 1.2M cycles before difference 
configs/common/FSConfig.py:
    seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
    change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
    For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
    Use instruction count from cpu rather than cycles because that is what legion does
    we can change it back after were done with legion
src/base/bitfield.hh:
    add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
    add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
    compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
    change asserts of packet success to if panics wrapped with NDEBUG defines
    so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
    expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
    convert some tabs to spaces
src/python/m5/objects/T1000.py:
    add more fake devices for each l1 bank and each memory controller

--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
 2006-12-04 00:54:40 -05:00
Steve Reinhardt e6d7e8af21 Support better param conversions to/from numeric subclasses. 
--HG--
extra : convert_revision : 2ccb75b0912a384789458710fd9bbb65626f839e
 2006-12-02 22:24:52 -08:00
Steve Reinhardt 4c0014a187 Fix help strings on GenRepl params. 
--HG--
extra : convert_revision : 520814e193b9e86b6410f3ab98d62ed131d295aa
 2006-12-02 22:23:46 -08:00
Ali Saidi 8c4f7a0404 Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory 
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it

configs/common/FSConfig.py:
    We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
    Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
    Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
    Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
    fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
    Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
    Let kernel be none
src/sim/system.cc:
    Let the system kernel be none, but warn about it

--HG--
extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
 2006-11-30 15:51:54 -05:00
Gabe Black f85082e0a0 Added a parameter to set memory to zero. This is to support Legion, and once we can make our own hypervisor binary, we probably won't need it. 
--HG--
extra : convert_revision : 168883e4a5d3760962cd9759a6f41c66f5a6402a
 2006-11-22 23:09:27 -05:00
Gabe Black 0a99750ebf Merge zizzer:/bk/sparcfs 
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 75f3398e38e18eb1f8248e23708d7a8d8cce0fc5
 2006-11-22 15:45:32 -05:00
Gabe Black cd2727694d Add in rom/rams for the nvram, hypervisor description, and partition description. 
--HG--
extra : convert_revision : a49de5fcfbea307c971964b8a68b95eb5d9a2bf4
 2006-11-20 17:59:35 -05:00
Nathan Binkert 31d829d388 Implement current working directory for LiveProcesses 
--HG--
extra : convert_revision : a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
 2006-11-16 12:43:11 -08:00
Gabe Black 74654ddd1f Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemops 
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
 2006-11-16 14:42:44 -05:00
Gabe Black 14ebaa1ecc Merge zizzer.eecs.umich.edu:/bk/newmem/ 
into  zower.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c49b760eac758dbde30867cb638fcb3b790f4721
 2006-11-16 14:41:56 -05:00
Gabe Black cd5b33b9ff Fixes for SPARC_FS 
configs/common/FSConfig.py:
    Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
    Create a T1000 platform
src/arch/sparc/miscregfile.cc:
    Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
    Truncate an ExtMachInst to a MachInst before comparing with Legion.

--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
 2006-11-16 12:34:10 -05:00
Gabe Black ac2c7967f6 Merge zizzer.eecs.umich.edu:/bk/newmem/ 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
 2006-11-14 15:23:23 -05:00
Gabe Black 079dd45417 Merge 141.212.106.238:/home/gblack/m5/newmemmemops 
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem

--HG--
extra : convert_revision : 8e805b9bbd5c64c2e5951384b3c6ef712062d08c
 2006-11-14 15:14:28 -05:00
Gabe Black bc4d15ddd1 Create a stub t1000 platform. 
--HG--
extra : convert_revision : 7e27b23b66c743b4625a1dd9d8d6ba61bff45168
 2006-11-14 15:14:27 -05:00
Ron Dreslinski ac309071af Update phase param in the .py file for the cpus 
--HG--
extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
 2006-11-14 01:13:26 -05:00
Nathan Binkert afed455e77 Expose debugBreakCycle through swig and get rid of 
the Debug param context

--HG--
extra : convert_revision : 40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4
 2006-11-13 12:20:08 -08:00
Nathan Binkert d2d4431752 Create a module called internal where swigged stuff goes. 
Rename cc_main to internal.main

--HG--
extra : convert_revision : e938005f600fbf8a43435e29426a948f4501f072
 2006-11-12 18:49:16 -08:00
Nathan Binkert 8354cfc715 Fix Typo 
--HG--
extra : convert_revision : 4f5b610f364876b29ad0e04f1757e4b42d1f2bd8
 2006-11-11 23:57:20 -08:00
Nathan Binkert b16e559177 Get rid of the ParamContext for pseudo instructions and move 
the parameters to the BaseCPU object.

--HG--
extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e
 2006-11-11 17:22:10 -08:00
Ali Saidi cb172d0332 Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit 
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.

SConstruct:
    Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
    add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
    add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
    add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
    add option to try raw when nothing works
src/cpu/exetrace.cc:
    cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
    change the instruction to be 32 bits because it is
src/mem/physical.cc:
    fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
    Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
    Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
    add the ability to add Addr() together

--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
 2006-11-09 18:22:46 -05:00
Lisa Hsu 64c0d82dec simplify maxtick parsing in both the python and the c++. 
configs/common/Simulation.py:
    simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
    make a new m5 param called MaxTick.
src/sim/host.hh:
    fix the M5 def. of MaxTick
src/sim/main.cc:
    Simplify the MaxTick/num_cycles parsing within main.cc

--HG--
extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
 2006-11-08 15:05:23 -05:00
Kevin Lim 344f72dd62 Remove mem parameter. Should have been removed earlier. 
src/python/m5/objects/BaseCPU.py:
    These parameters should have been removed in an earlier push.

--HG--
extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4
 2006-11-08 13:04:36 -05:00
Kevin Lim e174ec1815 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : 29426cebe81ac077c1a83f50e914ff6955ce81d4
 2006-11-08 11:41:10 -05:00
Ali Saidi f7a35c33d7 add code to operate in lockstep with legion 
src/python/m5/main.py:
    add option to operate in lockstep with legion

--HG--
extra : convert_revision : 2cc90ec0cf7e8d028ee813c2034a77415671a628
 2006-11-07 15:51:37 -05:00
Kevin Lim ea5df46882 Fix error message. 
--HG--
extra : convert_revision : 7ac0f40595c89b0d9352e82e447d25380b038408
 2006-11-07 15:45:03 -05:00
Kevin Lim 244e0c884c Remove hack by setting configuration better. 
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
    No need for specialized init() function any more.
src/python/m5/objects/Tsunami.py:
    Override responder when set by user.  This avoids having bus.responder floating around and not doing anything when the user has specified their own default responder.

--HG--
extra : convert_revision : c547daf15b23a889c98e62bfd53c293c85d7a041
 2006-11-07 14:24:31 -05:00
Ali Saidi bf3223d7ce delete pcifake, tsunamifake. Combine BadAddr/IsaFake into one 
src/SConscript:
    remove pcifake and tsunami fake from sconscript
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
    combine badaddr and isa fake into one
src/python/m5/objects/Pci.py:
    remove pcifake
src/python/m5/objects/Tsunami.py:
    make badaddr derive from isafake

--HG--
extra : convert_revision : 91470db60aa1de6b85827304e27bd3414cc9d8d1
 2006-11-06 16:24:25 -05:00
Kevin Lim 45363ea658 Have bus use the BadAddress device to handle bad addresses. The O3 CPU should be able to boot into Linux with caches on after this change. 
src/mem/bus.cc:
src/mem/bus.hh:
    Bus now will be setup with a default responder, unless the user overrides it.  This default responder should return BadAddress if no matching port is found.
src/python/m5/objects/Bus.py:
    Bus now has a default responder for FS mode if the user doesn't override it.  It returns BadAddress if no matching port is found.
src/python/m5/objects/Tsunami.py:
    Add bad address device.  Also record when the user has specified their own default responder.

--HG--
extra : convert_revision : 59070477ae313ee711b2d59baa2369c9a91c5b85
 2006-11-02 15:20:37 -05:00
Ali Saidi 0f98905ecc Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 4db140e6e8408b3ed39da327515b8e88a2701e6b
 2006-10-24 12:59:19 -04:00
Lisa Hsu 764f27a0c9 Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
 2006-10-23 18:46:05 -04:00
Lisa Hsu 4da3938ed9 get rid of the "resume" step at the end of changeToTiming/Atomic because this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok. 
--HG--
extra : convert_revision : 7530cf140844e18cc26df80057f8760f29ec952b
 2006-10-23 18:45:30 -04:00
Ron Dreslinski 28e9641c2c Use fixPacket function everywhere. 
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
    Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Use fix Packet function
src/mem/packet.cc:
    Fix an assert that was checking the wrong thing
src/mem/tport.cc:
    Properly detect if we need to do the access to the functional device

--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
 2006-10-20 13:01:21 -04:00
Ali Saidi 7be58fd5f4 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : c0f9bde20585b3811ff906728b003072b69696b5
 2006-10-20 13:00:15 -04:00
Ali Saidi 32384b2f6b still working on getting past initialization 
--HG--
extra : convert_revision : 7a5fccb9a19d363e479ef24012a7b8598272eaa9
 2006-10-20 13:00:05 -04:00
Lisa Hsu 75ecd3be60 how did i not commit this already? the other way doesn't seem to work, need to convert to System ptr first to access System method. 
src/python/m5/SimObject.py:
    how did i not commit this already?  the other way doesn't seem to work.

--HG--
extra : convert_revision : 55737d3d10742a1913a376d1febbc5809f2fab8f
 2006-10-18 18:04:53 -04:00
Steve Reinhardt 6cd187e1f0 Get rid of obsolete in-cache copy support. 
--HG--
extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
 2006-10-18 08:16:22 -07:00