Factor code out of main.cc and main.i into a bunch of files
so things are organized in a more sensible manner. Take apart finalInit and expose the individual functions which are now called from python. Make checkpointing a bit easier to use. --HG-- extra : convert_revision : f470ddabbb47103e7b4734ef753c40089f2dcd9d
This commit is contained in:
parent
4e8d2d1593
commit
ffe6bebb05
20 changed files with 857 additions and 392 deletions
|
@ -131,15 +131,19 @@ base_sources = Split('''
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mem/cache/cache_builder.cc
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python/swig/init.cc
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python/swig/core_wrap.cc
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python/swig/debug_wrap.cc
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python/swig/main_wrap.cc
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python/swig/event_wrap.cc
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python/swig/random_wrap.cc
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python/swig/sim_object_wrap.cc
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python/swig/stats_wrap.cc
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python/swig/trace_wrap.cc
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python/swig/pyevent.cc
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python/swig/pyobject.cc
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sim/async.cc
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sim/builder.cc
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sim/core.cc
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sim/debug.cc
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sim/eventq.cc
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sim/faults.cc
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@ -149,6 +153,7 @@ base_sources = Split('''
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sim/serialize.cc
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sim/sim_events.cc
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sim/sim_object.cc
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sim/simulate.cc
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sim/startup.cc
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sim/stat_control.cc
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sim/system.cc
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@ -107,10 +107,11 @@ def swig_it(module):
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'-o ${TARGETS[0]} $SOURCES')
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swig_modules.append(module)
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swig_it('main')
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swig_it('core')
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swig_it('debug')
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swig_it('event')
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swig_it('random')
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swig_it('sim_object')
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swig_it('stats')
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swig_it('trace')
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@ -693,7 +693,7 @@ class SimObject(object):
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def getCCObject(self):
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if not self._ccObject:
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self._ccObject = -1 # flag to catch cycles in recursion
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self._ccObject = internal.main.createSimObject(self.path())
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self._ccObject = internal.sim_object.createSimObject(self.path())
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elif self._ccObject == -1:
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raise RuntimeError, "%s: recursive call to getCCObject()" \
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% self.path()
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@ -727,13 +727,13 @@ class SimObject(object):
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# i don't know if there's a better way to do this - calling
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# setMemoryMode directly from self._ccObject results in calling
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# SimObject::setMemoryMode, not the System::setMemoryMode
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system_ptr = internal.main.convertToSystemPtr(self._ccObject)
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system_ptr = internal.sim_object.convertToSystemPtr(self._ccObject)
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system_ptr.setMemoryMode(mode)
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for child in self._children.itervalues():
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child.changeTiming(mode)
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def takeOverFrom(self, old_cpu):
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cpu_ptr = internal.main.convertToBaseCPUPtr(old_cpu._ccObject)
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cpu_ptr = internal.sim_object.convertToBaseCPUPtr(old_cpu._ccObject)
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self._ccObject.takeOverFrom(cpu_ptr)
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# generate output file for 'dot' to display as a pretty graph.
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@ -27,14 +27,16 @@
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# Authors: Nathan Binkert
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# Steve Reinhardt
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import atexit, os, sys
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import atexit
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import os
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import sys
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# import the SWIG-wrapped main C++ functions
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import internal
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# import a few SWIG-wrapped items (those that are likely to be used
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# directly by user scripts) completely into this module for
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# convenience
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from internal.main import simulate, SimLoopExitEvent
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from internal.event import SimLoopExitEvent
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# import the m5 compile options
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import defines
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@ -85,27 +87,60 @@ def instantiate(root):
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root.print_ini()
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sys.stdout.close() # close config.ini
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sys.stdout = sys.__stdout__ # restore to original
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internal.main.loadIniFile(resolveSimObject) # load config.ini into C++
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# load config.ini into C++
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internal.core.loadIniFile(resolveSimObject)
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# Initialize the global statistics
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internal.stats.initSimStats()
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root.createCCObject()
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root.connectPorts()
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internal.main.finalInit()
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noDot = True # temporary until we fix dot
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if not noDot:
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dot = pydot.Dot()
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instance.outputDot(dot)
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dot.orientation = "portrait"
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dot.size = "8.5,11"
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dot.ranksep="equally"
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dot.rank="samerank"
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dot.write("config.dot")
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dot.write_ps("config.ps")
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# Do a second pass to finish initializing the sim objects
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internal.sim_object.initAll()
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# Do a third pass to initialize statistics
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internal.sim_object.regAllStats()
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# Check to make sure that the stats package is properly initialized
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internal.stats.check()
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# Reset to put the stats in a consistent state.
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internal.stats.reset()
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def doDot(root):
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dot = pydot.Dot()
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instance.outputDot(dot)
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dot.orientation = "portrait"
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dot.size = "8.5,11"
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dot.ranksep="equally"
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dot.rank="samerank"
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dot.write("config.dot")
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dot.write_ps("config.ps")
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need_resume = []
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need_startup = True
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def simulate(*args, **kwargs):
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global need_resume, need_startup
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if need_startup:
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internal.core.SimStartup()
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need_startup = False
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for root in need_resume:
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resume(root)
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need_resume = []
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return internal.event.simulate(*args, **kwargs)
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# Export curTick to user script.
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def curTick():
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return internal.main.cvar.curTick
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return internal.event.cvar.curTick
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# register our C++ exit callback function with Python
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atexit.register(internal.main.doExitCleanup)
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atexit.register(internal.core.doExitCleanup)
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atexit.register(internal.stats.dump)
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# This loops until all objects have been fully drained.
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def doDrain(root):
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@ -119,7 +154,7 @@ def doDrain(root):
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# be drained.
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def drain(root):
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all_drained = False
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drain_event = internal.main.createCountedDrain()
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drain_event = internal.event.createCountedDrain()
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unready_objects = root.startDrain(drain_event, True)
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# If we've got some objects that can't drain immediately, then simulate
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if unready_objects > 0:
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@ -127,7 +162,7 @@ def drain(root):
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simulate()
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else:
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all_drained = True
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internal.main.cleanupCountedDrain(drain_event)
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internal.event.cleanupCountedDrain(drain_event)
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return all_drained
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def resume(root):
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@ -135,16 +170,16 @@ def resume(root):
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def checkpoint(root, dir):
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if not isinstance(root, objects.Root):
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raise TypeError, "Object is not a root object. Checkpoint must be called on a root object."
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raise TypeError, "Checkpoint must be called on a root object."
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doDrain(root)
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print "Writing checkpoint"
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internal.main.serializeAll(dir)
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internal.sim_object.serializeAll(dir)
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resume(root)
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def restoreCheckpoint(root, dir):
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print "Restoring from checkpoint"
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internal.main.unserializeAll(dir)
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resume(root)
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internal.sim_object.unserializeAll(dir)
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need_resume.append(root)
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def changeToAtomic(system):
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if not isinstance(system, objects.Root) and not isinstance(system, objects.System):
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@ -152,7 +187,7 @@ def changeToAtomic(system):
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"called on a root object."
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doDrain(system)
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print "Changing memory mode to atomic"
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system.changeTiming(internal.main.SimObject.Atomic)
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system.changeTiming(internal.sim_object.SimObject.Atomic)
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def changeToTiming(system):
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if not isinstance(system, objects.Root) and not isinstance(system, objects.System):
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@ -160,7 +195,7 @@ def changeToTiming(system):
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"called on a root object."
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doDrain(system)
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print "Changing memory mode to timing"
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system.changeTiming(internal.main.SimObject.Timing)
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system.changeTiming(internal.sim_object.SimObject.Timing)
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def switchCpus(cpuList):
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print "switching cpus"
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@ -180,7 +215,7 @@ def switchCpus(cpuList):
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raise TypeError, "%s is not of type BaseCPU" % cpu
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# Drain all of the individual CPUs
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drain_event = internal.main.createCountedDrain()
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drain_event = internal.event.createCountedDrain()
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unready_cpus = 0
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for old_cpu in old_cpus:
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unready_cpus += old_cpu.startDrain(drain_event, False)
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@ -188,7 +223,7 @@ def switchCpus(cpuList):
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if unready_cpus > 0:
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drain_event.setCount(unready_cpus)
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simulate()
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internal.main.cleanupCountedDrain(drain_event)
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internal.event.cleanupCountedDrain(drain_event)
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# Now all of the CPUs are ready to be switched out
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for old_cpu in old_cpus:
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old_cpu._ccObject.switchOut()
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@ -198,6 +233,14 @@ def switchCpus(cpuList):
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new_cpu._ccObject.resume()
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index += 1
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def dumpStats():
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print 'Dumping stats'
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internal.stats.dump()
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def resetStats():
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print 'Resetting stats'
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internal.stats.reset()
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# Since we have so many mutual imports in this package, we should:
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# 1. Put all intra-package imports at the *bottom* of the file, unless
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# they're absolutely needed before that (for top-level statements
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@ -240,7 +240,7 @@ def main():
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print "M5 Simulator System"
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print brief_copyright
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print
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print "M5 compiled %s" % internal.main.cvar.compileDate;
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print "M5 compiled %s" % internal.core.cvar.compileDate;
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print "M5 started %s" % datetime.now().ctime()
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print "M5 executing on %s" % socket.gethostname()
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print "command line:",
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@ -256,7 +256,7 @@ def main():
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usage(2)
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# tell C++ about output directory
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internal.main.setOutputDir(options.outdir)
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internal.core.setOutputDir(options.outdir)
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# update the system path with elements from the -p option
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sys.path[0:0] = options.path
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@ -894,9 +894,8 @@ class PortRef(object):
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if self.ccConnected: # already done this
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return
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peer = self.peer
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internal.main.connectPorts(self.simobj.getCCObject(), self.name,
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self.index, peer.simobj.getCCObject(),
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peer.name, peer.index)
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internal.sim_object.connectPorts(self.simobj.getCCObject(), self.name,
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self.index, peer.simobj.getCCObject(), peer.name, peer.index)
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self.ccConnected = True
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peer.ccConnected = True
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|
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57
src/python/swig/core.i
Normal file
57
src/python/swig/core.i
Normal file
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@ -0,0 +1,57 @@
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/*
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* Copyright (c) 2006 The Regents of The University of Michigan
|
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* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
* Steve Reinhardt
|
||||
*/
|
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|
||||
%module core
|
||||
|
||||
%{
|
||||
#include "python/swig/pyobject.hh"
|
||||
|
||||
#include "sim/core.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/startup.hh"
|
||||
|
||||
extern const char *compileDate;
|
||||
%}
|
||||
|
||||
%include "std_string.i"
|
||||
|
||||
void setOutputDir(const std::string &dir);
|
||||
void loadIniFile(PyObject *);
|
||||
void SimStartup();
|
||||
void doExitCleanup();
|
||||
|
||||
char *compileDate;
|
||||
|
||||
%wrapper %{
|
||||
// fix up module name to reflect the fact that it's inside the m5 package
|
||||
#undef SWIG_name
|
||||
#define SWIG_name "m5.internal._core"
|
||||
%}
|
|
@ -33,19 +33,48 @@
|
|||
%{
|
||||
#include "python/swig/pyevent.hh"
|
||||
|
||||
inline void
|
||||
create(PyObject *object, Tick when)
|
||||
{
|
||||
new PythonEvent(object, when);
|
||||
}
|
||||
#include "sim/sim_events.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
#include "sim/simulate.hh"
|
||||
%}
|
||||
|
||||
%include "stdint.i"
|
||||
%include "std_string.i"
|
||||
%include "sim/host.hh"
|
||||
|
||||
%inline %{
|
||||
extern void create(PyObject *object, Tick when);
|
||||
%}
|
||||
void create(PyObject *object, Tick when);
|
||||
|
||||
class Event;
|
||||
class CountedDrainEvent : public Event {
|
||||
public:
|
||||
void setCount(int _count);
|
||||
};
|
||||
|
||||
CountedDrainEvent *createCountedDrain();
|
||||
void cleanupCountedDrain(Event *drain_event);
|
||||
|
||||
%immutable curTick;
|
||||
Tick curTick;
|
||||
|
||||
// minimal definition of SimExitEvent interface to wrap
|
||||
class SimLoopExitEvent {
|
||||
public:
|
||||
std::string getCause();
|
||||
int getCode();
|
||||
SimLoopExitEvent(EventQueue *q, Tick _when, Tick _repeat,
|
||||
const std::string &_cause, int c = 0);
|
||||
};
|
||||
|
||||
%exception simulate {
|
||||
$action
|
||||
if (!result) {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
SimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
|
||||
void exitSimLoop(const std::string &message, int exit_code);
|
||||
|
||||
Tick curTick;
|
||||
|
||||
%wrapper %{
|
||||
// fix up module name to reflect the fact that it's inside the m5 package
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#define __PYTHON_SWIG_PYEVENT_HH__
|
||||
|
||||
#include "sim/eventq.hh"
|
||||
#include "sim/sim_events.hh"
|
||||
|
||||
class PythonEvent : public Event
|
||||
{
|
||||
|
@ -45,4 +46,29 @@ class PythonEvent : public Event
|
|||
virtual void process();
|
||||
};
|
||||
|
||||
inline void
|
||||
create(PyObject *object, Tick when)
|
||||
{
|
||||
new PythonEvent(object, when);
|
||||
}
|
||||
|
||||
inline Event *
|
||||
createCountedDrain()
|
||||
{
|
||||
return new CountedDrainEvent();
|
||||
}
|
||||
|
||||
inline void
|
||||
cleanupCountedDrain(Event *counted_drain)
|
||||
{
|
||||
CountedDrainEvent *event =
|
||||
dynamic_cast<CountedDrainEvent *>(counted_drain);
|
||||
if (event == NULL) {
|
||||
fatal("Called cleanupCountedDrain() on an event that was not "
|
||||
"a CountedDrainEvent.");
|
||||
}
|
||||
assert(event->getCount() == 0);
|
||||
delete event;
|
||||
}
|
||||
|
||||
#endif // __PYTHON_SWIG_PYEVENT_HH__
|
||||
|
|
137
src/python/swig/pyobject.cc
Normal file
137
src/python/swig/pyobject.cc
Normal file
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
*/
|
||||
|
||||
#include <Python.h>
|
||||
|
||||
#include <string>
|
||||
|
||||
#include "base/inifile.hh"
|
||||
#include "base/output.hh"
|
||||
#include "mem/mem_object.hh"
|
||||
#include "mem/port.hh"
|
||||
#include "sim/builder.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
/**
|
||||
* Look up a MemObject port. Helper function for connectPorts().
|
||||
*/
|
||||
Port *
|
||||
lookupPort(SimObject *so, const std::string &name, int i)
|
||||
{
|
||||
MemObject *mo = dynamic_cast<MemObject *>(so);
|
||||
if (mo == NULL) {
|
||||
warn("error casting SimObject %s to MemObject", so->name());
|
||||
return NULL;
|
||||
}
|
||||
|
||||
Port *p = mo->getPort(name, i);
|
||||
if (p == NULL)
|
||||
warn("error looking up port %s on object %s", name, so->name());
|
||||
return p;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Connect the described MemObject ports. Called from Python via SWIG.
|
||||
*/
|
||||
int
|
||||
connectPorts(SimObject *o1, const std::string &name1, int i1,
|
||||
SimObject *o2, const std::string &name2, int i2)
|
||||
{
|
||||
Port *p1 = lookupPort(o1, name1, i1);
|
||||
Port *p2 = lookupPort(o2, name2, i2);
|
||||
|
||||
if (p1 == NULL || p2 == NULL) {
|
||||
warn("connectPorts: port lookup error");
|
||||
return 0;
|
||||
}
|
||||
|
||||
p1->setPeer(p2);
|
||||
p2->setPeer(p1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
inline IniFile &
|
||||
inifile()
|
||||
{
|
||||
static IniFile inifile;
|
||||
return inifile;
|
||||
}
|
||||
|
||||
SimObject *
|
||||
createSimObject(const string &name)
|
||||
{
|
||||
return SimObjectClass::createObject(inifile(), name);
|
||||
}
|
||||
|
||||
/**
|
||||
* Pointer to the Python function that maps names to SimObjects.
|
||||
*/
|
||||
PyObject *resolveFunc = NULL;
|
||||
|
||||
/**
|
||||
* Convert a pointer to the Python object that SWIG wraps around a C++
|
||||
* SimObject pointer back to the actual C++ pointer. See main.i.
|
||||
*/
|
||||
extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
|
||||
|
||||
SimObject *
|
||||
resolveSimObject(const string &name)
|
||||
{
|
||||
PyObject *pyPtr = PyEval_CallFunction(resolveFunc, "(s)", name.c_str());
|
||||
if (pyPtr == NULL) {
|
||||
PyErr_Print();
|
||||
panic("resolveSimObject: failure on call to Python for %s", name);
|
||||
}
|
||||
|
||||
SimObject *simObj = convertSwigSimObjectPtr(pyPtr);
|
||||
if (simObj == NULL)
|
||||
panic("resolveSimObject: failure on pointer conversion for %s", name);
|
||||
|
||||
return simObj;
|
||||
}
|
||||
|
||||
/**
|
||||
* Load config.ini into C++ database. Exported to Python via SWIG;
|
||||
* invoked from m5.instantiate().
|
||||
*/
|
||||
void
|
||||
loadIniFile(PyObject *_resolveFunc)
|
||||
{
|
||||
resolveFunc = _resolveFunc;
|
||||
configStream = simout.find("config.out");
|
||||
|
||||
// The configuration database is now complete; start processing it.
|
||||
inifile().load(simout.resolve("config.ini"));
|
||||
}
|
||||
|
94
src/python/swig/pyobject.hh
Normal file
94
src/python/swig/pyobject.hh
Normal file
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
*/
|
||||
|
||||
#include <Python.h>
|
||||
|
||||
#include "cpu/base.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/serialize.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
#include "sim/system.hh"
|
||||
|
||||
SimObject *createSimObject(const std::string &name);
|
||||
extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
|
||||
SimObject *resolveSimObject(const std::string &name);
|
||||
void loadIniFile(PyObject *_resolveFunc);
|
||||
|
||||
|
||||
/**
|
||||
* Connect the described MemObject ports. Called from Python via SWIG.
|
||||
*/
|
||||
int connectPorts(SimObject *o1, const std::string &name1, int i1,
|
||||
SimObject *o2, const std::string &name2, int i2);
|
||||
|
||||
inline BaseCPU *
|
||||
convertToBaseCPUPtr(SimObject *obj)
|
||||
{
|
||||
BaseCPU *ptr = dynamic_cast<BaseCPU *>(obj);
|
||||
|
||||
if (ptr == NULL)
|
||||
warn("Casting to BaseCPU pointer failed");
|
||||
return ptr;
|
||||
}
|
||||
|
||||
inline System *
|
||||
convertToSystemPtr(SimObject *obj)
|
||||
{
|
||||
System *ptr = dynamic_cast<System *>(obj);
|
||||
|
||||
if (ptr == NULL)
|
||||
warn("Casting to System pointer failed");
|
||||
return ptr;
|
||||
}
|
||||
|
||||
inline void
|
||||
initAll()
|
||||
{
|
||||
SimObject::initAll();
|
||||
}
|
||||
|
||||
inline void
|
||||
regAllStats()
|
||||
{
|
||||
SimObject::regAllStats();
|
||||
}
|
||||
|
||||
inline void
|
||||
serializeAll(const std::string &cpt_dir)
|
||||
{
|
||||
Serializable::serializeAll(cpt_dir);
|
||||
}
|
||||
|
||||
inline void
|
||||
unserializeAll(const std::string &cpt_dir)
|
||||
{
|
||||
Serializable::unserializeAll(cpt_dir);
|
||||
}
|
||||
|
101
src/python/swig/sim_object.i
Normal file
101
src/python/swig/sim_object.i
Normal file
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
*/
|
||||
|
||||
%module sim_object
|
||||
|
||||
%{
|
||||
#include "python/swig/pyobject.hh"
|
||||
%}
|
||||
|
||||
// import these files for SWIG to wrap
|
||||
%include "stdint.i"
|
||||
%include "std_string.i"
|
||||
%include "sim/host.hh"
|
||||
|
||||
class BaseCPU;
|
||||
|
||||
class SimObject {
|
||||
public:
|
||||
enum State {
|
||||
Running,
|
||||
Draining,
|
||||
Drained
|
||||
};
|
||||
|
||||
enum MemoryMode {
|
||||
Invalid,
|
||||
Atomic,
|
||||
Timing
|
||||
};
|
||||
|
||||
unsigned int drain(Event *drain_event);
|
||||
void resume();
|
||||
void switchOut();
|
||||
void takeOverFrom(BaseCPU *cpu);
|
||||
SimObject(const std::string &_name);
|
||||
};
|
||||
|
||||
class System {
|
||||
private:
|
||||
System();
|
||||
public:
|
||||
void setMemoryMode(SimObject::MemoryMode mode);
|
||||
};
|
||||
|
||||
SimObject *createSimObject(const std::string &name);
|
||||
|
||||
int connectPorts(SimObject *o1, const std::string &name1, int i1,
|
||||
SimObject *o2, const std::string &name2, int i2);
|
||||
|
||||
BaseCPU *convertToBaseCPUPtr(SimObject *obj);
|
||||
System *convertToSystemPtr(SimObject *obj);
|
||||
|
||||
void serializeAll(const std::string &cpt_dir);
|
||||
void unserializeAll(const std::string &cpt_dir);
|
||||
|
||||
void initAll();
|
||||
void regAllStats();
|
||||
|
||||
%wrapper %{
|
||||
// fix up module name to reflect the fact that it's inside the m5 package
|
||||
#undef SWIG_name
|
||||
#define SWIG_name "m5.internal._sim_object"
|
||||
|
||||
// Convert a pointer to the Python object that SWIG wraps around a
|
||||
// C++ SimObject pointer back to the actual C++ pointer.
|
||||
SimObject *
|
||||
convertSwigSimObjectPtr(PyObject *pyObj)
|
||||
{
|
||||
SimObject *so;
|
||||
if (SWIG_ConvertPtr(pyObj, (void **) &so, SWIGTYPE_p_SimObject, 0) == -1)
|
||||
return NULL;
|
||||
return so;
|
||||
}
|
||||
%}
|
|
@ -48,6 +48,7 @@ void initMySQL(std::string host, std::string database, std::string user = "",
|
|||
|
||||
void StatEvent(bool dump, bool reset, Tick when = curTick, Tick repeat = 0);
|
||||
|
||||
void check();
|
||||
void dump();
|
||||
void reset();
|
||||
|
||||
|
|
38
src/sim/async.cc
Normal file
38
src/sim/async.cc
Normal file
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2000-2005 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
*/
|
||||
|
||||
volatile bool async_event = false;
|
||||
volatile bool async_statdump = false;
|
||||
volatile bool async_statreset = false;
|
||||
volatile bool async_exit = false;
|
||||
volatile bool async_io = false;
|
||||
volatile bool async_alarm = false;
|
||||
volatile bool async_exception = false;
|
||||
|
|
@ -43,7 +43,8 @@
|
|||
/// @note See the PollQueue object (in pollevent.hh) for the use of async_io and async_alarm.
|
||||
//@{
|
||||
extern volatile bool async_event; ///< Some asynchronous event has happened.
|
||||
extern volatile bool async_dump; ///< Async request to dump stats.
|
||||
extern volatile bool async_statdump; ///< Async request to dump stats.
|
||||
extern volatile bool async_statreset; ///< Async request to reset stats.
|
||||
extern volatile bool async_exit; ///< Async request to exit simulator.
|
||||
extern volatile bool async_io; ///< Async I/O request (SIGIO).
|
||||
extern volatile bool async_alarm; ///< Async alarm event (SIGALRM).
|
||||
|
|
76
src/sim/core.cc
Normal file
76
src/sim/core.cc
Normal file
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
* Steve Reinhardt
|
||||
*/
|
||||
|
||||
#include <iostream>
|
||||
#include <string>
|
||||
|
||||
#include "base/callback.hh"
|
||||
#include "base/output.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
void
|
||||
setOutputDir(const string &dir)
|
||||
{
|
||||
simout.setDirectory(dir);
|
||||
}
|
||||
|
||||
/**
|
||||
* Queue of C++ callbacks to invoke on simulator exit.
|
||||
*/
|
||||
inline CallbackQueue &
|
||||
exitCallbacks()
|
||||
{
|
||||
static CallbackQueue theQueue;
|
||||
return theQueue;
|
||||
}
|
||||
|
||||
/**
|
||||
* Register an exit callback.
|
||||
*/
|
||||
void
|
||||
registerExitCallback(Callback *callback)
|
||||
{
|
||||
exitCallbacks().add(callback);
|
||||
}
|
||||
|
||||
/**
|
||||
* Do C++ simulator exit processing. Exported to SWIG to be invoked
|
||||
* when simulator terminates via Python's atexit mechanism.
|
||||
*/
|
||||
void
|
||||
doExitCleanup()
|
||||
{
|
||||
exitCallbacks().process();
|
||||
exitCallbacks().clear();
|
||||
|
||||
cout.flush();
|
||||
}
|
40
src/sim/core.hh
Normal file
40
src/sim/core.hh
Normal file
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
* Steve Reinhardt
|
||||
*/
|
||||
|
||||
#include <Python.h>
|
||||
#include <string>
|
||||
|
||||
#include "base/callback.hh"
|
||||
|
||||
void setOutputDir(const std::string &dir);
|
||||
|
||||
void registerExitCallback(Callback *callback);
|
||||
void doExitCleanup();
|
355
src/sim/main.cc
355
src/sim/main.cc
|
@ -25,79 +25,38 @@
|
|||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Steve Raasch
|
||||
* Nathan Binkert
|
||||
* Steve Reinhardt
|
||||
* Authors: Nathan Binkert
|
||||
*/
|
||||
|
||||
///
|
||||
/// @file sim/main.cc
|
||||
///
|
||||
#include <Python.h> // must be before system headers... see Python docs
|
||||
#include <Python.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <errno.h>
|
||||
#include <libgen.h>
|
||||
#include <stdlib.h>
|
||||
#include <signal.h>
|
||||
#include <getopt.h>
|
||||
|
||||
#include <list>
|
||||
#include <iostream>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include "base/callback.hh"
|
||||
#include "base/inifile.hh"
|
||||
#include "base/cprintf.hh"
|
||||
#include "base/misc.hh"
|
||||
#include "base/output.hh"
|
||||
#include "base/pollevent.hh"
|
||||
#include "base/statistics.hh"
|
||||
#include "base/stats/output.hh"
|
||||
#include "base/str.hh"
|
||||
#include "base/time.hh"
|
||||
#include "config/pythonhome.hh"
|
||||
#include "cpu/base.hh"
|
||||
#include "cpu/smt.hh"
|
||||
#include "mem/mem_object.hh"
|
||||
#include "mem/port.hh"
|
||||
#include "python/swig/init.hh"
|
||||
#include "sim/async.hh"
|
||||
#include "sim/builder.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/serialize.hh"
|
||||
#include "sim/sim_events.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
#include "sim/system.hh"
|
||||
#include "sim/stat_control.hh"
|
||||
#include "sim/stats.hh"
|
||||
#include "sim/root.hh"
|
||||
|
||||
using namespace std;
|
||||
|
||||
// See async.h.
|
||||
volatile bool async_event = false;
|
||||
volatile bool async_dump = false;
|
||||
volatile bool async_dumpreset = false;
|
||||
volatile bool async_exit = false;
|
||||
volatile bool async_io = false;
|
||||
volatile bool async_alarm = false;
|
||||
volatile bool async_exception = false;
|
||||
|
||||
/// Stats signal handler.
|
||||
void
|
||||
dumpStatsHandler(int sigtype)
|
||||
{
|
||||
async_event = true;
|
||||
async_dump = true;
|
||||
async_statdump = true;
|
||||
}
|
||||
|
||||
void
|
||||
dumprstStatsHandler(int sigtype)
|
||||
{
|
||||
async_event = true;
|
||||
async_dumpreset = true;
|
||||
async_statdump = true;
|
||||
async_statreset = true;
|
||||
}
|
||||
|
||||
/// Exit signal handler.
|
||||
|
@ -112,7 +71,7 @@ exitNowHandler(int sigtype)
|
|||
void
|
||||
abortHandler(int sigtype)
|
||||
{
|
||||
cerr << "Program aborted at cycle " << curTick << endl;
|
||||
ccprintf(cerr, "Program aborted at cycle %d\n", curTick);
|
||||
}
|
||||
|
||||
int
|
||||
|
@ -160,301 +119,3 @@ main(int argc, char **argv)
|
|||
// clean up Python intepreter.
|
||||
Py_Finalize();
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
setOutputDir(const string &dir)
|
||||
{
|
||||
simout.setDirectory(dir);
|
||||
}
|
||||
|
||||
|
||||
IniFile inifile;
|
||||
|
||||
SimObject *
|
||||
createSimObject(const string &name)
|
||||
{
|
||||
return SimObjectClass::createObject(inifile, name);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Pointer to the Python function that maps names to SimObjects.
|
||||
*/
|
||||
PyObject *resolveFunc = NULL;
|
||||
|
||||
/**
|
||||
* Convert a pointer to the Python object that SWIG wraps around a C++
|
||||
* SimObject pointer back to the actual C++ pointer. See main.i.
|
||||
*/
|
||||
extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
|
||||
|
||||
|
||||
SimObject *
|
||||
resolveSimObject(const string &name)
|
||||
{
|
||||
PyObject *pyPtr = PyEval_CallFunction(resolveFunc, "(s)", name.c_str());
|
||||
if (pyPtr == NULL) {
|
||||
PyErr_Print();
|
||||
panic("resolveSimObject: failure on call to Python for %s", name);
|
||||
}
|
||||
|
||||
SimObject *simObj = convertSwigSimObjectPtr(pyPtr);
|
||||
if (simObj == NULL)
|
||||
panic("resolveSimObject: failure on pointer conversion for %s", name);
|
||||
|
||||
return simObj;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Load config.ini into C++ database. Exported to Python via SWIG;
|
||||
* invoked from m5.instantiate().
|
||||
*/
|
||||
void
|
||||
loadIniFile(PyObject *_resolveFunc)
|
||||
{
|
||||
resolveFunc = _resolveFunc;
|
||||
configStream = simout.find("config.out");
|
||||
|
||||
// The configuration database is now complete; start processing it.
|
||||
inifile.load(simout.resolve("config.ini"));
|
||||
|
||||
// Initialize statistics database
|
||||
Stats::initSimStats();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Look up a MemObject port. Helper function for connectPorts().
|
||||
*/
|
||||
Port *
|
||||
lookupPort(SimObject *so, const std::string &name, int i)
|
||||
{
|
||||
MemObject *mo = dynamic_cast<MemObject *>(so);
|
||||
if (mo == NULL) {
|
||||
warn("error casting SimObject %s to MemObject", so->name());
|
||||
return NULL;
|
||||
}
|
||||
|
||||
Port *p = mo->getPort(name, i);
|
||||
if (p == NULL)
|
||||
warn("error looking up port %s on object %s", name, so->name());
|
||||
return p;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Connect the described MemObject ports. Called from Python via SWIG.
|
||||
*/
|
||||
int
|
||||
connectPorts(SimObject *o1, const std::string &name1, int i1,
|
||||
SimObject *o2, const std::string &name2, int i2)
|
||||
{
|
||||
Port *p1 = lookupPort(o1, name1, i1);
|
||||
Port *p2 = lookupPort(o2, name2, i2);
|
||||
|
||||
if (p1 == NULL || p2 == NULL) {
|
||||
warn("connectPorts: port lookup error");
|
||||
return 0;
|
||||
}
|
||||
|
||||
p1->setPeer(p2);
|
||||
p2->setPeer(p1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Do final initialization steps after object construction but before
|
||||
* start of simulation.
|
||||
*/
|
||||
void
|
||||
finalInit()
|
||||
{
|
||||
// Do a second pass to finish initializing the sim objects
|
||||
SimObject::initAll();
|
||||
|
||||
// Restore checkpointed state, if any.
|
||||
#if 0
|
||||
configHierarchy.unserializeSimObjects();
|
||||
#endif
|
||||
|
||||
SimObject::regAllStats();
|
||||
|
||||
// Check to make sure that the stats package is properly initialized
|
||||
Stats::check();
|
||||
|
||||
// Reset to put the stats in a consistent state.
|
||||
Stats::reset();
|
||||
|
||||
SimStartup();
|
||||
}
|
||||
|
||||
/** Simulate for num_cycles additional cycles. If num_cycles is -1
|
||||
* (the default), do not limit simulation; some other event must
|
||||
* terminate the loop. Exported to Python via SWIG.
|
||||
* @return The SimLoopExitEvent that caused the loop to exit.
|
||||
*/
|
||||
SimLoopExitEvent *
|
||||
simulate(Tick num_cycles = MaxTick)
|
||||
{
|
||||
warn("Entering event queue @ %d. Starting simulation...\n", curTick);
|
||||
|
||||
if (num_cycles < 0)
|
||||
fatal("simulate: num_cycles must be >= 0 (was %d)\n", num_cycles);
|
||||
else if (curTick + num_cycles < 0) //Overflow
|
||||
num_cycles = MaxTick;
|
||||
else
|
||||
num_cycles = curTick + num_cycles;
|
||||
|
||||
Event *limit_event = schedExitSimLoop("simulate() limit reached",
|
||||
num_cycles);
|
||||
|
||||
while (1) {
|
||||
// there should always be at least one event (the SimLoopExitEvent
|
||||
// we just scheduled) in the queue
|
||||
assert(!mainEventQueue.empty());
|
||||
assert(curTick <= mainEventQueue.nextTick() &&
|
||||
"event scheduled in the past");
|
||||
|
||||
// forward current cycle to the time of the first event on the
|
||||
// queue
|
||||
curTick = mainEventQueue.nextTick();
|
||||
Event *exit_event = mainEventQueue.serviceOne();
|
||||
if (exit_event != NULL) {
|
||||
// hit some kind of exit event; return to Python
|
||||
// event must be subclass of SimLoopExitEvent...
|
||||
SimLoopExitEvent *se_event = dynamic_cast<SimLoopExitEvent *>(exit_event);
|
||||
if (se_event == NULL)
|
||||
panic("Bogus exit event class!");
|
||||
|
||||
// if we didn't hit limit_event, delete it
|
||||
if (se_event != limit_event) {
|
||||
assert(limit_event->scheduled());
|
||||
limit_event->deschedule();
|
||||
delete limit_event;
|
||||
}
|
||||
|
||||
return se_event;
|
||||
}
|
||||
|
||||
if (async_event) {
|
||||
async_event = false;
|
||||
if (async_dump) {
|
||||
async_dump = false;
|
||||
Stats::StatEvent(true, false);
|
||||
}
|
||||
|
||||
if (async_dumpreset) {
|
||||
async_dumpreset = false;
|
||||
Stats::StatEvent(true, true);
|
||||
}
|
||||
|
||||
if (async_exit) {
|
||||
async_exit = false;
|
||||
exitSimLoop("user interrupt received");
|
||||
}
|
||||
|
||||
if (async_io || async_alarm) {
|
||||
async_io = false;
|
||||
async_alarm = false;
|
||||
pollQueue.service();
|
||||
}
|
||||
|
||||
if (async_exception) {
|
||||
async_exception = false;
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// not reached... only exit is return on SimLoopExitEvent
|
||||
}
|
||||
|
||||
Event *
|
||||
createCountedDrain()
|
||||
{
|
||||
return new CountedDrainEvent();
|
||||
}
|
||||
|
||||
void
|
||||
cleanupCountedDrain(Event *counted_drain)
|
||||
{
|
||||
CountedDrainEvent *event =
|
||||
dynamic_cast<CountedDrainEvent *>(counted_drain);
|
||||
if (event == NULL) {
|
||||
fatal("Called cleanupCountedDrain() on an event that was not "
|
||||
"a CountedDrainEvent.");
|
||||
}
|
||||
assert(event->getCount() == 0);
|
||||
delete event;
|
||||
}
|
||||
|
||||
void
|
||||
serializeAll(const std::string &cpt_dir)
|
||||
{
|
||||
Serializable::serializeAll(cpt_dir);
|
||||
}
|
||||
|
||||
void
|
||||
unserializeAll(const std::string &cpt_dir)
|
||||
{
|
||||
Serializable::unserializeAll(cpt_dir);
|
||||
}
|
||||
|
||||
/**
|
||||
* Queue of C++ callbacks to invoke on simulator exit.
|
||||
*/
|
||||
CallbackQueue&
|
||||
exitCallbacks()
|
||||
{
|
||||
static CallbackQueue theQueue;
|
||||
return theQueue;
|
||||
}
|
||||
|
||||
/**
|
||||
* Register an exit callback.
|
||||
*/
|
||||
void
|
||||
registerExitCallback(Callback *callback)
|
||||
{
|
||||
exitCallbacks().add(callback);
|
||||
}
|
||||
|
||||
BaseCPU *
|
||||
convertToBaseCPUPtr(SimObject *obj)
|
||||
{
|
||||
BaseCPU *ptr = dynamic_cast<BaseCPU *>(obj);
|
||||
|
||||
if (ptr == NULL)
|
||||
warn("Casting to BaseCPU pointer failed");
|
||||
return ptr;
|
||||
}
|
||||
|
||||
System *
|
||||
convertToSystemPtr(SimObject *obj)
|
||||
{
|
||||
System *ptr = dynamic_cast<System *>(obj);
|
||||
|
||||
if (ptr == NULL)
|
||||
warn("Casting to System pointer failed");
|
||||
return ptr;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Do C++ simulator exit processing. Exported to SWIG to be invoked
|
||||
* when simulator terminates via Python's atexit mechanism.
|
||||
*/
|
||||
void
|
||||
doExitCleanup()
|
||||
{
|
||||
exitCallbacks().process();
|
||||
exitCallbacks().clear();
|
||||
|
||||
cout.flush();
|
||||
|
||||
// print simulation stats
|
||||
Stats::dump();
|
||||
}
|
||||
|
|
121
src/sim/simulate.cc
Normal file
121
src/sim/simulate.cc
Normal file
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
* Steve Reinhardt
|
||||
*/
|
||||
|
||||
#include "base/misc.hh"
|
||||
#include "base/pollevent.hh"
|
||||
#include "sim/stat_control.hh"
|
||||
#include "sim/async.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "sim/host.hh"
|
||||
#include "sim/sim_events.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
#include "sim/simulate.hh"
|
||||
|
||||
/** Simulate for num_cycles additional cycles. If num_cycles is -1
|
||||
* (the default), do not limit simulation; some other event must
|
||||
* terminate the loop. Exported to Python via SWIG.
|
||||
* @return The SimLoopExitEvent that caused the loop to exit.
|
||||
*/
|
||||
SimLoopExitEvent *
|
||||
simulate(Tick num_cycles)
|
||||
{
|
||||
warn("Entering event queue @ %d. Starting simulation...\n", curTick);
|
||||
|
||||
if (num_cycles < 0)
|
||||
fatal("simulate: num_cycles must be >= 0 (was %d)\n", num_cycles);
|
||||
else if (curTick + num_cycles < 0) //Overflow
|
||||
num_cycles = MaxTick;
|
||||
else
|
||||
num_cycles = curTick + num_cycles;
|
||||
|
||||
Event *limit_event;
|
||||
limit_event = schedExitSimLoop("simulate() limit reached", num_cycles);
|
||||
|
||||
while (1) {
|
||||
// there should always be at least one event (the SimLoopExitEvent
|
||||
// we just scheduled) in the queue
|
||||
assert(!mainEventQueue.empty());
|
||||
assert(curTick <= mainEventQueue.nextTick() &&
|
||||
"event scheduled in the past");
|
||||
|
||||
// forward current cycle to the time of the first event on the
|
||||
// queue
|
||||
curTick = mainEventQueue.nextTick();
|
||||
Event *exit_event = mainEventQueue.serviceOne();
|
||||
if (exit_event != NULL) {
|
||||
// hit some kind of exit event; return to Python
|
||||
// event must be subclass of SimLoopExitEvent...
|
||||
SimLoopExitEvent *se_event;
|
||||
se_event = dynamic_cast<SimLoopExitEvent *>(exit_event);
|
||||
|
||||
if (se_event == NULL)
|
||||
panic("Bogus exit event class!");
|
||||
|
||||
// if we didn't hit limit_event, delete it
|
||||
if (se_event != limit_event) {
|
||||
assert(limit_event->scheduled());
|
||||
limit_event->deschedule();
|
||||
delete limit_event;
|
||||
}
|
||||
|
||||
return se_event;
|
||||
}
|
||||
|
||||
if (async_event) {
|
||||
async_event = false;
|
||||
if (async_statdump || async_statreset) {
|
||||
async_statdump = false;
|
||||
async_statreset = false;
|
||||
|
||||
Stats::StatEvent(async_statdump, async_statreset);
|
||||
}
|
||||
|
||||
if (async_exit) {
|
||||
async_exit = false;
|
||||
exitSimLoop("user interrupt received");
|
||||
}
|
||||
|
||||
if (async_io || async_alarm) {
|
||||
async_io = false;
|
||||
async_alarm = false;
|
||||
pollQueue.service();
|
||||
}
|
||||
|
||||
if (async_exception) {
|
||||
async_exception = false;
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// not reached... only exit is return on SimLoopExitEvent
|
||||
}
|
||||
|
35
src/sim/simulate.hh
Normal file
35
src/sim/simulate.hh
Normal file
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
* Steve Reinhardt
|
||||
*/
|
||||
|
||||
#include "sim/host.hh"
|
||||
#include "sim/sim_events.hh"
|
||||
|
||||
SimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
|
Loading…
Reference in a new issue