Update phase param in the .py file for the cpus

--HG-- extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
2006-11-14 01:13:26 -05:00 · 2006-11-14 01:13:26 -05:00 · ac309071af
parent 4135dd48ed
commit ac309071af
1 changed files with 1 additions and 0 deletions
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@ -47,6 +47,7 @@ class BaseCPU(SimObject):
        "defer registration with system (for sampling)")

    clock = Param.Clock(Parent.clock, "clock speed")
+    phase = Param.Latency("0ns", "clock phase")

    _mem_ports = []