diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 2f702a4bf..8037c90af 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -47,6 +47,7 @@ class BaseCPU(SimObject):
         "defer registration with system (for sampling)")
 
     clock = Param.Clock(Parent.clock, "clock speed")
+    phase = Param.Latency("0ns", "clock phase")
 
     _mem_ports = []