gem5/src/python/m5
Steve Reinhardt 0305159abf PhysicalMemory has vector of uniform ports instead of one special one.
configs/example/memtest.py:
    PhysicalMemory has vector of uniform ports instead of one special one.
    Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
    Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
    Add comment.

--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
2007-05-19 00:24:34 -04:00
..
internal Completely re-work how the scons framework incorporates swig 2007-04-12 21:20:04 -07:00
objects PhysicalMemory has vector of uniform ports instead of one special one. 2007-05-19 00:24:34 -04:00
__init__.py Cleanup 2007-03-06 22:16:18 -08:00
attrdict.py Migrate most of main() and and all option parsing to python 2006-07-10 23:00:13 -04:00
convert.py Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
event.py Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
main.py Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
multidict.py Enable proxies (Self/Parent) for specifying ports. 2006-09-05 22:04:34 -07:00
params.py Float should have a c++ param type 2007-05-11 11:48:58 -07:00
proxy.py Fixes for Port proxies and proxy parameters. 2006-10-08 18:26:59 -07:00
SimObject.py Factor code out of main.cc and main.i into a bunch of files 2007-03-02 22:24:00 -08:00
smartdict.py Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
stats.py Do the default argument stuff in python 2007-03-03 07:45:55 -08:00
ticks.py Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
util.py Split config.py into multiple files. 2006-09-04 10:52:26 -07:00