Create a stub t1000 platform.
--HG-- extra : convert_revision : 7e27b23b66c743b4625a1dd9d8d6ba61bff45168
This commit is contained in:
Gabe Black
parent
20730b790c
commit
bc4d15ddd1
4 changed files with 309 additions and 0 deletions
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@ -37,6 +37,7 @@ Import('env')
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sources = []
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sources += Split('''
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t1000.cc
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''')
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# Convert file names to SCons File objects. This takes care of the
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124
src/dev/sparc/t1000.cc
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124
src/dev/sparc/t1000.cc
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@ -0,0 +1,124 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/** @file
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* Implementation of T1000 platform.
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "cpu/intr_control.hh"
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#include "dev/simconsole.hh"
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#include "dev/sparc/t1000.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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//Should this be AlphaISA?
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using namespace TheISA;
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T1000::T1000(const string &name, System *s, IntrControl *ic)
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: Platform(name, ic), system(s)
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{
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// set the back pointer from the system to myself
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system->platform = this;
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}
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Tick
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T1000::intrFrequency()
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{
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return (Tick)0;
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}
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void
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T1000::postConsoleInt()
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{
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}
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void
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T1000::clearConsoleInt()
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{
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}
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void
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T1000::postPciInt(int line)
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{
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}
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void
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T1000::clearPciInt(int line)
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{
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}
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Addr
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T1000::pciToDma(Addr pciAddr) const
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{
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return (Addr)0;
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}
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Addr
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T1000::calcConfigAddr(int bus, int dev, int func)
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{
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return (Addr)0;
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}
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void
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T1000::serialize(std::ostream &os)
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{
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}
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void
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T1000::unserialize(Checkpoint *cp, const std::string §ion)
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{
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000)
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SimObjectParam<System *> system;
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SimObjectParam<IntrControl *> intrctrl;
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END_DECLARE_SIM_OBJECT_PARAMS(T1000)
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BEGIN_INIT_SIM_OBJECT_PARAMS(T1000)
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INIT_PARAM(system, "system"),
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INIT_PARAM(intrctrl, "interrupt controller")
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END_INIT_SIM_OBJECT_PARAMS(T1000)
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CREATE_SIM_OBJECT(T1000)
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{
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return new T1000(getInstanceName(), system, intrctrl);
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}
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REGISTER_SIM_OBJECT("T1000", T1000)
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108
src/dev/sparc/t1000.hh
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108
src/dev/sparc/t1000.hh
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@ -0,0 +1,108 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/**
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* @file
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* Declaration of top level class for the Tsunami chipset. This class just
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* retains pointers to all its children so the children can communicate.
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*/
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#ifndef __DEV_T1000_HH__
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#define __DEV_T1000_HH__
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#include "dev/platform.hh"
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class IdeController;
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class System;
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class T1000 : public Platform
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{
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public:
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/** Pointer to the system */
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System *system;
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public:
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/**
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* Constructor for the Tsunami Class.
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* @param name name of the object
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* @param s system the object belongs to
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* @param intctrl pointer to the interrupt controller
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*/
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T1000(const std::string &name, System *s, IntrControl *intctrl);
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/**
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* Return the interrupting frequency to AlphaAccess
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* @return frequency of RTC interrupts
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*/
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virtual Tick intrFrequency();
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/**
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* Cause the cpu to post a serial interrupt to the CPU.
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*/
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virtual void postConsoleInt();
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/**
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* Clear a posted CPU interrupt (id=55)
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*/
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virtual void clearConsoleInt();
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/**
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* Cause the chipset to post a cpi interrupt to the CPU.
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*/
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virtual void postPciInt(int line);
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/**
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* Clear a posted PCI->CPU interrupt
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*/
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virtual void clearPciInt(int line);
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virtual Addr pciToDma(Addr pciAddr) const;
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/**
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* Calculate the configuration address given a bus/dev/func.
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*/
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virtual Addr calcConfigAddr(int bus, int dev, int func);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __DEV_T1000_HH__
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76
src/python/m5/objects/T1000.py
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76
src/python/m5/objects/T1000.py
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@ -0,0 +1,76 @@
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from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice
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from Platform import Platform
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from AlphaConsole import AlphaConsole
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from Uart import Uart8250
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from Pci import PciConfigAll
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from BadDevice import BadDevice
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class IsaFake(BasicPioDevice):
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type = 'IsaFake'
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pio_size = Param.Addr(0x8, "Size of address range")
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ret_data = Param.UInt8(0xFF, "Default data to return")
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ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
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class BadAddr(IsaFake):
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ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
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class T1000(Platform):
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type = 'T1000'
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system = Param.System(Parent.any, "system")
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fake_iob = IsaFake(pio_addr=0x8000000000, pio_size=0x7F00000000)
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fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
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fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
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fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
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fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
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fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
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fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
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fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
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fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
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fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
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fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
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fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
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fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
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fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
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fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
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fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
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fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
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fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
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fake_ata1 = IsaFake(pio_addr=0x801fc000170)
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fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
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uart = Uart8250(pio_addr=0x801fc0003f8)
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.fake_iob.pio = bus.port
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self.fake_uart1.pio = bus.port
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self.fake_uart2.pio = bus.port
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self.fake_uart3.pio = bus.port
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self.fake_uart4.pio = bus.port
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self.fake_ppc.pio = bus.port
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self.fake_OROM.pio = bus.port
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self.fake_pnp_addr.pio = bus.port
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self.fake_pnp_write.pio = bus.port
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self.fake_pnp_read0.pio = bus.port
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self.fake_pnp_read1.pio = bus.port
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self.fake_pnp_read2.pio = bus.port
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self.fake_pnp_read3.pio = bus.port
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self.fake_pnp_read4.pio = bus.port
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self.fake_pnp_read5.pio = bus.port
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self.fake_pnp_read6.pio = bus.port
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self.fake_pnp_read7.pio = bus.port
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self.fake_ata0.pio = bus.port
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self.fake_ata1.pio = bus.port
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self.fb.pio = bus.port
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self.io.pio = bus.port
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self.uart.pio = bus.port
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