Ali Saidi
a17dbdf883
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 17:19:50 +00:00
Ali Saidi
ae62d97158
MIPS: Fix regressions tests
2011-09-17 12:34:03 -04:00
Ali Saidi
28a2236ec1
O3: Update stats for new ordering fix.
2011-09-13 12:58:09 -04:00
Gabe Black
c5fd6f4fec
MIPS: Update MIPS stats for cleaned up operand checks.
2011-09-09 01:35:05 -07:00
Ali Saidi
f125ef22b9
O3: Update stats for LSQ changes.
2011-08-19 15:08:06 -05:00
Ali Saidi
3ebfe2eb01
O3: Update stats for fetch and bp changes.
2011-07-10 12:56:09 -05:00
Korey Sewell
b5736ba4ef
alpha:o3:simple: update simout/err files
...
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning
Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
2011-06-20 18:57:14 -04:00
Nathan Binkert
a7e27f9a82
tests: updates for stat name change
2011-04-22 10:18:51 -07:00
Nathan Binkert
8c1563096c
tests: update stats for name changes
2011-04-19 18:45:23 -07:00
Ali Saidi
1114be4b78
O3: Update stats for memory order violation checking patch.
2011-04-04 11:42:25 -05:00
Gabe Black
0851580aad
Stats: Re update stats.
2011-02-07 19:23:13 -08:00
Gabe Black
1b64bfa933
Stats: Back out broken update.
2011-02-07 19:23:11 -08:00
Brad Beckmann
45f881919f
regress: Regression Tester output updates
2011-02-06 22:14:23 -08:00
Ali Saidi
9b67f3723e
Stats: Update stats for previous set of patches.
2011-01-18 16:30:06 -06:00
Ali Saidi
371110fb0a
Regressions: Update regressions for SIMD opclass changes
2010-11-15 14:04:05 -06:00
Gabe Black
b53231e7fe
Ref output: Update refs for PCState change.
2010-10-31 00:07:48 -07:00
Steve Reinhardt
9e45ada171
stats: update stats for preceding coherence changes
...
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00
m5test
744b59d6de
tests: Update O3 ref outputs to reflect Lisa's dist format change.
2010-06-06 18:39:10 -04:00
Ali Saidi
e63c73b45d
BPRED: Update regressions for tournament predictor fix.
2010-05-13 23:45:59 -04:00
Lisa Hsu
ee20a7c0bd
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 10:08:41 -08:00
Gabe Black
4f4e6fc099
MIPS: Update the stats of the RUBY version of the regressions.
2010-01-02 07:06:26 -05:00
Gabe Black
47a1f11381
MIPS: Update stats for updated initial environment.
2009-12-31 15:30:51 -05:00
Korey Sewell
eb1bd7a2e6
mips-stats: update regressions of arguments fix
2009-09-24 12:30:53 -04:00
Nathan Binkert
e3e509b31a
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-06 15:49:48 -07:00
Nathan Binkert
567cab6859
stats: update reference outputs now that compatibility is gone
...
Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 10:25:17 -07:00
Steve Reinhardt
7b40c36fbd
Update stats for new single bad-address responder.
...
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
2009-04-22 01:55:52 -04:00
Korey Sewell
a25aa00522
o3-mips-regress: add hello word regression.
2009-04-18 10:42:29 -04:00
