419 lines
47 KiB
Text
419 lines
47 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 48407 # Simulator instruction rate (inst/s)
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host_mem_usage 206048 # Number of bytes of host memory used
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host_seconds 0.11 # Real time elapsed on the host
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host_tick_rate 131379529 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5169 # Number of instructions simulated
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sim_seconds 0.000014 # Number of seconds simulated
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sim_ticks 14060500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 572 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 1960 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 751 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 1593 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 2416 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 404 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 916 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 65 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 14561 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.400110 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.121131 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0-1 11999 82.41% 82.41% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1-2 1213 8.33% 90.74% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2-3 529 3.63% 94.37% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3-4 291 2.00% 96.37% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4-5 294 2.02% 98.39% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5-6 71 0.49% 98.87% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.30% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7-8 37 0.25% 99.55% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 65 0.45% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 14561 # Number of insts commited each cycle
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system.cpu.commit.COM:count 5826 # Number of instructions committed
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system.cpu.commit.COM:loads 1164 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 2089 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 620 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 6017 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 5169 # Number of Instructions Simulated
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system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
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system.cpu.cpi 5.440511 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 5.440511 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 2321 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 34074.626866 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36043.956044 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 2187 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4566000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.057734 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 3280000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.039207 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 27570.707071 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36046.875000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 628 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 8188500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.321081 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 297 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 233 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2307000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 20.226950 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 3246 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 29592.807425 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2815 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 12754500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.132779 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 431 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 276 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 5587000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.047751 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 3246 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 29592.807425 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 2815 # number of overall hits
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system.cpu.dcache.overall_miss_latency 12754500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.132779 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 431 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 276 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 5587000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.047751 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 91.308954 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2852 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 519 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 139 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 139 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 14436 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 10077 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 3965 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1080 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.fetch.Branches 2416 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 2220 # Number of cache lines fetched
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system.cpu.fetch.Cycles 6371 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 355 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 15622 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 767 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.085911 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 2220 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.555508 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 15641 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 0.998785 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.252974 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0-1 11507 73.57% 73.57% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1-2 1847 11.81% 85.38% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2-3 223 1.43% 86.80% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3-4 141 0.90% 87.71% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4-5 312 1.99% 89.70% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5-6 120 0.77% 90.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6-7 308 1.97% 92.44% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7-8 254 1.62% 94.06% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 929 5.94% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 15641 # Number of instructions fetched each cycle (Total)
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system.cpu.icache.ReadReq_accesses 2220 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 35681.279621 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 34902.735562 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1798 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 15057500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.190090 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 422 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 93 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 11483000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.148198 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 5.465046 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 2220 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 35681.279621 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1798 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 15057500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.190090 # miss rate for demand accesses
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system.cpu.icache.demand_misses 422 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 93 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 11483000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.148198 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 2220 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 35681.279621 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1798 # number of overall hits
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system.cpu.icache.overall_miss_latency 15057500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.190090 # miss rate for overall accesses
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system.cpu.icache.overall_misses 422 # number of overall misses
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system.cpu.icache.overall_mshr_hits 93 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 11483000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.148198 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 16 # number of replacements
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system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 156.015053 # Cycle average of tags in use
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system.cpu.icache.total_refs 1798 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 12481 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 1253 # Number of branches executed
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system.cpu.iew.EXEC:nop 1830 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.295249 # Inst execution rate
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system.cpu.iew.EXEC:refs 3456 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 1049 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 4132 # num instructions consuming a value
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system.cpu.iew.WB:count 7536 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.703291 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 2906 # num instructions producing a value
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system.cpu.iew.WB:rate 0.267975 # insts written-back per cycle
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system.cpu.iew.WB:sent 7618 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 681 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 2806 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 963 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 11847 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 2407 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 549 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 8303 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 1080 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations
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system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread.0.squashedLoads 1642 # Number of loads squashed
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system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed
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system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 272 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 409 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.183806 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.183806 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 5184 58.56% 58.56% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.62% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.64% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.66% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.66% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.66% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.66% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.66% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.66% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 2595 29.32% 87.98% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.02% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 8852 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.018301 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 8 4.94% 4.94% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.94% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.94% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.94% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.94% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.94% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.94% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.94% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 100 61.73% 66.67% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 15641 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.565948 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.209939 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 11653 74.50% 74.50% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 1757 11.23% 85.74% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 814 5.20% 90.94% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 738 4.72% 95.66% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 342 2.19% 97.85% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 199 1.27% 99.12% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.58% 99.70% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.20% 99.90% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 15641 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 0.314771 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 10005 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 8852 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 4214 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 36 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 2725 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34680 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31360 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_miss_latency 1734000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1568000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.221154 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12953500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34428.571429 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31178.571429 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 482000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436500 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.009950 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34356.223176 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 16010000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 14521500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.991489 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 466 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 16010000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 466 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 14521500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.991489 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 466 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 402 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 210.151573 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 2806 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.numCycles 28122 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 5 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IdleCycles 10468 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 9 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 15900 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 13681 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 8420 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 3575 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1080 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 19 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 5010 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 111 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|