Commit graph

75 commits

Author SHA1 Message Date
Ali Saidi
81a735a716 fs now gets to the point where it would really like a filesystem.
Time to make the ide device work

arch/alpha/system.cc:
    write the machine type and rev in the correct place
cpu/simple/cpu.cc:
    reset the packet structure every time it's reused... wow the
    simple cpu code  for talking to memory is getting horrible.
dev/alpha_console.cc:
    move the setAlphaAccess to startup() to make sure that the console
    binary is loaded
dev/tsunami_cchip.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
    fix a couple of bugs injected in the newmem fixes
mem/bus.cc:
    More verbose bus tracing
mem/packet.hh:
    Add a constructor to packet to set the result to unknown and a reset
    method in the case it's being reused
mem/vport.hh:
    don't need are own read/write methods since the base functional port
    ones call writeBlob readBlob which do the translation for us

--HG--
extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
2006-04-12 17:46:25 -04:00
Ali Saidi
08d9e0ea7a change how much of the param string is copied into the kenel
Set locked flag if required
make SC always return success -- this needs to be fixed at some point
fix a couple of things

FS executes a bit of console code before dying a horrible death

arch/alpha/linux/system.cc:
    only need to copy the length of the os flags param, not 256  bytes
cpu/simple/cpu.cc:
    Set the physical flag if required
    Make LL/SC always return success
mem/bus.cc:
    add some dprintfs and change a assert to a panic
mem/port.cc:
    delete the buffer with the [] operator
mem/request.hh:
    add a function to reset a request

--HG--
extra : convert_revision : f2b78ddad33c7f6ffe1c48791d86609ff1d10d46
2006-04-11 19:35:30 -04:00
Ali Saidi
f6fc18f03d fullsys now builds and runs for about one cycle
SConscript:
    easier to fix than temporarily remove
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    mem needed for both fullsys and syscall
dev/baddev.cc:
    fix for new mem system
dev/io_device.cc:
    fix typo
dev/io_device.hh:
    PioDevice needs to be a memobject
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
    fix for new mem systems
dev/platform.cc:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
    rather than the platform have a pointer to pciconfig, go the other
    way so all devices are the same and can have a platform pointer
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart8250.cc:
python/m5/objects/AlphaConsole.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/Device.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/System.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    fixes for newmem

--HG--
extra : convert_revision : b7b67e19095cca64889f6307725aa2f3d84c7105
2006-04-11 13:42:47 -04:00
Ron Dreslinski
9e3d79694c Move to a model with a unified request object.
Constructor takes a bool to signify that it is either a cpu_request or not a cpu_request.
When accedding variables of a cpu_request it asserts that it is a cpu_request.
It also asserts that a value being read has been written at some point in time prior (not gaurnteeing it is up to date, but it was at least written before read).

There is also a isCpuReq() function to determine if this is a cpu_request.  It should be called before accesing a cpu_request only variable.

SConscript:
    Add compilation support for request.cc
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/io_device.cc:
mem/page_table.cc:
mem/page_table.hh:
mem/port.cc:
    Update for unified request object and accessor functions.
mem/request.hh:
    Remove CpuRequest, make it a unified object.  Make variables private with accessor functions.

    May want to move things from .cc file into header (usually a assert() and either returning a value, or writting two).

--HG--
extra : convert_revision : f1e45cc490dadc7a418634539b03c3e72684a6e3
2006-04-07 15:54:48 -04:00
Gabe Black
adeb458b87 Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 08ae5e999d9b313e3e40cb6d58863905b70ca781
2006-03-31 20:32:18 -05:00
Gabe Black
5c79eb0410 Fixes to SPARC for syscall emulation mode.
arch/sparc/isa/base.isa:
arch/sparc/isa/decoder.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/formats/branch.isa:
arch/sparc/isa/formats/integerop.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/nop.isa:
arch/sparc/isa/formats/trap.isa:
arch/sparc/isa/formats/unknown.isa:
arch/sparc/isa/includes.isa:
arch/sparc/isa/operands.isa:
    Fixes towards running in syscall emulation mode.
arch/sparc/linux/process.cc:
    Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway?
base/loader/elf_object.cc:
    Cleared out comments about resolved issues.
cpu/simple/cpu.cc:
    Use NNPC for both SPARC and MIPS, instead of just MIPS
configs/test/hello_sparc:
    A test program for SPARC which prints "Hello World!"

--HG--
rename : arch/sparc/isa/formats/noop.isa => arch/sparc/isa/formats/nop.isa
extra : convert_revision : 10b3e3b9f21c215d809cffa930448007102ba698
2006-03-31 20:31:53 -05:00
Ali Saidi
5936c79ba0 Add a functional port that is used to load the original binaries in FS
SE mode now has a port that goes to whatever toplevel mem object the
CPU sees that does the appropriate translation for syscall emulation

SConscript:
    translating port is a syscall emu only source
arch/alpha/system.cc:
base/loader/object_file.cc:
base/loader/object_file.hh:
    Use the new functional port to write the binaries into memory
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/simple/cpu.cc:
    We aren't always going to be writing straight to memory with syscalls
    support writing to a cache
mem/port.hh:
    Add a simple unidirectional functional port that panics on any incoming requests
mem/translating_port.hh:
    make translating port inherit from the simple port
sim/system.cc:
sim/system.hh:
    Add a functional port that is used to load the original binaries

--HG--
extra : convert_revision : 9096866d0b23e3aceea68394abb76e63c0f8fd8d
2006-03-30 18:06:00 -05:00
Ali Saidi
e196d20d9d Make TranslatingPort be a type of Port rather than something special
arch/alpha/arguments.cc:
    rather than returning 0, put a panic in... it will actually make us fix
    this rather than scratching our respective heads
base/loader/object_file.cc:
base/loader/object_file.hh:
    Object loader now takes a port rather than a translating port
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
sim/process.cc:
    Make translating port a type of port rather than anything special
cpu/simple/cpu.cc:
    no need to grab a port from the cpu anymore
mem/physical.cc:
    add an additional type of port to physicalmemory called "functional"
    Only used for functional accesses (loading binaries/syscall emu)
mem/port.hh:
    make readBlok/writeBlob virtual so translating port can do the
    translation first
mem/translating_port.cc:
mem/translating_port.hh:
    Make TranslatingPort inherit from Port
sim/system.cc:
    header file that doesn't exit removed

--HG--
extra : convert_revision : 89b08f6146bba61f5605678d736055feab2fe6f7
2006-03-30 15:59:49 -05:00
Kevin Lim
0b2deb2a88 Fixes for full system compiling.
arch/alpha/arguments.cc:
    There will not be a phys mem ptr in the XC in the newmem.  This read will have to go through something else.
arch/alpha/ev5.cc:
    Remove instantiations of these functions for the FastCPU, as the FastCPU is not really used.  Also this messed up the ability to specify which CPU models are being built.
cpu/exec_context.hh:
    Remove getPhysMemPtr() function.
cpu/exetrace.cc:
    Include sim/system.hh, and sort the includes.
cpu/simple/cpu.cc:
    Fixes for full system compilation.
kern/system_events.cc:
    Remove include of encumbered FullCPU.  The branch prediction will need to be fixed up in a more generic way in the future.

--HG--
extra : convert_revision : a8bbf562a277aa80e8f40112570c0a825298a05c
2006-03-30 10:42:55 -05:00
Ali Saidi
c27c122afc Add the bus and connector objects to scons
change getPort parameter from char* to string
Add an extra phase between construction and init called connect

SConscript:
    Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    the connection to memory shouldn't be made until we know the memory
    object exists (e.g. after construction)
dev/io_device.hh:
    change to const string
mem/bus.hh:
    change getPort parameter from char* to string
    initialize num_interfaces
mem/mem_object.hh:
    change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
    change getPort parameter from char* to string
    get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
    get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
    Add an extra phase between construction and init called connect

--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
2006-03-26 21:44:22 -05:00
Korey Sewell
c32b4ecac1 infinitesimal small baby steps toward MIPS actually working
arch/mips/isa/formats/branch.isa:
    let user know that we alter r31 in disassembly
arch/mips/isa_traits.cc:
    add copyRegs function ...
    comment out serialize float code for now
arch/mips/isa_traits.hh:
    make FloatRegFile a class ... change values of architectural regs
arch/mips/process.cc:
    change MIPS to Mips
base/loader/elf_object.cc:
    get global pointer initialized to a value
base/loader/elf_object.hh:
    Add global_ptr to elf_object constructor
base/loader/object_file.hh:
    MIPS to Mips
base/traceflags.py:
    SimpleCPU trace flag
cpu/simple/cpu.cc:
    DPRINTF flags for SimpleCPU
cpu/static_inst.hh:
    Add Decoder functions to static_inst.hh

--HG--
extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
2006-03-15 16:26:40 -05:00
Korey Sewell
0d8cfed042 Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem

--HG--
extra : convert_revision : 054833d2f7019b9a1247efc4451ccb143242059d
2006-03-14 18:30:09 -05:00
Korey Sewell
6547e8882b Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu
SConscript:
    Separate Alpha EIO from syscall building for other architectures
arch/isa_specific.hh:
    change MIPS constant to 34k
arch/mips/isa/decoder.isa:
    Allow sll,ssnop,nop, and ehb to be determined through decoder using
    the different types of default cases
arch/mips/isa/formats/branch.isa:
    Delete debug code
arch/mips/isa/formats/noop.isa:
    add a Nop format
arch/mips/isa_traits.hh:
    use constants instead of enums
arch/mips/process.cc:
    point to the correct header file
cpu/simple/cpu.cc:
    Output the actual fault name
sim/process.cc:
    Inititalize NNPC

--HG--
extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
2006-03-14 18:28:51 -05:00
Gabe Black
fa763d2ecf Merge m5.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

cpu/cpu_exec_context.cc:
    Hand merge

--HG--
rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh
extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
2006-03-14 16:08:32 -05:00
Gabe Black
8e4ec55703 Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.
arch/alpha/arguments.cc:
    Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
    Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
    Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
    Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
    Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
    Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
    Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
    Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
    Replaced setFloatRegDouble with setFloatReg

--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
2006-03-14 15:55:00 -05:00
Steve Reinhardt
e2b329d574 Replace Memory with MemObject; no need for two different levels of hierarchy there.
Get rid of addPort().
Change getPort() behavior on PhysicalMemory.

SConscript:
cpu/simple/cpu.hh:
sim/system.cc:
sim/system.hh:
    Replace Memory with MemObject.
cpu/base.hh:
    No need to declare Port here anymore.
cpu/cpu_exec_context.hh:
    Need PageTable definition.
cpu/simple/cpu.cc:
mem/physical.cc:
mem/physical.hh:
    Replace Memory with MemObject.
    Get rid of addPort(); allow getting anonymous ports with getPort().
mem/translating_port.hh:
    Remove unneeded header.
sim/process.cc:
    Replace Memory with MemObject.
    Change how initialization port gets set up to deal with change in
    addPort()/getPort().  Current solution is not ideal but it works.
sim/process.hh:
    Remove unneeded headers and declarations.
    Make LiveProcess::getDesc() abstract instead of panicing if called.
sim/syscall_emul.hh:
    Fix includes.

--HG--
extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f
2006-03-12 17:21:59 -05:00
Steve Reinhardt
71c2c962db Clean up "using" declarations.
arch/alpha/isa_traits.hh:
    No unprotected "using" in header files.
cpu/simple/cpu.cc:
    Fix ISA namespace "using" statement.

--HG--
extra : convert_revision : 317ea40f8de00748d7613a0116edab05770bdc72
2006-03-12 15:14:07 -05:00
Korey Sewell
57d53f8a9d Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem

--HG--
extra : convert_revision : b101fa550567d5a9f5de6c2d8c3f67829ae050c1
2006-03-12 05:58:28 -05:00
Korey Sewell
4d19bbeeeb MIPS is back to compiling and building now!
arch/alpha/isa_traits.hh:
    used for SimpleCPU instead of explicitly calling the namespace we declare in isa_traits.hhs
    so other archs. can use SimpleCPU
arch/mips/SConscript:
    dont include common_syscall or tru64
arch/mips/faults.cc:
arch/mips/faults.hh:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
    Change Faults to new format
arch/mips/isa/decoder.isa:
    Fix readMiscReg access
    Made change so that you cant explicitly tell if a instruction nop,ehb,or ssnop... These are all variants
    of the sll instruction so I may need to make a separte class of instructions to handle thse better
arch/mips/isa/includes.isa:
    add isa_traits.hh and MipsISA included into every auto-gen file
arch/mips/isa_traits.cc:
    create copyMiscRegs function...
    delete useless code
arch/mips/isa_traits.hh:
    clean up for build
arch/mips/linux_process.cc:
    mem is now getMemPort(), linux process objects now take in a system argument
arch/mips/linux_process.hh:
    new argument for linux process
arch/mips/process.cc:
    add system
arch/mips/process.hh:
    add system variable
cpu/cpu_exec_context.cc:
    Change AlphaISA to TheISA
cpu/exec_context.hh:
    add readNextNPC and setNextNPC functions
cpu/simple/cpu.cc:
    include isa_traits for namespace declariation
cpu/simple/cpu.hh:
    PC & NPC access/modify functions
arch/mips/utility.hh:
    file needed for compile

--HG--
extra : convert_revision : 29a327e79c51c6174a6e526aa68c7aab7e7eb535
2006-03-12 05:57:34 -05:00
Steve Reinhardt
1f5266e79d Minor fix to fault message in SimpleCPU.
cpu/simple/cpu.cc:
    Fix up fault message... 0x prefix is redundant when using %p.

--HG--
extra : convert_revision : 329d4417287a036a0f24544f73f48c0e19059425
2006-03-12 00:34:02 -05:00
Gabe Black
3ed62ad025 Work towards factoring isa_traits.hh into smaller, more specialized files.
arch/SConscript:
    Sorted the switch headers, and added registerfile.hh, constants.hh, types.hh, and utility.hh.
arch/alpha/isa_traits.hh:
    Moved the register file types to registerfile.hh, small functions to utility.hh, and cleaned out alot of stuff that isn't necessary anymore.
base/loader/ecoff_object.cc:
base/loader/elf_object.cc:
cpu/pc_event.hh:
cpu/static_inst.hh:
mem/port.hh:
sim/faults.cc:
sim/system.hh:
    base/misc.hh isn't included through isa_traits.hh anymore.
cpu/simple/cpu.cc:
    Added include for arch/utility.hh

--HG--
extra : convert_revision : 24f65f330f87e3c909c939596cfcf48336022eaf
2006-03-10 19:11:27 -05:00
Gabe Black
68d7382cf3 Eliminated TARGET_ALPHA, since THE_ISA provides the same function.
--HG--
extra : convert_revision : eb173a553b0782891e8b4a8e227bfb647390883a
2006-03-10 16:26:31 -05:00
Gabe Black
f102365bfe SimpleCPU compiles with merge.
arch/alpha/isa_traits.hh:
arch/alpha/linux/process.cc:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
base/chunk_generator.hh:
base/loader/elf_object.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
kern/linux/linux.hh:
kern/tru64/tru64.hh:
mem/packet.hh:
mem/page_table.cc:
mem/page_table.hh:
mem/physical.cc:
mem/request.hh:
mem/translating_port.cc:
sim/process.hh:
sim/system.cc:
    Fixing merged changes.

--HG--
extra : convert_revision : 2e94f21009395db654880fcb94ec806b6f5772c3
2006-03-09 19:21:35 -05:00
Gabe Black
872bbdfc33 Hand merge. Stuff probably doesn't compile.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
2006-03-09 18:35:28 -05:00
Gabe Black
91545ac2bf Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

cpu/simple/cpu.cc:
    Hand Merge

--HG--
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : bf664b092f993d0f4675ce8e7df13645a920c1f4
2006-03-09 15:15:55 -05:00
Kevin Lim
e30bce8f8e Use functions to access XC.
cpu/exec_context.hh:
    Include readNextNPC function.
cpu/simple/cpu.cc:
    Use functions to set and access nextPC, nextNPC.

--HG--
extra : convert_revision : 22622b9c110e1d99cc9106a2a27c479579d7e1ad
2006-03-09 15:10:55 -05:00
Korey Sewell
a3aae21d03 last changes before big merge
arch/alpha/isa_traits.hh:
arch/sparc/isa_traits.hh:
    add nnpc for compiling purposes in exec_context setNextNPC function
cpu/exec_context.hh:
    set NNPC function
cpu/simple/cpu.cc:
    use NNPC in determining what PC we are using

--HG--
extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
2006-03-09 03:27:51 -05:00
Kevin Lim
11aead894d Updates for the quiesceEvent that was added to the XC.
Also several files need to include system.hh or symtab.hh.  This is because exec_context.hh has less #includes than before, requiring some of the files that include it to include some other files as well.

arch/alpha/faults.cc:
    Avoid accessing XC directly.
arch/alpha/stacktrace.cc:
    StackTrace needs to include system.hh.
cpu/cpu_exec_context.cc:
    Update for change to CPUExecContext.
cpu/cpu_exec_context.hh:
    Make quiesce events use CPUExecContext instead of ExecContext.  Include functions to allow the quiesce event and last activate/suspend be accessed.
cpu/exec_context.hh:
    Include functions for quiesceEvent.
cpu/intr_control.cc:
    Needs to include cpu/exec_context.hh.
cpu/profile.cc:
    Needs to include symtab.hh for the symbol table.
cpu/profile.hh:
    Needs forward declare of ExecContext.
cpu/simple/cpu.cc:
    Rename xc to cpuXC.
dev/tsunami_cchip.cc:
    Needs to include exec_context.hh.
kern/kernel_stats.cc:
    Needs to include system.hh.
kern/linux/events.cc:
    Needs to include system.hh.

    Also avoid accessing objects directly from the XC.
kern/tru64/dump_mbuf.cc:
    Include symtab.hh for the SymbolTable and system.hh.
kern/tru64/tru64_events.cc:
    Include system.hh
sim/pseudo_inst.cc:
    Avoid accessing objects directly within the XC.

--HG--
extra : convert_revision : 78fe30d98cd20f7403fa216f772071458b675c84
2006-03-07 19:59:12 -05:00
Kevin Lim
20eced3ea0 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc

Further changes still need to be made to the XC code.

arch/alpha/ev5.cc:
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
base/remote_gdb.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
kern/kernel_stats.cc:
sim/pseudo_inst.cc:
    Hand merge.

--HG--
rename : kern/freebsd/freebsd_system.cc => arch/alpha/freebsd/system.cc
rename : kern/linux/linux_system.cc => arch/alpha/linux/system.cc
rename : kern/linux/linux_threadinfo.hh => arch/alpha/linux/threadinfo.hh
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : c1fe71fdd87d1fcd376f4feec69fc3fa29152e3e
2006-03-05 00:34:54 -05:00
Kevin Lim
f15e492375 Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.
The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext).

Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC).  The CPU uses the CPUExecContext, or however else it stores its own state.  It then creates a ProxyExecContext, templated on the class used to hold its state.  This proxy is passed to any code outside of the CPU that needs to access the XC.  This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out.

Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers.

SConscript:
    Include new file, cpu_exec_context.cc.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
arch/alpha/isa/decoder.isa:
arch/alpha/stacktrace.cc:
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
cpu/intr_control.cc:
    Avoid directly accessing objects within the XC.
arch/alpha/ev5.cc:
    Avoid directly accessing objects within the XC.

    KernelStats have been moved to the BaseCPU instead of the XC.
arch/alpha/isa_traits.hh:
    Remove clearIprs().  It wasn't used very often and it did not work well with the proxy ExecContext.
cpu/base.cc:
    Place kernel stats within the BaseCPU instead of the ExecContext.

    For now comment out the profiling code sampling until its exact location is decided upon.
cpu/base.hh:
    Kernel stats are now in the BaseCPU instead of the ExecContext.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
    Changes to support rename of old ExecContext to CPUExecContext.  See changeset for more details.
cpu/exetrace.cc:
    Remove unneeded include of exec_context.hh.
cpu/intr_control.hh:
cpu/o3/alpha_cpu_builder.cc:
    Remove unneeded include of exec_context.hh
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Changes to support rename of old ExecContext to CPUExecContext.  See changeset for more details.

    Also avoid accessing anything directly from the XC.
cpu/pc_event.cc:
    Avoid accessing objects directly from the XC.
dev/tsunami_cchip.cc:
    Avoid accessing objects directly within the XC>
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/linux/linux_threadinfo.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Avoid accessing objects directly within the XC.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
    Kernel stats no longer exist within the XC.
kern/system_events.cc:
    Avoid accessing objects directly within the XC.  Also kernel stats are now in the BaseCPU.
sim/process.cc:
sim/process.hh:
    Avoid accessing regs directly within an ExecContext.  Instead use a CPUExecContext to initialize the registers and copy them over.
cpu/cpu_exec_context.cc:
    Rename old ExecContext to CPUExecContext.  This is used by the old CPU models to store any necessary architectural state.  Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.
cpu/cpu_exec_context.hh:
    Rename old ExecContext to CPUExecContext.  This is used by the old CPU models to store any necessary architectural state.  Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.

    Remove kernel stats from the ExecContext.
sim/pseudo_inst.cc:
    Kernel stats now live within the CPU.

    Avoid accessing objects directly within the XC.

--HG--
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85
2006-03-04 15:18:40 -05:00
Kevin Lim
5790e295a9 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs

arch/alpha/ev5.cc:
    Remove intr_post, it is no longer used.
arch/alpha/isa_traits.hh:
    Hand merge.

--HG--
extra : convert_revision : 94f14539a9e5646f8c368b15b2dff18ab2f492cf
2006-03-04 13:06:24 -05:00
Kevin Lim
fc664f7ca6 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs

--HG--
extra : convert_revision : 979ab1fc4e1ea4d6a78ac9a2ec894f0be4feb01d
2006-03-03 16:04:34 -05:00
Kevin Lim
e7825aab59 Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.
The shadow registers are folded into the normal integer registers to ease renaming indexing.

Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode.

arch/alpha/ev5.cc:
    Changes to automatically map the shadow registers if the instruction is in PAL mode.
arch/alpha/isa/branch.isa:
arch/alpha/isa/decoder.isa:
arch/alpha/isa/fp.isa:
arch/alpha/isa/int.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
arch/alpha/isa/unimp.isa:
    Changes for automatically using the shadow registers.  Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
arch/alpha/isa/main.isa:
    Changes for automatically using the shadow registers.  Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.

    The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode.  If it is, then it refers to the reg_redir table to determine the true index of the register it is using.

    Also include the opcdec instruction definition.
arch/alpha/isa_traits.hh:
    Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not.

    Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers).

    Change the dependence tags to reflect the integer registers include the 8 shadow registers.

    Define function to make an ExtMachInst.  Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU.
arch/isa_parser.py:
    Have static insts decode on the ExtMachInst.
base/remote_gdb.cc:
    Support the automatic remapping of shadow registers.  Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices.
cpu/o3/regfile.hh:
    Comment out the pal registers; they are now a part of the integer registers.
cpu/simple/cpu.cc:
    Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin.
cpu/static_inst.hh:
    Change from MachInst to ExtMachInst to support shadow register renaming.

--HG--
extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5
2006-03-03 15:28:25 -05:00
Gabe Black
dd0d8e6287 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : f6db244a66431dd6b8c5ba251ed02d76cd509cff
2006-03-02 21:44:43 -05:00
Ali Saidi
0fed64a6a4 Fix fault handling, dereferincing a null pointer is bad.
--HG--
extra : convert_revision : a4f658bfd39b7f1d219ad8929b8f45457f49299f
2006-03-02 17:49:12 -05:00
Steve Reinhardt
e7f442d527 Simple program runs with sendAtomic!
Ignoring returned latency for now.
Refactored loadSections in ObjectFile hierarchy.

base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
    Have each section record a pointer to image data.
    This allows us to move common loadSections code into ObjectFile.
base/loader/object_file.cc:
    Have each section record a pointer to image data.
    This allows us to move common loadSections code into ObjectFile.
    Also explicitly load BSS now since we need to allocate the
    translations for it in syscall emulation.
cpu/base.hh:
    Don't need memPort (just pass port in to ExecContext constructor).
cpu/exec_context.cc:
cpu/exec_context.hh:
mem/port.cc:
mem/translating_port.cc:
mem/translating_port.hh:
    Pass syscall emulation Port into constructor instead of
    getting it from BaseCPU.
cpu/simple/cpu.cc:
    Explicitly choose one of three timing models.
    Statically allocate request and packet objects when possible.
    Several more minor bug fixes.
    Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now.
    Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all).
    Pass syscall emulation Port into constructor instead of
    getting it from BaseCPU.
cpu/simple/cpu.hh:
    Explicitly choose one of three timing models.
    Statically allocate request and packet objects when possible.
    Pass syscall emulation Port into constructor instead of
    getting it from BaseCPU.
mem/physical.cc:
    Set packet result field.

--HG--
extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
2006-03-02 10:31:48 -05:00
Steve Reinhardt
0c2c7171a8 More progress... run a few instructions now, but die on the second
memory access (I think because we're deallocating our one and only
CpuRequest object).

base/loader/aout_object.cc:
base/loader/ecoff_object.cc:
base/loader/elf_object.cc:
    Add flag to force allocation of new pages on data writes.
cpu/simple/cpu.cc:
    Several minor fixes.
    Switch to atomic mode for now.
mem/physical.hh:
    Don't copy the packet to the response event, just keep a reference
    to the original.
mem/translating_port.cc:
mem/translating_port.hh:
    Add parameter to writeBlobFunctional() to force allocation of
    unallocated pages on writes.

--HG--
extra : convert_revision : 05cb31c7b0047b492dcfa0d12ddee690ef762b44
2006-03-02 01:01:03 -05:00
Gabe Black
e08cf8fee0 Changed the name of the fault's invocation method from ev5_trap to invoke.
--HG--
extra : convert_revision : b7ab14ac644f6a38c69aaa5372b3002b21f34af0
2006-03-01 01:23:10 -05:00
Gabe Black
d6c0657116 Used the Fault constructor to create Interrupt faults. Using the pointer directly prevents reference counting from working correctly.
cpu/simple/cpu.cc:
    Used the Fault constructor to create an Interrupt fault.

--HG--
extra : convert_revision : ec2ef7e3cd04ee9a44628877dc6e770fb907104b
2006-03-01 00:14:09 -05:00
Kevin Lim
34da58a698 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean

arch/alpha/ev5.cc:
cpu/o3/regfile.hh:
    Hand merge.

--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
extra : convert_revision : c941dd2198851398820b38a66471372ed8454891
2006-02-28 15:16:24 -05:00
Gabe Black
6165419d35 Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context.
--HG--
extra : convert_revision : 56e33536cdd9079ace03896b85ea3c84b6eb4e57
2006-02-27 23:26:13 -05:00
Kevin Lim
70b35bab57 Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
2006-02-27 11:44:35 -05:00
Gabe Black
f1ef4a8f06 Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc
--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/tlb.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision : 9fe6863cc37347d2a6bd716c529b0a4a50b36ea7
2006-02-27 06:05:10 -05:00
Gabe Black
c5dcd152f2 Changed targetarch to just arch.
SConscript:
    Changed all of the "targetarch" files to be "arch" files
arch/SConscript:
    Added all of the remaining targetarch files to isa_switch_hdrs

--HG--
extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480
2006-02-27 05:35:43 -05:00
Gabe Black
07cd7e966e Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class, and replaced the isA templated function with them where appropriate.
arch/alpha/ev5.cc:
cpu/simple/cpu.cc:
    Changed from the isA templated function to isMachineCheckFault and isAlignmentFault
sim/faults.hh:
    Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class.

--HG--
extra : convert_revision : 3bf3a4369bc24a039648ee4f2a9c1663362ff2e2
2006-02-27 04:02:45 -05:00
Gabe Black
e66f521d5b Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

SConscript:
arch/alpha/ev5.cc:
dev/alpha_console.cc:
    Hand merged

--HG--
extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
2006-02-24 18:45:28 -05:00
Gabe Black
08637efadc Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type.
arch/alpha/alpha_memory.cc:
arch/alpha/isa/decoder.isa:
    Added news where faults are created.
arch/alpha/ev5.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Changed Fault to be a RefCountingPtr
arch/alpha/isa/fp.isa:
    Added a new where a FloatEnableFault was created.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
    Added a new where an UnimplementedFault is created.
base/refcnt.hh:
    Added include of stddef.h for the NULL macro
cpu/base_dyn_inst.cc:
    Added a new where an UnimplementedOpcodeFault is created.
cpu/o3/alpha_cpu_impl.hh:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name()
cpu/o3/regfile.hh:
    Added new where UnimplementedOpcodeFaults are created.
cpu/simple/cpu.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created.
dev/alpha_console.cc:
    Added news where MachineCheckFaults are created.
dev/pcidev.hh:
    Added news where MachineCheckFaults are generated.
dev/sinic.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables.
kern/kernel_stats.cc:
    Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future.
kern/kernel_stats.hh:
    Commented out the declaration of _fault. when fault() is called, the fault increments its own stat.
sim/faults.cc:
sim/faults.hh:
    Changed Fault from a FaultBase * to a RefCountingPtr.

--HG--
extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d
2006-02-24 01:51:45 -05:00
Ron Dreslinski
b6247c9ea7 Add support for multiple ports on the memory. Hook up simple cpu to memory.
Ready to start testing if I could fix the linking errors I can't ever seem to fix.

cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Add connecting of ports until builder can handle it.
mem/physical.cc:
    Add function to allocate a port in the object

    Remove some full_sys stuff untill needed
mem/physical.hh:
    Add function to allocate a port in the object
python/m5/objects/BaseCPU.py:
    Update the params
sim/process.cc:
    Make sure to use the right name (hopefully CPU constructor already called)

--HG--
extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85
2006-02-23 17:02:34 -05:00
Ali Saidi
e1c3acd91c Merge zizzer:/bk/m5
into  zeep.eecs.umich.edu:/z/saidi/work/m5.head

cpu/simple/cpu.cc:
    remove initCPU from constructor
dev/alpha_console.cc:
    we are panicing, so no need to return a fault

--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
2006-02-23 15:06:06 -05:00
Ali Saidi
1166d4f0bf Get rid of the xc from the alphaAccess/alphaConsole backdoor device.
Now allocate an array of stacks indexed by cpu number which specify
cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for
their stacks before continuing. This change *REQUIRES* a the new
console code to operate correctly.

arch/alpha/ev5.cc:
    Add cpuId to initCPU/initIPR functions
cpu/o3/cpu.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move the cpu initilization into an init() function since it now needs
    the CPU id which isn't known at construction
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
    instead of the bootstrap variables, add space for 64 cpu stacks in the
    alpha access structure.
sim/system.cc:
    start all cpus immediately rather than just the first one

--HG--
extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
2006-02-23 14:50:16 -05:00