fs now gets to the point where it would really like a filesystem.
Time to make the ide device work
arch/alpha/system.cc:
write the machine type and rev in the correct place
cpu/simple/cpu.cc:
reset the packet structure every time it's reused... wow the
simple cpu code for talking to memory is getting horrible.
dev/alpha_console.cc:
move the setAlphaAccess to startup() to make sure that the console
binary is loaded
dev/tsunami_cchip.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
fix a couple of bugs injected in the newmem fixes
mem/bus.cc:
More verbose bus tracing
mem/packet.hh:
Add a constructor to packet to set the result to unknown and a reset
method in the case it's being reused
mem/vport.hh:
don't need are own read/write methods since the base functional port
ones call writeBlob readBlob which do the translation for us
--HG--
extra : convert_revision : 8d0e2b782bfbf13dc5c59dab1a79a084d2a7da0a
This commit is contained in:
Ali Saidi
parent
08d9e0ea7a
commit
81a735a716
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@ -107,9 +107,9 @@ AlphaSystem::AlphaSystem(Params *p)
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if (consoleSymtab->findAddress("m5_rpb", addr)) {
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uint64_t data;
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data = htog(params()->system_type);
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virtPort.write(addr, data);
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virtPort.write(addr+0x50, data);
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data = htog(params()->system_rev);
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virtPort.write(addr, data);
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virtPort.write(addr+0x58, data);
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} else
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panic("could not find hwrpb\n");
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109
configs/test/fs.py
Normal file
109
configs/test/fs.py
Normal file
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@ -0,0 +1,109 @@
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import os
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from SysPaths import *
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# Base for tests is directory containing this file.
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test_base = os.path.dirname(__file__)
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class BaseTsunami(Tsunami):
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cchip = TsunamiCChip(pio_addr=0x801a0000000)
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pchip = TsunamiPChip(pio_addr=0x80180000000)
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pciconfig = PciConfigAll(pio_addr=0x801fe000000)
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fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
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fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
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fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
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fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
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fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
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fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
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fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
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fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
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fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
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fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
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fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
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fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
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fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
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fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
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fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
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fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
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fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
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fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
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fake_ata1 = IsaFake(pio_addr=0x801fc000170)
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fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
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io = TsunamiIO(pio_addr=0x801fc000000)
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uart = Uart8250(pio_addr=0x801fc0003f8)
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# ethernet = NSGigE(configdata=NSGigEPciData(),
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# pci_bus=0, pci_dev=1, pci_func=0)
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# etherint = NSGigEInt(device=Parent.ethernet)
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console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
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# bridge = PciFake(configdata=BridgePciData(), pci_bus=0, pci_dev=2, pci_func=0)
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#class FreeBSDTsunami(BaseTsunami):
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# disk0 = FreeBSDRootDisk(delay='0us', driveID='master')
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# ide = IdeController(disks=[Parent.disk0],
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# configdata=IdeControllerPciData(),
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# pci_func=0, pci_dev=0, pci_bus=0)
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#class LinuxTsunami(BaseTsunami):
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# disk0 = LinuxRootDisk(delay='0us', driveID='master')
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# ide = IdeController(disks=[Parent.disk0],
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# configdata=IdeControllerPciData(),
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# pci_func=0, pci_dev=0, pci_bus=0)
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class LinuxAlphaSystem(LinuxAlphaSystem):
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magicbus = Bus()
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physmem = PhysicalMemory(range = AddrRange('128MB'))
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c1 = Connector(side_a=Parent.physmem, side_b=Parent.magicbus)
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tsunami = BaseTsunami()
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c2 = Connector(side_a=Parent.tsunami.cchip, side_a_name='pio', side_b=Parent.magicbus)
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c3 = Connector(side_a=Parent.tsunami.pchip, side_a_name='pio', side_b=Parent.magicbus)
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c4 = Connector(side_a=Parent.tsunami.pciconfig, side_a_name='pio', side_b=Parent.magicbus)
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c5 = Connector(side_a=Parent.tsunami.fake_sm_chip, side_a_name='pio', side_b=Parent.magicbus)
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c7 = Connector(side_a=Parent.tsunami.fake_uart1, side_a_name='pio', side_b=Parent.magicbus)
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c8 = Connector(side_a=Parent.tsunami.fake_uart2, side_a_name='pio', side_b=Parent.magicbus)
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c9 = Connector(side_a=Parent.tsunami.fake_uart3, side_a_name='pio', side_b=Parent.magicbus)
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c10 = Connector(side_a=Parent.tsunami.fake_uart4, side_a_name='pio', side_b=Parent.magicbus)
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c12 = Connector(side_a=Parent.tsunami.fake_ppc, side_a_name='pio', side_b=Parent.magicbus)
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c14 = Connector(side_a=Parent.tsunami.fake_OROM, side_a_name='pio', side_b=Parent.magicbus)
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c16 = Connector(side_a=Parent.tsunami.fake_pnp_addr, side_a_name='pio', side_b=Parent.magicbus)
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c17 = Connector(side_a=Parent.tsunami.fake_pnp_write, side_a_name='pio', side_b=Parent.magicbus)
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c18 = Connector(side_a=Parent.tsunami.fake_pnp_read0, side_a_name='pio', side_b=Parent.magicbus)
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c19 = Connector(side_a=Parent.tsunami.fake_pnp_read1, side_a_name='pio', side_b=Parent.magicbus)
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c20 = Connector(side_a=Parent.tsunami.fake_pnp_read2, side_a_name='pio', side_b=Parent.magicbus)
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c21 = Connector(side_a=Parent.tsunami.fake_pnp_read3, side_a_name='pio', side_b=Parent.magicbus)
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c22 = Connector(side_a=Parent.tsunami.fake_pnp_read4, side_a_name='pio', side_b=Parent.magicbus)
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c23 = Connector(side_a=Parent.tsunami.fake_pnp_read5, side_a_name='pio', side_b=Parent.magicbus)
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c24 = Connector(side_a=Parent.tsunami.fake_pnp_read6, side_a_name='pio', side_b=Parent.magicbus)
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c25 = Connector(side_a=Parent.tsunami.fake_pnp_read7, side_a_name='pio', side_b=Parent.magicbus)
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c27 = Connector(side_a=Parent.tsunami.fake_ata0, side_a_name='pio', side_b=Parent.magicbus)
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c28 = Connector(side_a=Parent.tsunami.fake_ata1, side_a_name='pio', side_b=Parent.magicbus)
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c30 = Connector(side_a=Parent.tsunami.fb, side_a_name='pio', side_b=Parent.magicbus)
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c31 = Connector(side_a=Parent.tsunami.io, side_a_name='pio', side_b=Parent.magicbus)
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c32 = Connector(side_a=Parent.tsunami.uart, side_a_name='pio', side_b=Parent.magicbus)
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c33 = Connector(side_a=Parent.tsunami.console, side_a_name='pio', side_b=Parent.magicbus)
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raw_image = RawDiskImage(image_file=disk('linux.img'),
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read_only=True)
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simple_disk = SimpleDisk(disk=Parent.raw_image)
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intrctrl = IntrControl()
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cpu = SimpleCPU(mem=Parent.magicbus)
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sim_console = SimConsole(listener=ConsoleListener(port=3456))
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kernel = binary('vmlinux')
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pal = binary('ts_osfpal')
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console = binary('console')
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boot_osflags = 'root=/dev/hda1 console=ttyS0'
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readfile = os.path.join(test_base, 'halt.sh')
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BaseCPU.itb = AlphaITB()
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BaseCPU.dtb = AlphaDTB()
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BaseCPU.system = Parent.any
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class TsunamiRoot(Root):
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pass
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root = TsunamiRoot(clock = '2GHz', system = LinuxAlphaSystem())
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@ -507,6 +507,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
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data_read_pkt->req = data_read_req;
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data_read_pkt->data = new uint8_t[8];
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#endif
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data_read_pkt->reset();
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data_read_pkt->addr = data_read_req->getPaddr();
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data_read_pkt->size = sizeof(T);
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@ -623,6 +624,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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data_write_pkt->data = new uint8_t[64];
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memcpy(data_write_pkt->data, &data, sizeof(T));
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#else
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data_write_pkt->reset();
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data_write_pkt->data = (uint8_t *)&data;
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#endif
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data_write_pkt->addr = data_write_req->getPaddr();
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@ -990,6 +992,7 @@ SimpleCPU::tick()
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ifetch_pkt->req = ifetch_req;
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ifetch_pkt->size = sizeof(MachInst);
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#endif
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ifetch_pkt->reset();
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ifetch_pkt->addr = ifetch_req->getPaddr();
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sendIcacheRequest(ifetch_pkt);
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@ -72,12 +72,12 @@ AlphaConsole::AlphaConsole(Params *p)
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alphaAccess->inputChar = 0;
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bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
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system->setAlphaAccess(pioAddr);
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}
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void
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AlphaConsole::startup()
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{
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system->setAlphaAccess(pioAddr);
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alphaAccess->numCPUs = system->getNumCPUs();
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alphaAccess->kernStart = system->getKernelStart();
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alphaAccess->kernEnd = system->getKernelEnd();
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@ -74,7 +74,7 @@ TsunamiCChip::read(Packet &pkt)
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DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt.addr, pkt.size);
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assert(pkt.result == Unknown);
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assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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Addr regnum = (pkt.addr - pioAddr) >> 6;
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@ -179,8 +179,8 @@ TsunamiCChip::read(Packet &pkt)
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTFN("Tsunami CChip: read regnum=%#x size=%d data=%lld\n", regnum,
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pkt.size, *data64);
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DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n",
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regnum, pkt.size, *data64);
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pkt.result = Success;
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return pioDelay;
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@ -282,7 +282,7 @@ TsunamiCChip::write(Packet &pkt)
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if(!supportedWrite)
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panic("TSDEV_CC_MISC write not implemented\n");
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break;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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@ -71,7 +71,7 @@ TsunamiPChip::read(Packet &pkt)
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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pkt.time = curTick + pioDelay;
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Addr daddr = pkt.addr - pioAddr;
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Addr daddr = (pkt.addr - pioAddr) >> 6;;
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uint64_t *data64;
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@ -159,7 +159,7 @@ TsunamiPChip::write(Packet &pkt)
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assert(pkt.result == Unknown);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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Addr daddr = pkt.addr - pioAddr;
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Addr daddr = (pkt.addr - pioAddr) >> 6;
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uint64_t data64 = *(uint64_t *)pkt.data;
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assert(pkt.size == sizeof(uint64_t));
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@ -225,7 +225,7 @@ TsunamiPChip::write(Packet &pkt)
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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panic("Default in PChip write reached reading 0x%x\n", daddr);
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} // uint64_t
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@ -111,7 +111,7 @@ Tick
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Uart8250::read(Packet &pkt)
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{
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assert(pkt.result == Unknown);
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assert(pkt.addr > pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
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assert(pkt.size == 1);
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pkt.time = curTick + pioDelay;
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@ -189,7 +189,10 @@ Uart8250::read(Packet &pkt)
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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/* uint32_t d32 = *data;
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DPRINTF(Uart, "Register read to register %#x returned %#x\n", daddr, d32);
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*/
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pkt.result = Success;
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return pioDelay;
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}
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@ -269,6 +272,7 @@ Uart8250::write(Packet &pkt)
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panic("Tried to access a UART port that doesn't exist\n");
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break;
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}
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pkt.result = Success;
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return pioDelay;
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}
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@ -57,6 +57,7 @@ Bus::findPort(Addr addr, int id)
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if (portList[i].range == addr) {
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dest_id = portList[i].portId;
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found = true;
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DPRINTF(Bus, "Found Addr: %llx on device %d\n", addr, dest_id);
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}
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i++;
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}
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@ -128,6 +128,12 @@ struct Packet
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/** Accessor function that returns the destination index of
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the packet. */
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short getDest() const { return dest; }
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Packet()
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: result(Unknown)
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{}
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void reset() { result = Unknown; }
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};
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#endif //__MEM_PACKET_HH
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33
mem/vport.hh
33
mem/vport.hh
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@ -63,39 +63,6 @@ class VirtualPort : public FunctionalPort
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*/
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bool nullExecContext() { return xc != NULL; }
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/** Write a piece of data into a virtual address.
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* @param vaddr virtual address to write to
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* @param data data to write
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*/
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template <typename T>
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inline void write(Addr vaddr, T data)
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{
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Addr paddr;
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if (xc)
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paddr = TheISA::vtophys(xc,vaddr);
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else
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paddr = TheISA::vtophys(vaddr);
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FunctionalPort::write(paddr, data);
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}
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/** Read data from a virtual address and return it.
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* @param vaddr address to read
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* @return data read
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*/
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template <typename T>
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inline T read(Addr vaddr)
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{
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Addr paddr;
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if (xc)
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paddr = TheISA::vtophys(xc,vaddr);
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else
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paddr = TheISA::vtophys(vaddr);
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return FunctionalPort::read<T>(paddr);
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}
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/** Version of readblob that translates virt->phys and deals
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* with page boundries. */
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virtual void readBlob(Addr addr, uint8_t *p, int size);
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Loading…
Reference in a new issue