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Fixes to SPARC for syscall emulation mode.

Browse source 
arch/sparc/isa/base.isa:
arch/sparc/isa/decoder.isa:
arch/sparc/isa/formats.isa:
arch/sparc/isa/formats/branch.isa:
arch/sparc/isa/formats/integerop.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/nop.isa:
arch/sparc/isa/formats/trap.isa:
arch/sparc/isa/formats/unknown.isa:
arch/sparc/isa/includes.isa:
arch/sparc/isa/operands.isa:
    Fixes towards running in syscall emulation mode.
arch/sparc/linux/process.cc:
    Fixed the assert and comment to check that the Num_Syscall_Descs is less than or equal to 284. Why does this assert need to exist anyway?
base/loader/elf_object.cc:
    Cleared out comments about resolved issues.
cpu/simple/cpu.cc:
    Use NNPC for both SPARC and MIPS, instead of just MIPS
configs/test/hello_sparc:
    A test program for SPARC which prints "Hello World!"

--HG--
rename : arch/sparc/isa/formats/noop.isa => arch/sparc/isa/formats/nop.isa
extra : convert_revision : 10b3e3b9f21c215d809cffa930448007102ba698
This commit is contained in:
Gabe Black 2006-03-31 20:31:53 -05:00
parent 2177d822ce
commit 5c79eb0410
15 changed files with 737 additions and 217 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

59
arch/sparc/isa/base.isa
View file

@ -57,6 +57,12 @@ output header {{
};
bool passesCondition(uint32_t codes, uint32_t condition);
inline int64_t sign_ext(uint64_t data, int origWidth)
{
int shiftAmount = sizeof(uint64_t) - origWidth;
return (((int64_t)data) << shiftAmount) >> shiftAmount;
}
}};
def template ROrImmDecode {{
@ -68,28 +74,59 @@ def template ROrImmDecode {{
let {{
def splitOutImm(code):
matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>d{0,2})')
matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)')
rOrImmMatch = matcher.search(code)
if (rOrImmMatch == None):
return (False, CodeBlock(code), None, '', '')
rString = matcher.sub(r'(?P=rNum)', rOrImmMatch.string)
iString = matcher.sub(r'(?P=iNum)', rOrImmMatch.string)
return (False, code, '', '', '')
rString = rOrImmMatch.group("rNum")
iString = rOrImmMatch.group("iNum")
orig_code = code
code = matcher.sub(r'Rs(?P<rNum>)', orig_code)
code = matcher.sub('Rs' + rOrImmMatch.group("rNum"), orig_code)
imm_code = matcher.sub('imm', orig_code)
return (True, CodeBlock(code), CodeBlock(imm_code), rString, iString)
return (True, code, imm_code, rString, iString)
def genCompositeIop(code, name, Name, parent, opt_flags, **extras):
origBlock = CodeBlock(code)
composite = code
for snippet in extras.values():
composite += ('\n' + snippet)
compositeBlock = CodeBlock(composite)
iop = InstObjParams(name, Name, parent, compositeBlock, opt_flags)
iop.code = origBlock.code
iop.orig_code = origBlock.orig_code
for (name, snippet) in extras.items():
exec "iop.%s = CodeBlock(snippet).code" % name
return iop
}};
output decoder {{
inline void printMnemonic(std::ostream &os, const char * mnemonic)
{
ccprintf(os, "\t%s ", mnemonic);
}
void
SparcStaticInst::printReg(std::ostream &os, int reg) const
{
if (reg < FP_Base_DepTag) {
ccprintf(os, "r%d", reg);
}
const int MaxGlobal = 8;
const int MaxOutput = 16;
const int MaxLocal = 24;
const int MaxInput = 32;
if (reg == FramePointerReg)
ccprintf(os, "%%fp");
else if (reg == StackPointerReg)
ccprintf(os, "%%sp");
else if(reg < MaxGlobal)
ccprintf(os, "%%g%d", reg);
else if(reg < MaxOutput)
ccprintf(os, "%%o%d", reg - MaxGlobal);
else if(reg < MaxLocal)
ccprintf(os, "%%l%d", reg - MaxOutput);
else if(reg < MaxInput)
ccprintf(os, "%%i%d", reg - MaxLocal);
else {
ccprintf(os, "f%d", reg - FP_Base_DepTag);
ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
}
}
@ -98,7 +135,7 @@ output decoder {{
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
printMnemonic(ss, mnemonic);
// just print the first two source regs... if there's
// a third one, it's a read-modify-write dest (Rc),

182
arch/sparc/isa/decoder.isa
View file

@ -7,61 +7,66 @@ decode OP default Unknown::unknown()
{
0x0: decode OP2
{
format Branch
//Throw an illegal instruction acception
0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
0x1: decode BPCC
{
//Throw an illegal instruction acception
0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
0x1: decode BPCC
format Branch19
{
0x0: bpcci({{
NNPC = xc->readNextNPC();
if(passesCondition(CcrIcc, COND2))
;//branchHere
NNPC = xc->readPC() + disp;
}});
0x2: bpccx({{
if(passesCondition(CcrXcc, COND2))
;//branchHere
NNPC = xc->readPC() + disp;
}});
}
0x2: bicc({{
if(passesCondition(CcrIcc, COND2))
;//branchHere
}});
0x3: decode RCOND2
}
0x2: Branch22::bicc({{
if(passesCondition(CcrIcc, COND2))
NNPC = xc->readPC() + disp;
}});
0x3: decode RCOND2
{
format BranchSplit
{
0x1: bpreq({{
if(Rs1 == 0)
;//branchHere
NNPC = xc->readPC() + disp;
}});
0x2: bprle({{
if(Rs1 <= 0)
;//branchHere
NNPC = xc->readPC() + disp;
}});
0x3: bprl({{
if(Rs1 < 0)
;//branchHere
NNPC = xc->readPC() + disp;
}});
0x5: bprne({{
if(Rs1 != 0)
;//branchHere
NNPC = xc->readPC() + disp;
}});
0x6: bprg({{
if(Rs1 > 0)
;//branchHere
NNPC = xc->readPC() + disp;
}});
0x7: bprge({{
if(Rs1 >= 0)
;//branchHere
NNPC = xc->readPC() + disp;
}});
}
//SETHI (or NOP if rd == 0 and imm == 0)
0x4: IntOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
0x6: Trap::fbfcc({{fault = new FpDisabled;}});
}
//SETHI (or NOP if rd == 0 and imm == 0)
0x4: SetHi::sethi({{Rd = imm;}});
0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
0x6: Trap::fbfcc({{fault = new FpDisabled;}});
}
0x1: Branch::call({{
0x1: Branch30::call({{
//branch here
Rd = xc->readPC();
R15 = xc->readPC();
NNPC = R15 + disp;
}});
0x2: decode OP3 {
format IntOp {
@ -69,41 +74,40 @@ decode OP default Unknown::unknown()
0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm)+1;}});
0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm;}});
0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm;}});
0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm);}});
0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm + CcrIccC;}});
0x09: mulx({{Rd = Rs1 * Rs2_or_imm;}});
0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm13)+1;}});
0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + CcrIccC;}});
0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
0x0A: umul({{
Rd = Rs1.udw<31:0> * Rs2_or_imm<31:0>;
Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
YValue = Rd<63:32>;
}});
0x0B: smul({{
Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm<31:0>;
Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
YValue = Rd.sdw;
}});
0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm) + 1 + CcrIccC;}});
0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + CcrIccC;}});
0x0D: udivx({{
if(val2 == 0) fault = new DivisionByZero;
else Rd.udw = Rs1.udw / Rs2_or_imm;
if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
else Rd.udw = Rs1.udw / Rs2_or_imm13;
}});
0x0E: udiv({{
uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
if(Rs2_or_imm.udw == 0) fault = new DivisionByZero;
if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
else
{
Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm.udw;
Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
if(Rd.udw >> 32 != 0)
Rd.udw = 0xFFFFFFFF;
}
}});
0x0F: sdiv({{
if(val2 == 0)
if(Rs2_or_imm13 == 0)
fault = new DivisionByZero;
else
{
Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm;
Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm13;
if(Rd.udw<63:31> != 0)
Rd.udw = 0x7FFFFFFF;
else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
@ -113,7 +117,7 @@ decode OP default Unknown::unknown()
}
format IntOpCc {
0x10: addcc({{
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
@ -124,11 +128,11 @@ decode OP default Unknown::unknown()
0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
0x14: subcc({{
int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 - val2;}},
{{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
{{((Rs1 >> 1) + (~val2) >> 1) +
{{(((Rs1 >> 1) + (~val2) >> 1) +
((Rs1 | ~val2) & 0x1))<63:>}},
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
);//SUBcc
@ -136,7 +140,7 @@ decode OP default Unknown::unknown()
0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
0x18: addccc({{
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
int64_t resTemp, val2 = Rs2_or_imm13;
int64_t carryin = CcrIccC;
Rd = resTemp = Rs1 + val2 + carryin;}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
@ -147,38 +151,38 @@ decode OP default Unknown::unknown()
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//ADDCcc
0x1A: umulcc({{
uint64_t resTemp, val2 = (I ? SIMM13 : Rs2);
uint64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
YValue = resTemp<63:32>;}},
{{0}},{{0}},{{0}},{{0}});//UMULcc
0x1B: smulcc({{
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
YValue = resTemp<63:32>;}}
,{{0}},{{0}},{{0}},{{0}});//SMULcc
0x1C: subccc({{
int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
int64_t resTemp, val2 = Rs2_or_imm13;
int64_t carryin = CcrIccC;
Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
{{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
{{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
{{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
{{(((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
{{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
);//SUBCcc
0x1D: udivxcc({{
uint64_t val2 = (I ? SIMM13 : Rs2.udw);
if(val2 == 0) fault = new DivisionByZero;
else Rd.udw = Rs1.udw / val2;}}
if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
else Rd = Rs1.udw / Rs2_or_imm13;}}
,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
0x1E: udivcc({{
uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
uint32_t resTemp, val2 = Rs2_or_imm13;
int32_t overflow;
if(val2 == 0) fault = new DivisionByZero;
else
{
resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
int32_t overflow = (resTemp<63:32> != 0);
if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
else rd.udw = resTemp;
overflow = (resTemp<63:32> != 0);
if(overflow) Rd = resTemp = 0xFFFFFFFF;
else Rd = resTemp;
} }},
{{0}},
{{overflow}},
@ -186,16 +190,17 @@ decode OP default Unknown::unknown()
{{0}}
);//UDIVcc
0x1F: sdivcc({{
int32_t resTemp, val2 = (I ? SIMM13 : Rs2.sdw<31:0>);
int32_t resTemp, val2 = Rs2_or_imm13;
int32_t overflow, underflow;
if(val2 == 0) fault = new DivisionByZero;
else
{
Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
int32_t overflow = (resTemp<63:31> != 0);
int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
else rd.udw = resTemp;
Rd = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
overflow = (resTemp<63:31> != 0);
underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
if(overflow) Rd = resTemp = 0x7FFFFFFF;
else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000;
else Rd = resTemp;
} }},
{{0}},
{{overflow || underflow}},
@ -203,7 +208,7 @@ decode OP default Unknown::unknown()
{{0}}
);//SDIVcc
0x20: taddcc({{
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
{{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
@ -212,16 +217,16 @@ decode OP default Unknown::unknown()
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TADDcc
0x21: tsubcc({{
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
{{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
{{overflow}},
{{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TSUBcc
0x22: taddcctv({{
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
if(overflow) fault = new TagOverflow;}},
@ -231,7 +236,7 @@ decode OP default Unknown::unknown()
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TADDccTV
0x23: tsubcctv({{
int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
int64_t resTemp, val2 = Rs2_or_imm13;
Rd = resTemp = Rs1 + val2;
int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
if(overflow) fault = new TagOverflow;}},
@ -241,10 +246,10 @@ decode OP default Unknown::unknown()
{{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
);//TSUBccTV
0x24: mulscc({{
int64_t resTemp, multiplicand = (I ? SIMM13 : Rs2);
int64_t resTemp, multiplicand = Rs2_or_imm13;
int32_t multiplier = Rs1<31:0>;
int32_t savedLSB = Rs1<0:>;
multiplier = multipler<31:1> |
multiplier = multiplier<31:1> |
((CcrIccN
^ CcrIccV) << 32);
if(!YValue<0:>)
@ -276,11 +281,11 @@ decode OP default Unknown::unknown()
0x2: rdccr({{Rd = Ccr;}}); //RDCCR
0x3: rdasi({{Rd = Asi;}}); //RDASI
0x4: PrivTick::rdtick({{Rd = Tick;}});
0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
0x5: rdpc({{Rd = xc->readPC();}}); //RDPC
0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
0xF: decode I {
0x0: Noop::membar({{/*Membar isn't needed yet*/}});
0x1: Noop::stbar({{/*Stbar isn't needed yet*/}});
0x0: Nop::membar({{/*Membar isn't needed yet*/}});
0x1: Nop::stbar({{/*Stbar isn't needed yet*/}});
}
}
0x2A: decode RS1 {
@ -336,12 +341,14 @@ decode OP default Unknown::unknown()
}});//SDIVX
0x2E: decode RS1 {
0x0: IntOp::popc({{
int64_t count = 0, val2 = Rs2_or_imm;
int64_t count = 0;
uint64_t temp = Rs2_or_imm13;
//Count the 1s in the front 4bits until none are left
uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
for(unsigned int x = 0; x < 16; x++)
while(temp)
{
count += oneBits[Rs2_or_imm13 & 0xF];
val2 >> 4;
count += oneBits[temp & 0xF];
temp = temp >> 4;
}
}});//POPC
}
@ -401,8 +408,25 @@ decode OP default Unknown::unknown()
0x34: Trap::fpop1({{fault = new FpDisabled;}});
0x35: Trap::fpop2({{fault = new FpDisabled;}});
0x38: Branch::jmpl({{/*Stuff*/}});
0x39: Branch::return({{/*Other Stuff*/}});
0x38: Branch::jmpl({{
Addr target = Rs1 + Rs2_or_imm13;
if(target && 0x3)
fault = new MemAddressNotAligned;
else
{
Rd = xc->readPC();
NNPC = target;
}
}});
0x39: Branch::return({{
Addr target = Rs1 + Rs2_or_imm13;
if(target && 0x3)
fault = new MemAddressNotAligned;
else
NNPC = target;
//This needs to change the register window
//like restore does
}});
0x3A: decode CC
{
0x0: Trap::tcci({{
@ -512,7 +536,7 @@ decode OP default Unknown::unknown()
0x26: Trap::stqf({{fault = new FpDisabled;}});
0x27: Trap::stdf({{fault = new FpDisabled;}});
0x2D: Noop::prefetch({{ }}); //PREFETCH
0x2D: Nop::prefetch({{ }}); //PREFETCH
0x30: Trap::ldfa({{return new FpDisabled;}});
@ -528,7 +552,7 @@ decode OP default Unknown::unknown()
Mem.uw = Rd.uw;
Rd.uw = val;
}}); //CASA
0x3D: Noop::prefetcha({{ }}); //PREFETCHA
0x3D: Nop::prefetcha({{ }}); //PREFETCHA
0x3E: Cas::casxa({{
uint64_t val = Mem.udw;
if(Rs2 == val)

6
arch/sparc/isa/formats.isa
View file

@ -2,6 +2,9 @@
//Templates from this format are used later
##include "formats/basic.isa"
//Include the noop format
##include "formats/nop.isa"
//Include the integerOp and integerOpCc format
##include "formats/integerop.isa"
@ -23,6 +26,3 @@
//Include the branch format
##include "formats/branch.isa"
//Include the noop format
##include "formats/noop.isa"

243
arch/sparc/isa/formats/branch.isa
View file

@ -5,7 +5,7 @@
output header {{
/**
* Base class for integer operations.
* Base class for branch operations.
*/
class Branch : public SparcStaticInst
{
@ -19,12 +19,187 @@ output header {{
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for branch operations with an immediate displacement.
*/
class BranchDisp : public Branch
{
protected:
// Constructor
BranchDisp(const char *mnem, MachInst _machInst,
OpClass __opClass) :
Branch(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
int32_t disp;
};
/**
* Base class for branches with 19 bit displacements.
*/
class Branch19 : public BranchDisp
{
protected:
// Constructor
Branch19(const char *mnem, MachInst _machInst,
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
disp = sign_ext(DISP19 << 2, 21);
}
};
/**
* Base class for branches with 22 bit displacements.
*/
class Branch22 : public BranchDisp
{
protected:
// Constructor
Branch22(const char *mnem, MachInst _machInst,
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
disp = sign_ext(DISP22 << 2, 24);
}
};
/**
* Base class for branches with 30 bit displacements.
*/
class Branch30 : public BranchDisp
{
protected:
// Constructor
Branch30(const char *mnem, MachInst _machInst,
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
disp = sign_ext(DISP30 << 2, 32);
}
};
/**
* Base class for 16bit split displacements.
*/
class BranchSplit : public BranchDisp
{
protected:
// Constructor
BranchSplit(const char *mnem, MachInst _machInst,
OpClass __opClass) :
BranchDisp(mnem, _machInst, __opClass)
{
disp = sign_ext((D16HI << 16) | (D16LO << 2), 18);
}
};
/**
* Base class for branches that use an immediate and a register to
* compute their displacements.
*/
class BranchImm13 : public Branch
{
protected:
// Constructor
BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) :
Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13))
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
int32_t imm;
};
}};
output decoder {{
std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
std::string Branch::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Branch instruction\n";
std::stringstream response;
printMnemonic(response, mnemonic);
if (_numSrcRegs > 0)
{
printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs; x++)
{
response << ", ";
printReg(response, _srcRegIdx[x]);
}
}
if (_numDestRegs > 0)
{
if(_numSrcRegs > 0)
response << ", ";
printReg(response, _destRegIdx[0]);
}
return response.str();
}
std::string BranchImm13::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
if (_numSrcRegs > 0)
{
printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs; x++)
{
response << ", ";
printReg(response, _srcRegIdx[x]);
}
}
if(_numSrcRegs > 0)
response << ", ";
ccprintf(response, "0x%x", imm);
if (_numDestRegs > 0)
{
response << ", ";
printReg(response, _destRegIdx[0]);
}
return response.str();
}
std::string BranchDisp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
std::string symbol;
Addr symbolAddr;
Addr target = disp + pc;
printMnemonic(response, mnemonic);
ccprintf(response, "0x%x", target);
if(symtab->findNearestSymbol(target, symbol, symbolAddr))
{
ccprintf(response, " <%s", symbol);
if(symbolAddr != target)
ccprintf(response, "+0x%x>", target - symbolAddr);
else
ccprintf(response, ">");
}
return response.str();
}
}};
@ -37,6 +212,8 @@ def template BranchExecute {{
%(op_decl)s;
%(op_rd)s;
NNPC = xc->readNextNPC();
%(code)s;
if(fault == NoFault)
@ -49,13 +226,63 @@ def template BranchExecute {{
}
}};
// Primary format for integer operate instructions:
// Primary format for branch instructions:
def format Branch(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BranchExecute.subst(iop)
if usesImm:
imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
codeBlk, opt_flags)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += BranchExecute.subst(imm_iop)
decode_block = ROrImmDecode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
}};
// Primary format for branch instructions:
def format Branch19(code, *opt_flags) {{
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
}};
// Primary format for branch instructions:
def format Branch22(code, *opt_flags) {{
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
}};
// Primary format for branch instructions:
def format Branch30(code, *opt_flags) {{
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
}};
// Primary format for branch instructions:
def format BranchSplit(code, *opt_flags) {{
codeBlk = CodeBlock(code)
iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)
decode_block = BasicDecode.subst(iop)
}};

307
arch/sparc/isa/formats/integerop.isa
View file

@ -11,51 +11,222 @@ output header {{
{
protected:
// Constructor
IntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
IntOp(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
virtual bool printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for immediate integer operations.
*/
class IntOpImm : public IntOp
{
protected:
// Constructor
IntOpImm(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
IntOp(mnem, _machInst, __opClass)
{
}
uint32_t imm;
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
virtual bool printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for 10 bit immediate integer operations.
*/
class IntOpImm10 : public IntOp
class IntOpImm10 : public IntOpImm
{
protected:
// Constructor
IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
IntOp(mnem, _machInst, __opClass), imm(SIMM10)
IntOpImm10(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
imm = SIMM10;
}
uint32_t imm;
};
/**
* Base class for 13 bit immediate integer operations.
*/
class IntOpImm13 : public IntOp
class IntOpImm13 : public IntOpImm
{
protected:
// Constructor
IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
IntOp(mnem, _machInst, __opClass), imm(SIMM13)
IntOpImm13(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
imm = SIMM13;
}
};
/**
* Base class for sethi.
*/
class SetHi : public IntOpImm
{
protected:
// Constructor
SetHi(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
imm = (IMM22 << 10) & 0xFFFFFC00;
}
uint32_t imm;
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
def template SetHiDecode {{
{
if(RD == 0 && IMM22 == 0)
return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass));
else
return (SparcStaticInst *)(new %(class_name)s(machInst));
}
}};
output decoder {{
bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symbab) const
{
if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
{
printMnemonic(os, "mov");
if(_numSrcRegs > 0)
printReg(os, _srcRegIdx[1]);
ccprintf(os, ", ");
if(_numDestRegs > 0)
printReg(os, _destRegIdx[0]);
return true;
}
return false;
}
bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symbab) const
{
if(!strcmp(mnemonic, "or"))
{
if(_srcRegIdx[0] == 0)
{
if(imm == 0)
{
printMnemonic(os, "clr");
if(_numDestRegs > 0)
printReg(os, _destRegIdx[0]);
return true;
}
else
{
printMnemonic(os, "mov");
ccprintf(os, ", 0x%x, ", imm);
if(_numDestRegs > 0)
printReg(os, _destRegIdx[0]);
return true;
}
}
else if(imm == 0)
{
printMnemonic(os, "mov");
if(_numSrcRegs > 0)
printReg(os, _srcRegIdx[0]);
ccprintf(os, ", ");
if(_numDestRegs > 0)
printReg(os, _destRegIdx[0]);
return true;
}
}
return false;
}
std::string IntOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Integer instruction\n";
std::stringstream response;
if(!printPseudoOps(response, pc, symtab))
{
printMnemonic(response, mnemonic);
if (_numSrcRegs > 0)
{
printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs; x++)
{
response << ", ";
printReg(response, _srcRegIdx[x]);
}
}
if (_numDestRegs > 0)
{
if(_numSrcRegs > 0)
response << ", ";
printReg(response, _destRegIdx[0]);
}
}
return response.str();
}
std::string IntOpImm::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
if(!printPseudoOps(response, pc, symtab))
{
printMnemonic(response, mnemonic);
if (_numSrcRegs > 1)
{
printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs - 1; x++)
{
response << ", ";
printReg(response, _srcRegIdx[x]);
}
}
if(_numSrcRegs > 0)
response << ", ";
ccprintf(response, "0x%x", imm);
if (_numDestRegs > 0)
{
response << ", ";
printReg(response, _destRegIdx[0]);
}
}
return response.str();
}
std::string SetHi::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
if(_numSrcRegs > 0)
response << ", ";
ccprintf(response, "%%hi(0x%x), ", imm);
printReg(response, _destRegIdx[0]);
return response.str();
}
}};
@ -69,97 +240,87 @@ def template IntOpExecute {{
%(op_rd)s;
%(code)s;
//Write the resulting state to the execution context
if(fault == NoFault)
%(op_wb)s;
return fault;
}
}};
def template IntOpCcExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault;
%(op_decl)s;
%(op_rd)s;
%(code)s;
//Write the resulting state to the execution context
if(fault == NoFault)
{
%(op_wb)s;
CcrIccN = Rd & (1 << 63);
CcrIccZ = (Rd == 0);
CcrIccV = ivValue;
CcrIccC = icValue;
CcrXccN = Rd & (1 << 31);
CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
CcrXccV = xvValue;
CcrXccC = xcValue;
}
return fault;
}
}};
def template IntOpCcResExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault;
%(op_decl)s;
%(op_rd)s;
%(code)s;
//Write the resulting state to the execution context
if(fault == NoFault)
{
%(op_wb)s;
CcrIccN = Rd & (1 << 63);
CcrIccZ = (Rd == 0);
CcrXccN = Rd & (1 << 31);
CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
CcrIccV = CcrIccC = CcrXccV = CcrXccC = 0;
%(cc_code)s;
}
return fault;
}
}};
let {{
def doIntFormat(code, execTemplate, name, Name, opt_flags):
(usesImm, cblk, immCblk, rString, iString) = splitOutImm(code)
iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
def doIntFormat(code, ccCode, name, Name, opt_flags):
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
iop = genCompositeIop(code, name, Name,
'IntOp', opt_flags, cc_code=ccCode)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = execTemplate.subst(iop)
exec_output = IntOpExecute.subst(iop)
if usesImm:
imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
immCblk, opt_flags)
imm_iop = genCompositeIop(code, name, Name + 'Imm',
'IntOpImm' + iString, opt_flags, cc_code=ccCode)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += execTemplate.subst(imm_iop)
exec_output += IntOpExecute.subst(imm_iop)
decode_block = ROrImmDecode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
return (header_output, decoder_output, exec_output, decode_block)
calcCcCode = '''
CcrIccN = (Rd >> 63) & 1;
CcrIccZ = (Rd == 0);
CcrXccN = (Rd >> 31) & 1;
CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
CcrIccV = %(ivValue)s;
CcrIccC = %(icValue)s;
CcrXccV = %(xvValue)s;
CcrXccC = %(xcValue)s;
'''
}};
// Primary format for integer operate instructions:
def format IntOp(code, *opt_flags) {{
doIntFormat(code, IntOpExecute, name, Name, opt_flags)
ccCode = ''
(header_output,
decoder_output,
exec_output,
decode_block) = doIntFormat(code, ccCode,
name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
('xvValue', xvValue), ('xcValue', xcValue)):
code.replace(marker, value)
doIntFormat(code, IntOpCcExecute, name, Name, opt_flags)
ccCode = calcCcCode % vars()
(header_output,
decoder_output,
exec_output,
decode_block) = doIntFormat(code, ccCode,
name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCcRes(code, *opt_flags) {{
doIntFormat(code, IntOpCcResExecute, name, Name, opt_flags)
ccCode = calcCcCode % {"icValue":"0",
"ivValue":"0",
"xcValue":"0",
"xvValue":"0"}
(header_output,
decoder_output,
exec_output,
decode_block) = doIntFormat(code, ccCode,
name, Name, opt_flags)
}};
def format SetHi(code, *opt_flags) {{
iop = genCompositeIop(code, name, Name, 'SetHi',
opt_flags, cc_code='')
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = IntOpExecute.subst(iop)
decode_block = SetHiDecode.subst(iop)
}};

95
arch/sparc/isa/formats/mem.isa
View file

@ -5,7 +5,7 @@
output header {{
/**
* Base class for integer operations.
* Base class for memory operations.
*/
class Mem : public SparcStaticInst
{
@ -20,12 +20,76 @@ output header {{
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
/**
* Class for memory operations which use an immediate offset.
*/
class MemImm : public Mem
{
protected:
// Constructor
MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
Mem(mnem, _machInst, __opClass), imm(SIMM13)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
int imm;
};
}};
output decoder {{
std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
std::string Mem::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Memory instruction\n";
std::stringstream response;
bool load = (_numDestRegs == 1);
printMnemonic(response, mnemonic);
if(!load)
{
printReg(response, _srcRegIdx[0]);
ccprintf(response, ", ");
}
ccprintf(response, "[ ");
printReg(response, _srcRegIdx[load ? 0 : 1]);
ccprintf(response, " + ");
printReg(response, _srcRegIdx[load ? 1 : 2]);
ccprintf(response, " ]");
if(load)
{
ccprintf(response, ", ");
printReg(response, _destRegIdx[0]);
}
return response.str();
}
std::string MemImm::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
bool load = (_numDestRegs == 1);
printMnemonic(response, mnemonic);
if(!load)
{
printReg(response, _srcRegIdx[0]);
ccprintf(response, ", ");
}
ccprintf(response, "[ ");
printReg(response, _srcRegIdx[load ? 0 : 1]);
ccprintf(response, " + 0x%x ]", imm);
if(load)
{
ccprintf(response, ", ");
printReg(response, _destRegIdx[0]);
}
return response.str();
}
}};
@ -50,19 +114,16 @@ def template MemExecute {{
}
}};
// Primary format for integer operate instructions:
// Primary format for memory instructions:
def format Mem(code, *opt_flags) {{
addrCalc = 'EA = I ? (Rs1 + SIMM13) : Rs1 + Rs2;'
composite = code + '\n' + addrCalc
origCodeBlk = CodeBlock(code)
compositeBlk = CodeBlock(composite)
addrCalcBlk = CodeBlock(addrCalc)
iop = InstObjParams(name, Name, 'SparcStaticInst', compositeBlk, opt_flags)
iop.code = origCodeBlk.code
iop.orig_code = origCodeBlk.orig_code
iop.ea_code = addrCalcBlk.code
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = MemExecute.subst(iop)
addrCalcReg = 'EA = Rs1 + Rs2;'
addrCalcImm = 'EA = Rs1 + SIMM13;'
iop = genCompositeIop(code, name, Name, 'Mem',
opt_flags, ea_code=addrCalcReg)
iop_imm = genCompositeIop(code, name, Name + 'Imm', 'MemImm',
opt_flags, ea_code=addrCalcImm)
header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
decode_block = ROrImmDecode.subst(iop)
exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
}};

34
arch/sparc/isa/formats/noop.isa → arch/sparc/isa/formats/nop.isa
View file

@ -1,35 +1,47 @@
////////////////////////////////////////////////////////////////////
//
// Noop instruction
// Nop instruction
//
output header {{
/**
* Noop class.
* Nop class.
*/
class Noop : public SparcStaticInst
class Nop : public SparcStaticInst
{
protected:
public:
// Constructor
Noop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
Nop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
// All Nop instructions do the same thing, so this can be
// defined here. Nops can be defined directly, so there needs
// to be a default implementation
Fault execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
//Nothing to see here, move along
return NoFault;
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string Noop::generateDisassembly(Addr pc,
std::string Nop::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Noop\n";
std::stringstream response;
printMnemonic(response, mnemonic);
return response.str();
}
}};
def template NoopExecute {{
def template NopExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@ -39,12 +51,12 @@ def template NoopExecute {{
}};
// Primary format for integer operate instructions:
def format Noop(code, *opt_flags) {{
def format Nop(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
iop = InstObjParams(name, Name, 'Nop', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = NoopExecute.subst(iop)
exec_output = NopExecute.subst(iop)
}};

4
arch/sparc/isa/formats/trap.isa
View file

@ -27,7 +27,7 @@ output decoder {{
std::string Trap::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Trap instruction\n";
return "Trap instruction";
}
}};
@ -46,7 +46,7 @@ def template TrapExecute {{
def format Trap(code, *opt_flags) {{
orig_code = code
cblk = CodeBlock(code)
iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
iop = InstObjParams(name, Name, 'Trap', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)

2
arch/sparc/isa/formats/unknown.isa
View file

@ -29,7 +29,7 @@ output decoder {{
std::string Unknown::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Unknown instruction\n";
return "Unknown instruction";
}
}};

1
arch/sparc/isa/includes.isa
View file

@ -12,6 +12,7 @@ output header {{
#include "arch/sparc/faults.hh"
#include "mem/request.hh" // some constructors use MemReq flags
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/regfile.hh"
}};
output decoder {{

10
arch/sparc/isa/operands.isa
View file

@ -25,11 +25,13 @@ def operands {{
#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 4),
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
'R0': ('IntReg', 'udw', '0', None, 1),
'R16': ('IntReg', 'udw', '16', None, 1),
'R0': ('IntReg', 'udw', '0', None, 6),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 7),
'R16': ('IntReg', 'udw', '16', None, 8),
# Control registers
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
@ -57,7 +59,7 @@ def operands {{
'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
'CcrXccN': ('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25),
'CcrXccN': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_N', None, 25),
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27),
#'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28),

4
arch/sparc/linux/process.cc
View file

@ -356,9 +356,9 @@ SparcLinuxProcess::SparcLinuxProcess(const std::string &name,
stdin_fd, stdout_fd, stderr_fd, argv, envp),
Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
{
// The sparc syscall table must be <= 283 entries because that is all there
// The sparc syscall table must be <= 284 entries because that is all there
// is space for.
assert(Num_Syscall_Descs <= 283);
assert(Num_Syscall_Descs <= 284);
}

5
base/loader/elf_object.cc
View file

@ -77,11 +77,6 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data)
return NULL;
} else {
//Detect the architecture
//Versioning issues in libelf need to be resolved to get the correct
//SPARC constants.
//If MIPS supports 32 bit executables, this may need to be changed.
//Also, there are other MIPS constants which may be used, like
//EM_MIPS_RS3_LE and EM_MIPS_X
//Since we don't know how to check for alpha right now, we'll
//just assume if it wasn't something else and it's 64 bit, that's
//what it must be.

BIN
configs/test/hello_sparc Executable file
View file

Binary file not shown.

2
cpu/simple/cpu.cc
View file

@ -1089,7 +1089,7 @@ SimpleCPU::tick()
#endif // FULL_SYSTEM
}
else {
#if THE_ISA != MIPS_ISA
#if THE_ISA == ALPHA_ISA
// go to the next instruction
cpuXC->setPC(cpuXC->readNextPC());
cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));