style: [patch 3/22] reduce include dependencies in some headers

Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.
This commit is contained in:
Brandon Potter 2016-11-09 14:27:40 -06:00
parent 93d8e6b898
commit a928a438b8
106 changed files with 203 additions and 166 deletions

View file

@ -40,6 +40,7 @@
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace AlphaISA;

View file

@ -32,6 +32,7 @@
#ifndef __ARCH_ALPHA_PROCESS_HH__
#define __ARCH_ALPHA_PROCESS_HH__
#include "mem/page_table.hh"
#include "sim/process.hh"
class AlphaLiveProcess : public LiveProcess

View file

@ -53,6 +53,7 @@
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;

View file

@ -48,6 +48,7 @@
#include "arch/arm/intregs.hh"
#include "base/loader/object_file.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
class LiveProcess;

View file

@ -41,6 +41,7 @@
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;

View file

@ -35,6 +35,7 @@
#include <string>
#include <vector>
#include "mem/page_table.hh"
#include "sim/process.hh"
class LiveProcess;

View file

@ -35,6 +35,7 @@
#include "params/PowerInterrupts.hh"
#include "sim/sim_object.hh"
class BaseCPU;
class ThreadContext;
namespace PowerISA {

View file

@ -41,6 +41,7 @@
#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;

View file

@ -36,6 +36,7 @@
#include <string>
#include <vector>
#include "mem/page_table.hh"
#include "sim/process.hh"
class LiveProcess;

View file

@ -133,6 +133,7 @@
* "Stub" to allow remote cpu to debug over a serial line using gdb.
*/
#include "arch/power/remote_gdb.hh"
#include <sys/signal.h>
@ -144,6 +145,7 @@
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
using namespace std;

View file

@ -35,6 +35,7 @@
#include "params/RiscvInterrupts.hh"
#include "sim/sim_object.hh"
class BaseCPU;
class ThreadContext;
namespace RiscvISA {

View file

@ -44,6 +44,7 @@
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;

View file

@ -35,6 +35,7 @@
#include <string>
#include <vector>
#include "mem/page_table.hh"
#include "sim/process.hh"
class LiveProcess;

View file

@ -43,6 +43,7 @@
#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;

View file

@ -35,6 +35,7 @@
#include <string>
#include <vector>
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/process.hh"

View file

@ -42,6 +42,7 @@
#include "arch/x86/types.hh"
#include "arch/x86/x86_traits.hh"
#include "base/compiler.hh"
#include "base/types.hh"
namespace LittleEndianGuest {}

View file

@ -46,14 +46,13 @@
#include <vector>
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "base/trie.hh"
#include "cpu/thread_context.hh"
#include "arch/x86/system.hh"
#include "debug/MMU.hh"
class Checkpoint;
class ThreadContext;
namespace X86ISA
{

View file

@ -59,6 +59,7 @@
#include "mem/page_table.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_desc.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;

View file

@ -31,9 +31,10 @@
#include "arch/x86/pseudo_inst.hh"
#include "arch/x86/system.hh"
#include "cpu/thread_context.hh"
#include "debug/PseudoInst.hh"
#include "mem/se_translating_port_proxy.hh"
#include "sim/process.hh"
#include "sim/system.hh"
using namespace X86ISA;

View file

@ -39,19 +39,12 @@
#include "arch/x86/system.hh"
#include "arch/vtophys.hh"
#include "arch/x86/bios/intelmp.hh"
#include "arch/x86/bios/smbios.hh"
#include "arch/x86/isa_traits.hh"
#include "arch/x86/regs/misc.hh"
#include "base/intmath.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "mem/port_proxy.hh"
#include "params/X86System.hh"
#include "sim/byteswap.hh"
using namespace LittleEndianGuest;
using namespace X86ISA;

View file

@ -44,11 +44,7 @@
#include <vector>
#include "arch/x86/regs/misc.hh"
#include "base/loader/symtab.hh"
#include "cpu/pc_event.hh"
#include "kern/system_events.hh"
#include "params/X86System.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
namespace X86ISA

View file

@ -45,17 +45,13 @@
#include "arch/generic/mmapped_ipr.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/insts/microldstop.hh"
#include "arch/x86/pagetable.hh"
#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/regs/msr.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
#include "mem/packet_access.hh"
#include "mem/page_table.hh"
#include "mem/request.hh"
#include "sim/full_system.hh"

View file

@ -41,20 +41,15 @@
#define __ARCH_X86_TLB_HH__
#include <list>
#include <string>
#include <vector>
#include "arch/generic/tlb.hh"
#include "arch/x86/regs/segment.hh"
#include "arch/x86/pagetable.hh"
#include "base/trie.hh"
#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/X86TLB.hh"
#include "sim/sim_object.hh"
class ThreadContext;
class Packet;
namespace X86ISA
{

View file

@ -42,11 +42,10 @@
#include "arch/x86/interrupts.hh"
#include "arch/x86/registers.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/x86_traits.hh"
#include "cpu/base.hh"
#include "fputils/fp80.h"
#include "sim/system.hh"
#include "sim/full_system.hh"
namespace X86ISA {

View file

@ -40,16 +40,10 @@
#ifndef __ARCH_X86_UTILITY_HH__
#define __ARCH_X86_UTILITY_HH__
#include "arch/x86/regs/misc.hh"
#include "arch/x86/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"
class ThreadContext;
namespace X86ISA
{

View file

@ -32,7 +32,7 @@
#ifndef __BASE_BITFIELD_HH__
#define __BASE_BITFIELD_HH__
#include "base/types.hh"
#include <inttypes.h>
/**
* Generate a 64-bit mask of 'nbits' 1s, right justified.

View file

@ -32,7 +32,6 @@
#define __BASE_BITUNION_HH__
#include "base/bitfield.hh"
#include "base/types.hh"
// The following implements the BitUnion system of defining bitfields
//on top of an underlying class. This is done through the pervasive use of

View file

@ -35,6 +35,7 @@
#include <iostream>
#include <sstream>
#include "base/misc.hh"
#include "config/use_posix_clock.hh"
#include "sim/core.hh"
#include "sim/serialize.hh"

View file

@ -46,7 +46,8 @@
#include <sys/types.h>
#include "base/output.hh" //simout
#include "base/misc.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "debug/VNC.hh"

View file

@ -50,6 +50,7 @@
#include <queue>
#include <sstream>
#include "base/misc.hh"
#include "cpu/minor/trace.hh"
#include "cpu/activity.hh"
#include "cpu/timebuf.hh"

View file

@ -29,6 +29,7 @@
#include "cpu/testers/directedtest/InvalidateGenerator.hh"
#include "base/trace.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "debug/DirectedTest.hh"

View file

@ -41,6 +41,7 @@
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "base/trace.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "debug/DirectedTest.hh"
#include "sim/sim_exit.hh"

View file

@ -30,6 +30,7 @@
#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "debug/DirectedTest.hh"

View file

@ -46,6 +46,7 @@
#include "base/random.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "debug/MemTest.hh"
#include "mem/mem_object.hh"
#include "sim/sim_exit.hh"

View file

@ -30,6 +30,7 @@
#include "cpu/testers/rubytest/Check.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/RubyTest.hh"
#include "mem/ruby/common/SubBlock.hh"

View file

@ -31,6 +31,7 @@
#include "base/intmath.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "debug/RubyTest.hh"

View file

@ -42,6 +42,7 @@
#include "cpu/testers/rubytest/RubyTester.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "debug/RubyTest.hh"
#include "mem/ruby/common/SubBlock.hh"

View file

@ -54,6 +54,7 @@
#include "dev/arm/flash_device.hh"
#include "base/trace.hh"
#include "debug/Drain.hh"
/**

View file

@ -34,6 +34,7 @@
#define __DEV_MC146818_HH__
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "sim/eventq_impl.hh"
/** Real-Time Clock (MC146818) */

View file

@ -83,6 +83,7 @@
#include <thread>
#include <utility>
#include "base/misc.hh"
#include "dev/net/dist_packet.hh"
#include "dev/net/etherpkt.hh"
#include "sim/core.hh"

View file

@ -38,6 +38,7 @@
#include <string>
#include <vector>
#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/Ethernet.hh"
#include "debug/EthernetData.hh"

View file

@ -36,7 +36,9 @@
#include "dev/net/etherswitch.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/EthernetAll.hh"
#include "sim/core.hh"
using namespace std;

View file

@ -39,6 +39,7 @@
#include <list>
#include "base/statistics.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/GPUVRF.hh"
#include "gpu-compute/vector_register_state.hh"

View file

@ -33,7 +33,6 @@
#include <cstdio>
#include <string>
#include "cpu/thread_context.hh"
#include "debug/SyscallVerbose.hh"
#include "sim/process.hh"
#include "sim/system.hh"

View file

@ -36,9 +36,9 @@
#include <string>
#include "kern/operatingsystem.hh"
#include "sim/process.hh"
class ThreadContext;
class LiveProcess;
///
/// This class encapsulates the types, structures, constants,

View file

@ -49,6 +49,7 @@
#include "mem/cache/prefetch/stride.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/HWPrefetch.hh"
StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)

View file

@ -43,6 +43,7 @@
#include <cctype>
#include <iomanip>
#include "base/trace.hh"
#include "debug/ExternalPort.hh"
std::map<std::string, ExternalMaster::Handler *>

View file

@ -42,6 +42,7 @@
#include <cctype>
#include <iomanip>
#include "base/trace.hh"
#include "debug/ExternalPort.hh"
/** Implement a `stub' port which just responds to requests by printing

View file

@ -48,6 +48,7 @@
#include <vector>
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/MemChecker.hh"
#include "params/MemChecker.hh"

View file

@ -38,13 +38,12 @@
#include <string>
#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "mem/page_table.hh"
#include "sim/serialize.hh"
#include "sim/system.hh"
class System;
/**
* This class implements an in-memory multi-level page table that can be

View file

@ -32,18 +32,15 @@
* @file
* Definitions of page table
*/
#include <fstream>
#include <map>
#include <string>
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/MMU.hh"
#include "mem/multi_level_page_table.hh"
#include "sim/faults.hh"
#include "sim/sim_object.hh"
#include "mem/page_table.hh"
using namespace std;
using namespace TheISA;

View file

@ -37,18 +37,13 @@
*/
#include "mem/page_table.hh"
#include <fstream>
#include <map>
#include <memory>
#include <string>
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/MMU.hh"
#include "sim/faults.hh"
#include "sim/sim_object.hh"
#include "sim/serialize.hh"
using namespace std;
using namespace TheISA;

View file

@ -42,13 +42,14 @@
#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
#include "base/intmath.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "mem/request.hh"
#include "sim/serialize.hh"
#include "sim/system.hh"
class ThreadContext;
class System;
/**
* Declaration of base class for page table

View file

@ -41,6 +41,7 @@
#include <string>
#include <vector>
#include "base/trace.hh"
#include "debug/RubyQueue.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"

View file

@ -30,6 +30,8 @@
#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
#include "base/misc.hh"
AbstractReplacementPolicy::AbstractReplacementPolicy(const Params * p)
: SimObject(p)
{

View file

@ -45,9 +45,9 @@
#ifndef __MEM_SE_TRANSLATING_PORT_PROXY_HH__
#define __MEM_SE_TRANSLATING_PORT_PROXY_HH__
#include "mem/page_table.hh"
#include "mem/port_proxy.hh"
class PageTableBase;
class Process;
/**

View file

@ -45,6 +45,7 @@
#include "mem/simple_mem.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/Drain.hh"
using namespace std;

View file

@ -32,6 +32,7 @@
#include <Python.h>
#include "base/misc.hh"
#include "sim/async.hh"
#include "sim/eventq.hh"

View file

@ -82,6 +82,9 @@ if env['TARGET_ISA'] != 'null':
Source('syscall_emul.cc')
Source('syscall_desc.cc')
if env['TARGET_ISA'] != 'x86':
Source('microcode_rom.cc')
DebugFlag('Checkpoint')
DebugFlag('Config')
DebugFlag('CxxConfig')

View file

@ -32,7 +32,6 @@
#include "arch/utility.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
Arguments::Data::~Data()
{

View file

@ -34,7 +34,6 @@
#include <cassert>
#include <memory>
#include "base/types.hh"
#include "mem/fs_translating_port_proxy.hh"
class ThreadContext;

View file

@ -38,7 +38,6 @@
#define __SIM_BYTE_SWAP_HH__
#include "base/bigint.hh"
#include "base/misc.hh"
#include "base/types.hh"
// This lets us figure out what the byte order of the host system is

View file

@ -47,6 +47,7 @@
#include <algorithm>
#include <functional>
#include "base/trace.hh"
#include "debug/ClockDomain.hh"
#include "params/ClockDomain.hh"
#include "params/DerivedClockDomain.hh"

View file

@ -51,7 +51,6 @@
#include "base/callback.hh"
#include "base/intmath.hh"
#include "base/misc.hh"
#include "enums/PwrState.hh"
#include "params/ClockedObject.hh"
#include "sim/core.hh"

View file

@ -57,8 +57,6 @@
#include <string>
#include <vector>
#include "mem/port.hh"
#include "params/SimObject.hh"
#include "sim/sim_object.hh"
class CxxConfigParams;

View file

@ -39,6 +39,8 @@
#include "sim/cxx_config_ini.hh"
#include "base/str.hh"
bool
CxxIniFile::getParam(const std::string &object_name,
const std::string &param_name,

View file

@ -47,7 +47,6 @@
#define __SIM_CXX_CONFIG_INI_HH__
#include "base/inifile.hh"
#include "base/str.hh"
#include "sim/cxx_config.hh"
/** CxxConfigManager interface for using .ini files */

View file

@ -43,6 +43,7 @@
#include <sstream>
#include "base/str.hh"
#include "base/trace.hh"
#include "debug/CxxConfig.hh"
#include "mem/mem_object.hh"
#include "sim/serialize.hh"

View file

@ -44,8 +44,6 @@
#include <mutex>
#include <unordered_set>
#include "base/flags.hh"
class Drainable;
#ifndef SWIG // SWIG doesn't support strongly typed enums

View file

@ -45,9 +45,11 @@
#include <utility>
#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/DVFS.hh"
#include "params/DVFSHandler.hh"
#include "sim/clock_domain.hh"
#include "sim/eventq_impl.hh"
#include "sim/stat_control.hh"
#include "sim/voltage_domain.hh"
@ -170,6 +172,30 @@ DVFSHandler::UpdateEvent::updatePerfLevel()
d->perfLevel(perfLevelToSet);
}
double
DVFSHandler::voltageAtPerfLevel(DomainID domain_id, PerfLevel perf_level) const
{
VoltageDomain *d = findDomain(domain_id)->voltageDomain();
assert(d);
PerfLevel n = d->numVoltages();
if (perf_level < n)
return d->voltage(perf_level);
// Request outside of the range of the voltage domain
if (n == 1) {
DPRINTF(DVFS, "DVFS: Request for perf-level %i for single-point "\
"voltage domain %s. Returning voltage at level 0: %.2f "\
"V\n", perf_level, d->name(), d->voltage(0));
// Special case for single point voltage domain -> same voltage for
// all points
return d->voltage(0);
}
warn("DVFSHandler %s reads illegal voltage level %u from "\
"VoltageDomain %s. Returning 0 V\n", name(), perf_level, d->name());
return 0.;
}
void
DVFSHandler::serialize(CheckpointOut &cp) const
{

View file

@ -53,13 +53,10 @@
#include <vector>
#include "debug/DVFS.hh"
#include "params/ClockDomain.hh"
#include "params/DVFSHandler.hh"
#include "params/VoltageDomain.hh"
#include "sim/clock_domain.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
#include "sim/voltage_domain.hh"
/**
* DVFS Handler class, maintains a list of all the domains it can handle.
@ -156,28 +153,7 @@ class DVFSHandler : public SimObject
* @return Voltage for the requested performance level of the respective
* domain
*/
double voltageAtPerfLevel(DomainID domain_id, PerfLevel perf_level) const
{
VoltageDomain *d = findDomain(domain_id)->voltageDomain();
assert(d);
PerfLevel n = d->numVoltages();
if (perf_level < n)
return d->voltage(perf_level);
// Request outside of the range of the voltage domain
if (n == 1) {
DPRINTF(DVFS, "DVFS: Request for perf-level %i for single-point "\
"voltage domain %s. Returning voltage at level 0: %.2f "\
"V\n", perf_level, d->name(), d->voltage(0));
// Special case for single point voltage domain -> same voltage for
// all points
return d->voltage(0);
}
warn("DVFSHandler %s reads illegal voltage level %u from "\
"VoltageDomain %s. Returning 0 V\n", name(), perf_level, d->name());
return 0.;
}
double voltageAtPerfLevel(DomainID domain_id, PerfLevel perf_level) const;
/**
* Get the total number of available performance levels.

View file

@ -47,7 +47,6 @@
#include <string>
#include "base/flags.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "debug/Event.hh"
#include "sim/serialize.hh"

View file

@ -35,7 +35,9 @@
#include <ostream>
#include <string>
#include "sim/emul_driver.hh"
#include "sim/serialize.hh"
class EmulatedDriver;
/**
* FDEntry is used to manage a single file descriptor mapping and metadata

View file

@ -52,6 +52,7 @@
#include "base/atomicio.hh"
#include "base/cprintf.hh"
#include "base/misc.hh"
#include "sim/async.hh"
#include "sim/backtrace.hh"
#include "sim/core.hh"

View file

@ -45,9 +45,8 @@
#define __INSTRECORD_HH__
#include "base/bigint.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh" // for InstSeqNum
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
#include "sim/sim_object.hh"

40
src/sim/microcode_rom.cc Normal file
View file

@ -0,0 +1,40 @@
/*
* Copyright (c) 2008 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "sim/microcode_rom.hh"
#include "base/misc.hh"
#include "cpu/static_inst_fwd.hh"
StaticInstPtr
MicrocodeRom::fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop)
{
panic("ROM based microcode isn't implemented.\n");
}

View file

@ -36,17 +36,16 @@
* anything more.
*/
#include "base/misc.hh"
#include "cpu/static_inst.hh"
#include <inttypes.h>
#include "cpu/static_inst_fwd.hh"
typedef uint16_t MicroPC;
class MicrocodeRom
{
public:
StaticInstPtr
fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop)
{
panic("ROM based microcode isn't implemented.\n");
}
StaticInstPtr fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop);
};
#endif // __SIM_MICROCODE_ROM_HH__

View file

@ -42,11 +42,13 @@
#include <unordered_map>
#include "base/statistics.hh"
#include "params/MathExprPowerModel.hh"
#include "sim/mathexpr.hh"
#include "sim/power/power_model.hh"
#include "sim/sim_object.hh"
namespace Stats {
class Info;
}
/**
* A Equation power model. The power is represented as a combination

View file

@ -42,7 +42,7 @@
#include "base/statistics.hh"
#include "params/PowerModel.hh"
#include "params/PowerModelState.hh"
#include "sim/sim_object.hh"
#include "sim/clocked_object.hh"
#include "sim/sub_system.hh"
PowerModelState::PowerModelState(const Params *p)

View file

@ -43,9 +43,10 @@
#include "base/statistics.hh"
#include "params/PowerModel.hh"
#include "params/PowerModelState.hh"
#include "sim/power/thermal_model.hh"
#include "sim/probe/probe.hh"
#include "sim/sim_object.hh"
class SimObject;
class ClockedObject;
/**
* A PowerModelState is an abstract class used as interface to get power

View file

@ -44,8 +44,11 @@
#include "base/statistics.hh"
#include "debug/ThermalDomain.hh"
#include "params/ThermalDomain.hh"
#include "sim/clocked_object.hh"
#include "sim/linear_solver.hh"
#include "sim/power/thermal_model.hh"
#include "sim/sim_object.hh"
#include "sim/probe/probe.hh"
#include "sim/sub_system.hh"
ThermalDomain::ThermalDomain(const Params *p)
: SimObject(p), _initTemperature(p->initial_temperature),

View file

@ -45,11 +45,11 @@
#include "base/statistics.hh"
#include "params/ThermalDomain.hh"
#include "sim/power/thermal_entity.hh"
#include "sim/probe/probe.hh"
#include "sim/sim_object.hh"
#include "sim/sub_system.hh"
class SubSystem;
class ThermalNode;
template <class T> class ProbePointArg;
/**
* A ThermalDomain is used to group objects under that operate under

View file

@ -40,8 +40,7 @@
#ifndef __SIM_THERMAL_ENTITY_HH__
#define __SIM_THERMAL_ENTITY_HH__
#include "sim/linear_solver.hh"
class LinearEquation;
class ThermalNode;
/**

View file

@ -42,7 +42,6 @@
#include <vector>
#include "base/statistics.hh"
#include "params/ThermalCapacitor.hh"
#include "params/ThermalModel.hh"
#include "params/ThermalReference.hh"

View file

@ -40,6 +40,7 @@
#include "sim/probe/probe.hh"
#include "debug/ProbeVerbose.hh"
#include "params/ProbeListenerObject.hh"
ProbePoint::ProbePoint(ProbeManager *manager, const std::string& _name)
: name(_name)

View file

@ -64,13 +64,14 @@
#include <string>
#include <vector>
#include "base/compiler.hh"
#include "base/trace.hh"
#include "params/ProbeListenerObject.hh"
#include "sim/sim_object.hh"
/** Forward declare the ProbeManager. */
class ProbeManager;
class ProbeListener;
class ProbeListenerObjectParams;
/**
* Name space containing shared probe point declarations.

View file

@ -48,9 +48,10 @@
#include <fcntl.h>
#include <unistd.h>
#include <cstdio>
#include <array>
#include <map>
#include <string>
#include <vector>
#include "base/intmath.hh"
#include "base/loader/object_file.hh"
@ -58,14 +59,11 @@
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "mem/multi_level_page_table.hh"
#include "mem/page_table.hh"
#include "mem/se_translating_port_proxy.hh"
#include "params/LiveProcess.hh"
#include "params/Process.hh"
#include "sim/debug.hh"
#include "sim/process_impl.hh"
#include "sim/stats.hh"
#include "sim/emul_driver.hh"
#include "sim/syscall_desc.hh"
#include "sim/system.hh"

View file

@ -34,6 +34,7 @@
#define __PROCESS_HH__
#include <array>
#include <map>
#include <string>
#include <vector>
@ -44,15 +45,16 @@
#include "mem/se_translating_port_proxy.hh"
#include "sim/fd_entry.hh"
#include "sim/sim_object.hh"
#include "sim/syscall_return.hh"
class PageTable;
struct ProcessParams;
struct LiveProcessParams;
struct ProcessParams;
class EmulatedDriver;
class PageTableBase;
class SyscallDesc;
class SyscallReturn;
class System;
class ThreadContext;
class EmulatedDriver;
template<class IntType>
struct AuxVector

View file

@ -36,7 +36,6 @@
#include <vector>
#include "mem/se_translating_port_proxy.hh"
#include "sim/byteswap.hh"
//This needs to be templated for cases where 32 bit pointers are needed.
template<class AddrType>

View file

@ -31,13 +31,13 @@
* Gabe Black
*/
#include "sim/root.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/TimeSync.hh"
#include "sim/eventq_impl.hh"
#include "sim/full_system.hh"
#include "sim/root.hh"
Root *Root::_root = NULL;

View file

@ -59,14 +59,12 @@
#include <vector>
#include "base/bitunion.hh"
#include "base/types.hh"
class CheckpointIn;
class IniFile;
class Serializable;
class CheckpointIn;
class SimObject;
class SimObjectResolver;
class EventQueue;
typedef std::ostream CheckpointOut;

View file

@ -35,7 +35,8 @@
#include <string>
#include "base/types.hh"
#include "sim/core.hh"
Tick curTick();
// forward declaration
class Callback;

View file

@ -32,17 +32,11 @@
#include "sim/sim_object.hh"
#include <cassert>
#include "base/callback.hh"
#include "base/inifile.hh"
#include "base/match.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Checkpoint.hh"
#include "sim/probe/probe.hh"
#include "sim/stats.hh"
using namespace std;

View file

@ -49,21 +49,18 @@
#ifndef __SIM_OBJECT_HH__
#define __SIM_OBJECT_HH__
#include <iostream>
#include <list>
#include <map>
#include <string>
#include <vector>
#include "enums/MemoryMode.hh"
#include "params/SimObject.hh"
#include "sim/drain.hh"
#include "sim/eventq.hh"
#include "sim/eventq_impl.hh"
#include "sim/serialize.hh"
class BaseCPU;
class Event;
class EventManager;
class ProbeManager;
/**
* Abstract superclass for simulation objects. Represents things that
* correspond to physical components and can be specified via the

View file

@ -30,7 +30,8 @@
*/
#include "base/types.hh"
#include "sim/sim_events.hh"
class GlobalSimLoopExitEvent;
GlobalSimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
extern GlobalSimLoopExitEvent *simulate_limit_event;

View file

@ -39,6 +39,8 @@
#include "sim/stat_register.hh"
#include "base/statistics.hh"
namespace Stats
{

View file

@ -44,8 +44,6 @@
#ifndef __SIM_STAT_REGISTER_H__
#define __SIM_STAT_REGISTER_H__
#include "base/statistics.hh"
namespace Stats
{

View file

@ -48,7 +48,6 @@
#include <vector>
#include "params/SubSystem.hh"
#include "sim/power/thermal_domain.hh"
#include "sim/sim_object.hh"
class PowerModel;

View file

@ -34,7 +34,6 @@
#include <fcntl.h>
#include <unistd.h>
#include <cstdio>
#include <iostream>
#include <string>
@ -42,7 +41,6 @@
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"

View file

@ -62,7 +62,7 @@
/// application on the host machine.
#ifdef __CYGWIN32__
#include <sys/fcntl.h> // for O_BINARY
#include <sys/fcntl.h>
#endif
#include <fcntl.h>
@ -78,8 +78,7 @@
#include <cerrno>
#include <string>
#include "base/chunk_generator.hh"
#include "base/intmath.hh" // for RoundUp
#include "base/intmath.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "base/trace.hh"
@ -88,13 +87,11 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/emul_driver.hh"
#include "sim/process.hh"
#include "sim/syscall_debug_macros.hh"
#include "sim/syscall_emul_buf.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"
class SyscallDesc;
@ -156,7 +153,7 @@ SyscallReturn lseekFunc(SyscallDesc *desc, int num,
/// Target _llseek() handler.
SyscallReturn _llseekFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
LiveProcess *p, ThreadContext *tc);
/// Target munmap() handler.
SyscallReturn munmapFunc(SyscallDesc *desc, int num,
@ -236,39 +233,39 @@ SyscallReturn fcntlFunc(SyscallDesc *desc, int num,
/// Target fcntl64() handler.
SyscallReturn fcntl64Func(SyscallDesc *desc, int num,
LiveProcess *process, ThreadContext *tc);
LiveProcess *process, ThreadContext *tc);
/// Target setuid() handler.
SyscallReturn setuidFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
LiveProcess *p, ThreadContext *tc);
/// Target getpid() handler.
SyscallReturn getpidFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
LiveProcess *p, ThreadContext *tc);
/// Target getuid() handler.
SyscallReturn getuidFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
LiveProcess *p, ThreadContext *tc);
/// Target getgid() handler.
SyscallReturn getgidFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
LiveProcess *p, ThreadContext *tc);
/// Target getppid() handler.
SyscallReturn getppidFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
LiveProcess *p, ThreadContext *tc);
/// Target geteuid() handler.
SyscallReturn geteuidFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
LiveProcess *p, ThreadContext *tc);
/// Target getegid() handler.
SyscallReturn getegidFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
LiveProcess *p, ThreadContext *tc);
/// Target clone() handler.
SyscallReturn cloneFunc(SyscallDesc *desc, int num,
LiveProcess *p, ThreadContext *tc);
LiveProcess *p, ThreadContext *tc);
/// Target access() handler
SyscallReturn accessFunc(SyscallDesc *desc, int num,

Some files were not shown because too many files have changed in this diff Show more