a928a438b8
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include.
286 lines
9.7 KiB
C++
286 lines
9.7 KiB
C++
/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* Copyright (c) 2009 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/testers/rubytest/RubyTester.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "cpu/testers/rubytest/Check.hh"
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#include "debug/RubyTest.hh"
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#include "mem/ruby/common/SubBlock.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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RubyTester::RubyTester(const Params *p)
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: MemObject(p), checkStartEvent(this),
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_masterId(p->system->getMasterId(name())),
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m_checkTable_ptr(nullptr),
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m_num_cpus(p->num_cpus),
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m_checks_to_complete(p->checks_to_complete),
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m_deadlock_threshold(p->deadlock_threshold),
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m_num_writers(0),
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m_num_readers(0),
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m_wakeup_frequency(p->wakeup_frequency),
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m_check_flush(p->check_flush),
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m_num_inst_only_ports(p->port_cpuInstPort_connection_count),
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m_num_inst_data_ports(p->port_cpuInstDataPort_connection_count)
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{
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m_checks_completed = 0;
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//
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// Create the requested inst and data ports and place them on the
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// appropriate read and write port lists. The reason for the subtle
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// difference between inst and data ports vs. read and write ports is
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// from the tester's perspective, it only needs to know whether a port
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// supports reads (checks) or writes (actions). Meanwhile, the protocol
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// controllers have data ports (support read and writes) or inst ports
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// (support only reads).
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// Note: the inst ports are the lowest elements of the readPort vector,
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// then the data ports are added to the readPort vector
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//
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int idx = 0;
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for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
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readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
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this, i, idx));
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idx++;
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}
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for (int i = 0; i < p->port_cpuInstDataPort_connection_count; ++i) {
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CpuPort *port = new CpuPort(csprintf("%s-instDataPort%d", name(), i),
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this, i, idx);
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readPorts.push_back(port);
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writePorts.push_back(port);
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idx++;
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}
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for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
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CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i),
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this, i, idx);
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readPorts.push_back(port);
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writePorts.push_back(port);
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idx++;
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}
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// add the check start event to the event queue
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schedule(checkStartEvent, 1);
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}
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RubyTester::~RubyTester()
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{
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delete m_checkTable_ptr;
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// Only delete the readPorts since the writePorts are just a subset
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for (int i = 0; i < readPorts.size(); i++)
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delete readPorts[i];
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}
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void
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RubyTester::init()
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{
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assert(writePorts.size() > 0 && readPorts.size() > 0);
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m_last_progress_vector.resize(m_num_cpus);
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for (int i = 0; i < m_last_progress_vector.size(); i++) {
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m_last_progress_vector[i] = Cycles(0);
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}
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m_num_writers = writePorts.size();
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m_num_readers = readPorts.size();
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assert(m_num_readers == m_num_cpus);
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m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
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}
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BaseMasterPort &
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RubyTester::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" &&
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if_name != "cpuDataPort") {
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// pass it along to our super class
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return MemObject::getMasterPort(if_name, idx);
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} else {
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if (if_name == "cpuInstPort") {
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if (idx > m_num_inst_only_ports) {
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panic("RubyTester::getMasterPort: unknown inst port %d\n",
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idx);
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}
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//
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// inst ports map to the lowest readPort elements
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//
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return *readPorts[idx];
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} else if (if_name == "cpuInstDataPort") {
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if (idx > m_num_inst_data_ports) {
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panic("RubyTester::getMasterPort: unknown inst+data port %d\n",
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idx);
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}
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int read_idx = idx + m_num_inst_only_ports;
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//
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// inst+data ports map to the next readPort elements
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//
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return *readPorts[read_idx];
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} else {
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assert(if_name == "cpuDataPort");
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//
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// data only ports map to the final readPort elements
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//
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if (idx > (static_cast<int>(readPorts.size()) -
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(m_num_inst_only_ports + m_num_inst_data_ports))) {
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panic("RubyTester::getMasterPort: unknown data port %d\n",
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idx);
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}
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int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports;
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return *readPorts[read_idx];
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}
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// Note: currently the Ruby Tester does not support write only ports
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// but that could easily be added here
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}
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}
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bool
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RubyTester::CpuPort::recvTimingResp(PacketPtr pkt)
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{
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// retrieve the subblock and call hitCallback
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RubyTester::SenderState* senderState =
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safe_cast<RubyTester::SenderState*>(pkt->senderState);
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SubBlock& subblock = senderState->subBlock;
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tester->hitCallback(globalIdx, &subblock);
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// Now that the tester has completed, delete the senderState
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// (includes sublock) and the packet, then return
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delete pkt->senderState;
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delete pkt->req;
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delete pkt;
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return true;
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}
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bool
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RubyTester::isInstOnlyCpuPort(int idx)
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{
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return idx < m_num_inst_only_ports;
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}
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bool
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RubyTester::isInstDataCpuPort(int idx)
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{
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return ((idx >= m_num_inst_only_ports) &&
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(idx < (m_num_inst_only_ports + m_num_inst_data_ports)));
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}
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MasterPort*
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RubyTester::getReadableCpuPort(int idx)
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{
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assert(idx >= 0 && idx < readPorts.size());
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return readPorts[idx];
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}
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MasterPort*
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RubyTester::getWritableCpuPort(int idx)
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{
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assert(idx >= 0 && idx < writePorts.size());
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return writePorts[idx];
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}
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void
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RubyTester::hitCallback(NodeID proc, SubBlock* data)
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{
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// Mark that we made progress
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m_last_progress_vector[proc] = curCycle();
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DPRINTF(RubyTest, "completed request for proc: %d", proc);
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DPRINTFR(RubyTest, " addr: 0x%x, size: %d, data: ",
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data->getAddress(), data->getSize());
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for (int byte = 0; byte < data->getSize(); byte++) {
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DPRINTFR(RubyTest, "%d ", data->getByte(byte));
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}
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DPRINTFR(RubyTest, "\n");
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// This tells us our store has 'completed' or for a load gives us
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// back the data to make the check
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Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress());
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assert(check_ptr != NULL);
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check_ptr->performCallback(proc, data, curCycle());
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}
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void
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RubyTester::wakeup()
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{
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if (m_checks_completed < m_checks_to_complete) {
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// Try to perform an action or check
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Check* check_ptr = m_checkTable_ptr->getRandomCheck();
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assert(check_ptr != NULL);
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check_ptr->initiate();
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checkForDeadlock();
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schedule(checkStartEvent, curTick() + m_wakeup_frequency);
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} else {
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exitSimLoop("Ruby Tester completed");
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}
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}
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void
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RubyTester::checkForDeadlock()
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{
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int size = m_last_progress_vector.size();
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Cycles current_time = curCycle();
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for (int processor = 0; processor < size; processor++) {
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if ((current_time - m_last_progress_vector[processor]) >
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m_deadlock_threshold) {
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panic("Deadlock detected: current_time: %d last_progress_time: %d "
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"difference: %d processor: %d\n",
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current_time, m_last_progress_vector[processor],
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current_time - m_last_progress_vector[processor], processor);
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}
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}
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}
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void
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RubyTester::print(std::ostream& out) const
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{
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out << "[RubyTester]" << std::endl;
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}
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RubyTester *
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RubyTesterParams::create()
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{
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return new RubyTester(this);
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}
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