a928a438b8
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include.
108 lines
2.9 KiB
C++
108 lines
2.9 KiB
C++
/*
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* Copyright (c) 2011 Google
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_RISCV_INTERRUPT_HH__
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#define __ARCH_RISCV_INTERRUPT_HH__
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#include "base/misc.hh"
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#include "params/RiscvInterrupts.hh"
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#include "sim/sim_object.hh"
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class BaseCPU;
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class ThreadContext;
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namespace RiscvISA {
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class Interrupts : public SimObject
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{
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private:
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BaseCPU * cpu;
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public:
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typedef RiscvInterruptsParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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Interrupts(Params * p) : SimObject(p), cpu(nullptr)
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{}
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void
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setCPU(BaseCPU * _cpu)
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{
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cpu = _cpu;
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}
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void
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post(int int_num, int index)
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{
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panic("Interrupts::post not implemented.\n");
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}
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void
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clear(int int_num, int index)
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{
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panic("Interrupts::clear not implemented.\n");
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}
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void
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clearAll()
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{
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panic("Interrupts::clearAll not implemented.\n");
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}
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bool
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checkInterrupts(ThreadContext *tc) const
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{
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panic("Interrupts::checkInterrupts not implemented.\n");
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}
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Fault
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getInterrupt(ThreadContext *tc)
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{
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assert(checkInterrupts(tc));
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panic("Interrupts::getInterrupt not implemented.\n");
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}
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void
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updateIntrInfo(ThreadContext *tc)
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{
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panic("Interrupts::updateIntrInfo not implemented.\n");
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}
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};
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} // namespace RiscvISA
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#endif // __ARCH_RISCV_INTERRUPT_HH__
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