a928a438b8
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include.
500 lines
17 KiB
C++
500 lines
17 KiB
C++
/*
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* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/tlb.hh"
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#include <cstring>
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#include <memory>
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#include "arch/generic/mmapped_ipr.hh"
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#include "arch/x86/faults.hh"
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#include "arch/x86/insts/microldstop.hh"
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#include "arch/x86/pagetable_walker.hh"
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#include "arch/x86/regs/misc.hh"
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#include "arch/x86/regs/msr.hh"
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#include "arch/x86/x86_traits.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "debug/TLB.hh"
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#include "mem/page_table.hh"
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#include "mem/request.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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namespace X86ISA {
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TLB::TLB(const Params *p)
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: BaseTLB(p), configAddress(0), size(p->size),
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tlb(size), lruSeq(0)
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{
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if (!size)
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fatal("TLBs must have a non-zero size.\n");
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for (int x = 0; x < size; x++) {
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tlb[x].trieHandle = NULL;
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freeList.push_back(&tlb[x]);
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}
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walker = p->walker;
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walker->setTLB(this);
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}
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void
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TLB::evictLRU()
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{
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// Find the entry with the lowest (and hence least recently updated)
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// sequence number.
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unsigned lru = 0;
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for (unsigned i = 1; i < size; i++) {
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if (tlb[i].lruSeq < tlb[lru].lruSeq)
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lru = i;
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}
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assert(tlb[lru].trieHandle);
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trie.remove(tlb[lru].trieHandle);
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tlb[lru].trieHandle = NULL;
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freeList.push_back(&tlb[lru]);
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}
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TlbEntry *
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TLB::insert(Addr vpn, TlbEntry &entry)
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{
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// If somebody beat us to it, just use that existing entry.
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TlbEntry *newEntry = trie.lookup(vpn);
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if (newEntry) {
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assert(newEntry->vaddr == vpn);
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return newEntry;
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}
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if (freeList.empty())
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evictLRU();
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newEntry = freeList.front();
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freeList.pop_front();
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*newEntry = entry;
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newEntry->lruSeq = nextSeq();
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newEntry->vaddr = vpn;
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newEntry->trieHandle =
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trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
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return newEntry;
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}
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TlbEntry *
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TLB::lookup(Addr va, bool update_lru)
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{
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TlbEntry *entry = trie.lookup(va);
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if (entry && update_lru)
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entry->lruSeq = nextSeq();
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return entry;
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}
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void
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TLB::flushAll()
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{
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DPRINTF(TLB, "Invalidating all entries.\n");
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for (unsigned i = 0; i < size; i++) {
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if (tlb[i].trieHandle) {
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trie.remove(tlb[i].trieHandle);
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tlb[i].trieHandle = NULL;
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freeList.push_back(&tlb[i]);
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}
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}
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}
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void
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TLB::setConfigAddress(uint32_t addr)
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{
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configAddress = addr;
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}
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void
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TLB::flushNonGlobal()
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{
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DPRINTF(TLB, "Invalidating all non global entries.\n");
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for (unsigned i = 0; i < size; i++) {
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if (tlb[i].trieHandle && !tlb[i].global) {
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trie.remove(tlb[i].trieHandle);
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tlb[i].trieHandle = NULL;
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freeList.push_back(&tlb[i]);
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}
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}
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}
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void
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TLB::demapPage(Addr va, uint64_t asn)
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{
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TlbEntry *entry = trie.lookup(va);
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if (entry) {
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trie.remove(entry->trieHandle);
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entry->trieHandle = NULL;
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freeList.push_back(entry);
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}
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}
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Fault
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TLB::translateInt(RequestPtr req, ThreadContext *tc)
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{
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DPRINTF(TLB, "Addresses references internal memory.\n");
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Addr vaddr = req->getVaddr();
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Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
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if (prefix == IntAddrPrefixCPUID) {
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panic("CPUID memory space not yet implemented!\n");
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} else if (prefix == IntAddrPrefixMSR) {
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vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
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req->setFlags(Request::MMAPPED_IPR);
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MiscRegIndex regNum;
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if (!msrAddrToIndex(regNum, vaddr))
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return std::make_shared<GeneralProtection>(0);
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//The index is multiplied by the size of a MiscReg so that
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//any memory dependence calculations will not see these as
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//overlapping.
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req->setPaddr((Addr)regNum * sizeof(MiscReg));
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return NoFault;
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} else if (prefix == IntAddrPrefixIO) {
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// TODO If CPL > IOPL or in virtual mode, check the I/O permission
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// bitmap in the TSS.
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Addr IOPort = vaddr & ~IntAddrPrefixMask;
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// Make sure the address fits in the expected 16 bit IO address
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// space.
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assert(!(IOPort & ~0xFFFF));
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if (IOPort == 0xCF8 && req->getSize() == 4) {
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req->setFlags(Request::MMAPPED_IPR);
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req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
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} else if ((IOPort & ~mask(2)) == 0xCFC) {
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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Addr configAddress =
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tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
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if (bits(configAddress, 31, 31)) {
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req->setPaddr(PhysAddrPrefixPciConfig |
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mbits(configAddress, 30, 2) |
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(IOPort & mask(2)));
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} else {
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req->setPaddr(PhysAddrPrefixIO | IOPort);
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}
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} else {
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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req->setPaddr(PhysAddrPrefixIO | IOPort);
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}
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return NoFault;
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} else {
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panic("Access to unrecognized internal address space %#x.\n",
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prefix);
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}
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}
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Fault
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TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
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{
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Addr paddr = req->getPaddr();
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AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
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if (m5opRange.contains(paddr)) {
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if (m5opRange.contains(paddr)) {
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req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
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Request::STRICT_ORDER);
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req->setPaddr(GenericISA::iprAddressPseudoInst(
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(paddr >> 8) & 0xFF,
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paddr & 0xFF));
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}
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} else if (FullSystem) {
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// Check for an access to the local APIC
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LocalApicBase localApicBase =
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tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
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AddrRange apicRange(localApicBase.base * PageBytes,
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(localApicBase.base + 1) * PageBytes - 1);
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if (apicRange.contains(paddr)) {
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// The Intel developer's manuals say the below restrictions apply,
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// but the linux kernel, because of a compiler optimization, breaks
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// them.
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/*
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// Check alignment
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if (paddr & ((32/8) - 1))
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return new GeneralProtection(0);
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// Check access size
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if (req->getSize() != (32/8))
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return new GeneralProtection(0);
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*/
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// Force the access to be uncacheable.
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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req->setPaddr(x86LocalAPICAddress(tc->contextId(),
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paddr - apicRange.start()));
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}
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}
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return NoFault;
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}
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Fault
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TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
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Mode mode, bool &delayedResponse, bool timing)
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{
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Request::Flags flags = req->getFlags();
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int seg = flags & SegmentFlagMask;
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bool storeCheck = flags & (StoreCheck << FlagShift);
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delayedResponse = false;
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// If this is true, we're dealing with a request to a non-memory address
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// space.
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if (seg == SEGMENT_REG_MS) {
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return translateInt(req, tc);
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}
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Addr vaddr = req->getVaddr();
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DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
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HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
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// If protected mode has been enabled...
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if (m5Reg.prot) {
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DPRINTF(TLB, "In protected mode.\n");
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// If we're not in 64-bit mode, do protection/limit checks
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if (m5Reg.mode != LongMode) {
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DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
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// Check for a NULL segment selector.
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if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
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seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
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&& !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
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return std::make_shared<GeneralProtection>(0);
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bool expandDown = false;
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SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
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if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
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if (!attr.writable && (mode == Write || storeCheck))
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return std::make_shared<GeneralProtection>(0);
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if (!attr.readable && mode == Read)
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return std::make_shared<GeneralProtection>(0);
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expandDown = attr.expandDown;
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}
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Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
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Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
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bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
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unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr
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: (unsigned)m5Reg.defAddr;
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int size = (1 << logSize) * 8;
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Addr offset = bits(vaddr - base, size - 1, 0);
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Addr endOffset = offset + req->getSize() - 1;
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if (expandDown) {
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DPRINTF(TLB, "Checking an expand down segment.\n");
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warn_once("Expand down segments are untested.\n");
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if (offset <= limit || endOffset <= limit)
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return std::make_shared<GeneralProtection>(0);
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} else {
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if (offset > limit || endOffset > limit)
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return std::make_shared<GeneralProtection>(0);
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}
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}
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if (m5Reg.submode != SixtyFourBitMode ||
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(flags & (AddrSizeFlagBit << FlagShift)))
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vaddr &= mask(32);
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// If paging is enabled, do the translation.
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if (m5Reg.paging) {
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DPRINTF(TLB, "Paging enabled.\n");
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// The vaddr already has the segment base applied.
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TlbEntry *entry = lookup(vaddr);
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if (!entry) {
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if (FullSystem) {
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Fault fault = walker->start(tc, translation, req, mode);
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if (timing || fault != NoFault) {
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// This gets ignored in atomic mode.
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delayedResponse = true;
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return fault;
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}
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entry = lookup(vaddr);
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assert(entry);
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} else {
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DPRINTF(TLB, "Handling a TLB miss for "
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"address %#x at pc %#x.\n",
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vaddr, tc->instAddr());
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Process *p = tc->getProcessPtr();
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TlbEntry newEntry;
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bool success = p->pTable->lookup(vaddr, newEntry);
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if (!success && mode != Execute) {
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// Check if we just need to grow the stack.
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if (p->fixupStackFault(vaddr)) {
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// If we did, lookup the entry for the new page.
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success = p->pTable->lookup(vaddr, newEntry);
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}
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}
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if (!success) {
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return std::make_shared<PageFault>(vaddr, true, mode,
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true, false);
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} else {
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Addr alignedVaddr = p->pTable->pageAlign(vaddr);
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DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
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newEntry.pageStart());
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entry = insert(alignedVaddr, newEntry);
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}
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DPRINTF(TLB, "Miss was serviced.\n");
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}
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}
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DPRINTF(TLB, "Entry found with paddr %#x, "
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"doing protection checks.\n", entry->paddr);
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// Do paging protection checks.
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bool inUser = (m5Reg.cpl == 3 &&
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!(flags & (CPL0FlagBit << FlagShift)));
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CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
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bool badWrite = (!entry->writable && (inUser || cr0.wp));
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if ((inUser && !entry->user) || (mode == Write && badWrite)) {
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// The page must have been present to get into the TLB in
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// the first place. We'll assume the reserved bits are
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// fine even though we're not checking them.
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return std::make_shared<PageFault>(vaddr, true, mode, inUser,
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false);
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}
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if (storeCheck && badWrite) {
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// This would fault if this were a write, so return a page
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// fault that reflects that happening.
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return std::make_shared<PageFault>(vaddr, true, Write, inUser,
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false);
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}
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Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
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DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
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req->setPaddr(paddr);
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if (entry->uncacheable)
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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} else {
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//Use the address which already has segmentation applied.
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DPRINTF(TLB, "Paging disabled.\n");
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DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
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req->setPaddr(vaddr);
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}
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} else {
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// Real mode
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DPRINTF(TLB, "In real mode.\n");
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DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
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req->setPaddr(vaddr);
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}
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return finalizePhysical(req, tc, mode);
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}
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Fault
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TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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bool delayedResponse;
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return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
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}
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void
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TLB::translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode)
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{
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bool delayedResponse;
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assert(translation);
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Fault fault =
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TLB::translate(req, tc, translation, mode, delayedResponse, true);
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if (!delayedResponse)
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translation->finish(fault, req, tc, mode);
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}
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Fault
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TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
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{
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panic("Not implemented\n");
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return NoFault;
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}
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Walker *
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TLB::getWalker()
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{
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return walker;
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}
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void
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TLB::serialize(CheckpointOut &cp) const
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{
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// Only store the entries in use.
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uint32_t _size = size - freeList.size();
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SERIALIZE_SCALAR(_size);
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SERIALIZE_SCALAR(lruSeq);
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uint32_t _count = 0;
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for (uint32_t x = 0; x < size; x++) {
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if (tlb[x].trieHandle != NULL)
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tlb[x].serializeSection(cp, csprintf("Entry%d", _count++));
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}
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}
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void
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TLB::unserialize(CheckpointIn &cp)
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{
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// Do not allow to restore with a smaller tlb.
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uint32_t _size;
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UNSERIALIZE_SCALAR(_size);
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if (_size > size) {
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fatal("TLB size less than the one in checkpoint!");
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}
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UNSERIALIZE_SCALAR(lruSeq);
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for (uint32_t x = 0; x < _size; x++) {
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TlbEntry *newEntry = freeList.front();
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freeList.pop_front();
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newEntry->unserializeSection(cp, csprintf("Entry%d", x));
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newEntry->trieHandle = trie.insert(newEntry->vaddr,
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TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
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}
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}
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BaseMasterPort *
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TLB::getMasterPort()
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{
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return &walker->getMasterPort("port");
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}
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} // namespace X86ISA
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X86ISA::TLB *
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X86TLBParams::create()
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{
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return new X86ISA::TLB(this);
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}
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