2007-08-27 05:24:18 +02:00
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/*
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2008-06-12 06:46:22 +02:00
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* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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2007-08-27 05:24:18 +02:00
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* All rights reserved.
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*
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2010-05-24 07:44:15 +02:00
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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2007-08-27 05:24:18 +02:00
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*
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2010-05-24 07:44:15 +02:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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2007-08-27 05:24:18 +02:00
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* contributors may be used to endorse or promote products derived from
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2010-05-24 07:44:15 +02:00
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* this software without specific prior written permission.
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2007-08-27 05:24:18 +02:00
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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2016-11-09 21:27:37 +01:00
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#include "arch/x86/tlb.hh"
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2007-08-27 05:24:18 +02:00
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#include <cstring>
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2014-10-16 11:49:51 +02:00
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#include <memory>
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2007-08-27 05:24:18 +02:00
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2013-09-30 12:20:53 +02:00
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#include "arch/generic/mmapped_ipr.hh"
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2011-04-15 19:44:06 +02:00
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#include "arch/x86/faults.hh"
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2016-11-09 21:27:37 +01:00
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#include "arch/x86/insts/microldstop.hh"
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2011-10-13 11:22:23 +02:00
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#include "arch/x86/pagetable_walker.hh"
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2016-11-09 21:27:37 +01:00
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#include "arch/x86/regs/misc.hh"
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#include "arch/x86/regs/msr.hh"
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2007-10-13 01:37:55 +02:00
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#include "arch/x86/x86_traits.hh"
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2007-09-25 02:39:56 +02:00
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#include "base/trace.hh"
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2011-04-15 19:44:06 +02:00
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#include "cpu/thread_context.hh"
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2011-04-15 19:44:32 +02:00
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#include "debug/TLB.hh"
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2009-02-25 19:16:21 +01:00
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#include "mem/page_table.hh"
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2011-10-30 08:33:02 +01:00
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#include "mem/request.hh"
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2011-10-13 11:22:23 +02:00
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#include "sim/full_system.hh"
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2011-10-30 08:33:02 +01:00
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#include "sim/process.hh"
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2011-10-13 11:22:23 +02:00
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2007-11-13 03:06:57 +01:00
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namespace X86ISA {
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2015-07-07 10:51:03 +02:00
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TLB::TLB(const Params *p)
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: BaseTLB(p), configAddress(0), size(p->size),
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tlb(size), lruSeq(0)
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2007-10-03 08:00:37 +02:00
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{
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2012-04-15 08:24:18 +02:00
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if (!size)
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fatal("TLBs must have a non-zero size.\n");
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2007-10-03 08:00:37 +02:00
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2012-04-15 08:24:18 +02:00
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for (int x = 0; x < size; x++) {
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tlb[x].trieHandle = NULL;
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2007-10-03 08:00:37 +02:00
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freeList.push_back(&tlb[x]);
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2012-04-15 08:24:18 +02:00
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}
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2007-10-03 08:00:37 +02:00
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2007-11-13 03:06:57 +01:00
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walker = p->walker;
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walker->setTLB(this);
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}
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2007-11-12 23:38:31 +01:00
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2012-04-15 08:24:18 +02:00
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void
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TLB::evictLRU()
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{
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// Find the entry with the lowest (and hence least recently updated)
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// sequence number.
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unsigned lru = 0;
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for (unsigned i = 1; i < size; i++) {
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if (tlb[i].lruSeq < tlb[lru].lruSeq)
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lru = i;
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}
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assert(tlb[lru].trieHandle);
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trie.remove(tlb[lru].trieHandle);
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tlb[lru].trieHandle = NULL;
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freeList.push_back(&tlb[lru]);
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}
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2009-02-25 19:16:21 +01:00
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TlbEntry *
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2007-10-03 08:00:37 +02:00
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TLB::insert(Addr vpn, TlbEntry &entry)
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{
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2012-04-24 09:48:41 +02:00
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// If somebody beat us to it, just use that existing entry.
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TlbEntry *newEntry = trie.lookup(vpn);
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if (newEntry) {
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2012-06-08 00:03:45 +02:00
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assert(newEntry->vaddr == vpn);
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2012-04-24 09:48:41 +02:00
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return newEntry;
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}
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2007-10-03 08:00:37 +02:00
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2012-04-15 08:24:18 +02:00
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if (freeList.empty())
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evictLRU();
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2012-04-24 09:48:41 +02:00
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2012-04-15 08:24:18 +02:00
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newEntry = freeList.front();
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freeList.pop_front();
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2007-10-03 08:00:37 +02:00
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*newEntry = entry;
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2012-04-15 08:24:18 +02:00
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newEntry->lruSeq = nextSeq();
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2007-10-03 08:00:37 +02:00
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newEntry->vaddr = vpn;
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2012-04-15 08:24:18 +02:00
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newEntry->trieHandle =
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2012-04-24 09:48:41 +02:00
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trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry);
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2009-02-25 19:16:21 +01:00
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return newEntry;
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2007-10-03 08:00:37 +02:00
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}
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2008-02-27 05:39:53 +01:00
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TlbEntry *
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TLB::lookup(Addr va, bool update_lru)
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{
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2012-04-15 08:24:18 +02:00
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TlbEntry *entry = trie.lookup(va);
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if (entry && update_lru)
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entry->lruSeq = nextSeq();
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return entry;
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2007-10-03 08:00:37 +02:00
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}
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void
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2013-01-07 19:05:40 +01:00
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TLB::flushAll()
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2007-10-03 08:00:37 +02:00
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{
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2007-11-12 23:39:07 +01:00
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DPRINTF(TLB, "Invalidating all entries.\n");
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2012-04-15 08:24:18 +02:00
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for (unsigned i = 0; i < size; i++) {
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if (tlb[i].trieHandle) {
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trie.remove(tlb[i].trieHandle);
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tlb[i].trieHandle = NULL;
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freeList.push_back(&tlb[i]);
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}
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2007-11-12 23:39:07 +01:00
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}
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2007-10-03 08:00:37 +02:00
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}
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2008-02-27 05:38:01 +01:00
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void
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TLB::setConfigAddress(uint32_t addr)
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{
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configAddress = addr;
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}
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2007-10-03 08:00:37 +02:00
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void
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2013-01-07 19:05:40 +01:00
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TLB::flushNonGlobal()
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2007-10-03 08:00:37 +02:00
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{
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2007-11-12 23:39:07 +01:00
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DPRINTF(TLB, "Invalidating all non global entries.\n");
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2012-04-15 08:24:18 +02:00
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for (unsigned i = 0; i < size; i++) {
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if (tlb[i].trieHandle && !tlb[i].global) {
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trie.remove(tlb[i].trieHandle);
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tlb[i].trieHandle = NULL;
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freeList.push_back(&tlb[i]);
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2007-11-12 23:39:07 +01:00
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}
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}
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2007-10-03 08:00:37 +02:00
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}
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void
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2008-02-27 05:38:51 +01:00
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TLB::demapPage(Addr va, uint64_t asn)
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2007-09-25 02:39:56 +02:00
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{
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2012-04-15 08:24:18 +02:00
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TlbEntry *entry = trie.lookup(va);
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if (entry) {
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trie.remove(entry->trieHandle);
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entry->trieHandle = NULL;
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freeList.push_back(entry);
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2008-02-27 05:39:22 +01:00
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}
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2007-09-25 02:39:56 +02:00
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}
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Fault
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2009-04-27 01:48:44 +02:00
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TLB::translateInt(RequestPtr req, ThreadContext *tc)
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2007-09-25 02:39:56 +02:00
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{
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2009-04-27 01:48:44 +02:00
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DPRINTF(TLB, "Addresses references internal memory.\n");
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2007-10-03 08:00:37 +02:00
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Addr vaddr = req->getVaddr();
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2009-04-27 01:48:44 +02:00
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Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
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if (prefix == IntAddrPrefixCPUID) {
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panic("CPUID memory space not yet implemented!\n");
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} else if (prefix == IntAddrPrefixMSR) {
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2011-09-23 11:42:22 +02:00
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vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
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2011-03-02 08:18:47 +01:00
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req->setFlags(Request::MMAPPED_IPR);
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2011-09-23 11:42:22 +02:00
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MiscRegIndex regNum;
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if (!msrAddrToIndex(regNum, vaddr))
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2014-10-16 11:49:51 +02:00
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return std::make_shared<GeneralProtection>(0);
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2011-09-23 11:42:22 +02:00
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2009-04-27 01:48:44 +02:00
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//The index is multiplied by the size of a MiscReg so that
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//any memory dependence calculations will not see these as
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//overlapping.
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2011-09-23 11:42:22 +02:00
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req->setPaddr((Addr)regNum * sizeof(MiscReg));
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2009-04-27 01:48:44 +02:00
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return NoFault;
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} else if (prefix == IntAddrPrefixIO) {
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// TODO If CPL > IOPL or in virtual mode, check the I/O permission
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// bitmap in the TSS.
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2007-10-03 08:00:37 +02:00
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2009-04-27 01:48:44 +02:00
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Addr IOPort = vaddr & ~IntAddrPrefixMask;
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// Make sure the address fits in the expected 16 bit IO address
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// space.
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assert(!(IOPort & ~0xFFFF));
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if (IOPort == 0xCF8 && req->getSize() == 4) {
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2011-03-02 08:18:47 +01:00
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req->setFlags(Request::MMAPPED_IPR);
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2009-04-27 01:48:44 +02:00
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req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
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} else if ((IOPort & ~mask(2)) == 0xCFC) {
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2015-05-05 09:22:33 +02:00
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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2009-04-27 01:48:44 +02:00
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Addr configAddress =
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tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
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if (bits(configAddress, 31, 31)) {
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req->setPaddr(PhysAddrPrefixPciConfig |
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mbits(configAddress, 30, 2) |
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(IOPort & mask(2)));
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2011-02-28 01:25:06 +01:00
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} else {
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req->setPaddr(PhysAddrPrefixIO | IOPort);
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2008-02-27 05:38:01 +01:00
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}
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2007-10-13 01:37:55 +02:00
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} else {
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2015-05-05 09:22:33 +02:00
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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2009-04-27 01:48:44 +02:00
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req->setPaddr(PhysAddrPrefixIO | IOPort);
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2007-10-13 01:37:55 +02:00
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}
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2009-04-27 01:48:44 +02:00
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return NoFault;
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} else {
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panic("Access to unrecognized internal address space %#x.\n",
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prefix);
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2007-10-13 01:37:55 +02:00
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}
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2009-04-27 01:48:44 +02:00
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}
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2013-06-03 13:55:41 +02:00
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Fault
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TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
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{
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Addr paddr = req->getPaddr();
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2014-11-24 03:01:08 +01:00
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AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
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if (m5opRange.contains(paddr)) {
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if (m5opRange.contains(paddr)) {
|
2016-09-14 05:18:34 +02:00
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req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
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Request::STRICT_ORDER);
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2014-11-24 03:01:08 +01:00
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req->setPaddr(GenericISA::iprAddressPseudoInst(
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(paddr >> 8) & 0xFF,
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paddr & 0xFF));
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}
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} else if (FullSystem) {
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// Check for an access to the local APIC
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2013-06-03 13:55:41 +02:00
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LocalApicBase localApicBase =
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tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
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AddrRange apicRange(localApicBase.base * PageBytes,
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(localApicBase.base + 1) * PageBytes - 1);
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if (apicRange.contains(paddr)) {
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// The Intel developer's manuals say the below restrictions apply,
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// but the linux kernel, because of a compiler optimization, breaks
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// them.
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/*
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// Check alignment
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if (paddr & ((32/8) - 1))
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return new GeneralProtection(0);
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// Check access size
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if (req->getSize() != (32/8))
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return new GeneralProtection(0);
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*/
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// Force the access to be uncacheable.
|
2015-05-05 09:22:33 +02:00
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
|
2013-06-03 13:55:41 +02:00
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req->setPaddr(x86LocalAPICAddress(tc->contextId(),
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paddr - apicRange.start()));
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}
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}
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return NoFault;
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}
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|
2009-04-27 01:48:44 +02:00
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Fault
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TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
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Mode mode, bool &delayedResponse, bool timing)
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{
|
2016-08-15 13:00:35 +02:00
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|
Request::Flags flags = req->getFlags();
|
2009-04-27 01:48:44 +02:00
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int seg = flags & SegmentFlagMask;
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bool storeCheck = flags & (StoreCheck << FlagShift);
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|
2011-09-05 11:48:57 +02:00
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delayedResponse = false;
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2009-04-27 01:48:44 +02:00
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// If this is true, we're dealing with a request to a non-memory address
|
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// space.
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|
if (seg == SEGMENT_REG_MS) {
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|
return translateInt(req, tc);
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}
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|
|
Addr vaddr = req->getVaddr();
|
|
|
|
DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
|
2007-10-03 08:00:37 +02:00
|
|
|
|
2009-04-27 01:48:44 +02:00
|
|
|
HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
|
2007-10-08 03:18:39 +02:00
|
|
|
|
|
|
|
// If protected mode has been enabled...
|
2009-04-27 01:48:44 +02:00
|
|
|
if (m5Reg.prot) {
|
2007-11-12 23:38:31 +01:00
|
|
|
DPRINTF(TLB, "In protected mode.\n");
|
2007-10-08 03:18:39 +02:00
|
|
|
// If we're not in 64-bit mode, do protection/limit checks
|
2009-04-27 01:48:44 +02:00
|
|
|
if (m5Reg.mode != LongMode) {
|
2007-11-12 23:38:31 +01:00
|
|
|
DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
|
2008-06-12 06:51:50 +02:00
|
|
|
// Check for a NULL segment selector.
|
2009-04-19 12:41:10 +02:00
|
|
|
if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
|
2009-04-27 01:48:44 +02:00
|
|
|
seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
|
2009-04-19 12:41:10 +02:00
|
|
|
&& !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<GeneralProtection>(0);
|
2008-06-12 06:52:12 +02:00
|
|
|
bool expandDown = false;
|
2009-02-27 18:23:50 +01:00
|
|
|
SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
|
2008-06-12 06:52:12 +02:00
|
|
|
if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
|
2009-04-19 13:57:51 +02:00
|
|
|
if (!attr.writable && (mode == Write || storeCheck))
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<GeneralProtection>(0);
|
2009-04-09 07:21:27 +02:00
|
|
|
if (!attr.readable && mode == Read)
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<GeneralProtection>(0);
|
2008-06-12 06:52:12 +02:00
|
|
|
expandDown = attr.expandDown;
|
2009-02-27 18:23:50 +01:00
|
|
|
|
2008-06-12 06:52:12 +02:00
|
|
|
}
|
2007-10-08 03:18:39 +02:00
|
|
|
Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
|
|
|
|
Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
|
2009-02-27 18:23:50 +01:00
|
|
|
bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
|
2012-06-07 15:11:00 +02:00
|
|
|
unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr
|
|
|
|
: (unsigned)m5Reg.defAddr;
|
2012-05-29 06:56:23 +02:00
|
|
|
int size = (1 << logSize) * 8;
|
|
|
|
Addr offset = bits(vaddr - base, size - 1, 0);
|
2009-02-27 18:23:50 +01:00
|
|
|
Addr endOffset = offset + req->getSize() - 1;
|
2008-06-12 06:52:12 +02:00
|
|
|
if (expandDown) {
|
2007-11-12 23:38:31 +01:00
|
|
|
DPRINTF(TLB, "Checking an expand down segment.\n");
|
2009-02-27 18:23:50 +01:00
|
|
|
warn_once("Expand down segments are untested.\n");
|
|
|
|
if (offset <= limit || endOffset <= limit)
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<GeneralProtection>(0);
|
2007-10-08 03:18:39 +02:00
|
|
|
} else {
|
2009-02-27 18:23:50 +01:00
|
|
|
if (offset > limit || endOffset > limit)
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<GeneralProtection>(0);
|
2007-10-08 03:18:39 +02:00
|
|
|
}
|
|
|
|
}
|
2012-05-28 04:01:04 +02:00
|
|
|
if (m5Reg.submode != SixtyFourBitMode ||
|
2012-03-31 21:27:33 +02:00
|
|
|
(flags & (AddrSizeFlagBit << FlagShift)))
|
|
|
|
vaddr &= mask(32);
|
2007-10-08 03:18:39 +02:00
|
|
|
// If paging is enabled, do the translation.
|
2009-04-27 01:48:44 +02:00
|
|
|
if (m5Reg.paging) {
|
2007-11-12 23:38:31 +01:00
|
|
|
DPRINTF(TLB, "Paging enabled.\n");
|
2007-10-08 03:18:39 +02:00
|
|
|
// The vaddr already has the segment base applied.
|
|
|
|
TlbEntry *entry = lookup(vaddr);
|
|
|
|
if (!entry) {
|
2011-10-13 11:22:23 +02:00
|
|
|
if (FullSystem) {
|
|
|
|
Fault fault = walker->start(tc, translation, req, mode);
|
|
|
|
if (timing || fault != NoFault) {
|
|
|
|
// This gets ignored in atomic mode.
|
|
|
|
delayedResponse = true;
|
|
|
|
return fault;
|
2011-09-09 10:01:43 +02:00
|
|
|
}
|
2011-10-13 11:22:23 +02:00
|
|
|
entry = lookup(vaddr);
|
|
|
|
assert(entry);
|
2009-02-25 19:16:21 +01:00
|
|
|
} else {
|
2011-10-13 11:22:23 +02:00
|
|
|
DPRINTF(TLB, "Handling a TLB miss for "
|
|
|
|
"address %#x at pc %#x.\n",
|
|
|
|
vaddr, tc->instAddr());
|
|
|
|
|
|
|
|
Process *p = tc->getProcessPtr();
|
|
|
|
TlbEntry newEntry;
|
|
|
|
bool success = p->pTable->lookup(vaddr, newEntry);
|
|
|
|
if (!success && mode != Execute) {
|
|
|
|
// Check if we just need to grow the stack.
|
|
|
|
if (p->fixupStackFault(vaddr)) {
|
|
|
|
// If we did, lookup the entry for the new page.
|
|
|
|
success = p->pTable->lookup(vaddr, newEntry);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!success) {
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<PageFault>(vaddr, true, mode,
|
|
|
|
true, false);
|
2011-10-13 11:22:23 +02:00
|
|
|
} else {
|
|
|
|
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
|
|
|
|
DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
|
|
|
|
newEntry.pageStart());
|
|
|
|
entry = insert(alignedVaddr, newEntry);
|
|
|
|
}
|
|
|
|
DPRINTF(TLB, "Miss was serviced.\n");
|
|
|
|
}
|
2007-10-08 03:18:39 +02:00
|
|
|
}
|
2012-01-05 18:00:32 +01:00
|
|
|
|
|
|
|
DPRINTF(TLB, "Entry found with paddr %#x, "
|
|
|
|
"doing protection checks.\n", entry->paddr);
|
2009-02-25 19:16:21 +01:00
|
|
|
// Do paging protection checks.
|
2009-04-27 01:48:44 +02:00
|
|
|
bool inUser = (m5Reg.cpl == 3 &&
|
2009-02-25 19:18:58 +01:00
|
|
|
!(flags & (CPL0FlagBit << FlagShift)));
|
2011-02-08 00:18:52 +01:00
|
|
|
CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
|
|
|
|
bool badWrite = (!entry->writable && (inUser || cr0.wp));
|
|
|
|
if ((inUser && !entry->user) || (mode == Write && badWrite)) {
|
2009-02-25 19:18:58 +01:00
|
|
|
// The page must have been present to get into the TLB in
|
|
|
|
// the first place. We'll assume the reserved bits are
|
|
|
|
// fine even though we're not checking them.
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<PageFault>(vaddr, true, mode, inUser,
|
|
|
|
false);
|
2009-02-25 19:18:58 +01:00
|
|
|
}
|
2011-02-08 00:18:52 +01:00
|
|
|
if (storeCheck && badWrite) {
|
2009-04-19 13:57:51 +02:00
|
|
|
// This would fault if this were a write, so return a page
|
|
|
|
// fault that reflects that happening.
|
2014-10-16 11:49:51 +02:00
|
|
|
return std::make_shared<PageFault>(vaddr, true, Write, inUser,
|
|
|
|
false);
|
2009-04-19 13:57:51 +02:00
|
|
|
}
|
2009-02-25 19:18:58 +01:00
|
|
|
|
2012-04-15 08:24:18 +02:00
|
|
|
Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes));
|
2009-02-25 19:16:21 +01:00
|
|
|
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
|
|
|
|
req->setPaddr(paddr);
|
2010-11-23 12:10:17 +01:00
|
|
|
if (entry->uncacheable)
|
2015-05-05 09:22:33 +02:00
|
|
|
req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
|
2007-10-08 03:18:39 +02:00
|
|
|
} else {
|
|
|
|
//Use the address which already has segmentation applied.
|
2007-11-12 23:38:31 +01:00
|
|
|
DPRINTF(TLB, "Paging disabled.\n");
|
|
|
|
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
|
2007-10-08 03:18:39 +02:00
|
|
|
req->setPaddr(vaddr);
|
|
|
|
}
|
2007-10-03 08:00:37 +02:00
|
|
|
} else {
|
2007-10-08 03:18:39 +02:00
|
|
|
// Real mode
|
2007-11-12 23:38:31 +01:00
|
|
|
DPRINTF(TLB, "In real mode.\n");
|
|
|
|
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
|
2007-10-08 03:18:39 +02:00
|
|
|
req->setPaddr(vaddr);
|
2007-10-03 08:00:37 +02:00
|
|
|
}
|
2013-06-03 13:55:41 +02:00
|
|
|
|
|
|
|
return finalizePhysical(req, tc, mode);
|
2012-03-19 11:36:09 +01:00
|
|
|
}
|
2007-09-25 02:39:56 +02:00
|
|
|
|
2007-10-08 03:18:39 +02:00
|
|
|
Fault
|
2009-04-09 07:21:27 +02:00
|
|
|
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
|
2007-10-08 03:18:39 +02:00
|
|
|
{
|
2009-02-25 19:16:21 +01:00
|
|
|
bool delayedResponse;
|
2009-04-09 07:21:27 +02:00
|
|
|
return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
|
2007-10-08 03:18:39 +02:00
|
|
|
}
|
|
|
|
|
2009-02-25 19:16:15 +01:00
|
|
|
void
|
2009-04-09 07:21:27 +02:00
|
|
|
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
|
2009-04-09 07:21:27 +02:00
|
|
|
Translation *translation, Mode mode)
|
2009-02-25 19:16:15 +01:00
|
|
|
{
|
2009-02-25 19:16:21 +01:00
|
|
|
bool delayedResponse;
|
2009-02-25 19:16:15 +01:00
|
|
|
assert(translation);
|
2009-04-09 07:21:27 +02:00
|
|
|
Fault fault =
|
|
|
|
TLB::translate(req, tc, translation, mode, delayedResponse, true);
|
2009-02-25 19:16:21 +01:00
|
|
|
if (!delayedResponse)
|
2009-04-09 07:21:27 +02:00
|
|
|
translation->finish(fault, req, tc, mode);
|
2009-02-25 19:16:15 +01:00
|
|
|
}
|
|
|
|
|
2012-03-09 15:59:28 +01:00
|
|
|
Fault
|
|
|
|
TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
|
|
|
|
{
|
|
|
|
panic("Not implemented\n");
|
|
|
|
return NoFault;
|
|
|
|
}
|
|
|
|
|
2011-02-07 07:14:18 +01:00
|
|
|
Walker *
|
|
|
|
TLB::getWalker()
|
|
|
|
{
|
|
|
|
return walker;
|
|
|
|
}
|
|
|
|
|
2007-09-25 02:39:56 +02:00
|
|
|
void
|
2015-07-07 10:51:03 +02:00
|
|
|
TLB::serialize(CheckpointOut &cp) const
|
2007-09-25 02:39:56 +02:00
|
|
|
{
|
2013-08-07 21:51:17 +02:00
|
|
|
// Only store the entries in use.
|
|
|
|
uint32_t _size = size - freeList.size();
|
|
|
|
SERIALIZE_SCALAR(_size);
|
|
|
|
SERIALIZE_SCALAR(lruSeq);
|
|
|
|
|
|
|
|
uint32_t _count = 0;
|
|
|
|
for (uint32_t x = 0; x < size; x++) {
|
2015-07-07 10:51:03 +02:00
|
|
|
if (tlb[x].trieHandle != NULL)
|
|
|
|
tlb[x].serializeSection(cp, csprintf("Entry%d", _count++));
|
2013-08-07 21:51:17 +02:00
|
|
|
}
|
2007-09-25 02:39:56 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2015-07-07 10:51:03 +02:00
|
|
|
TLB::unserialize(CheckpointIn &cp)
|
2007-09-25 02:39:56 +02:00
|
|
|
{
|
2013-08-07 21:51:17 +02:00
|
|
|
// Do not allow to restore with a smaller tlb.
|
|
|
|
uint32_t _size;
|
|
|
|
UNSERIALIZE_SCALAR(_size);
|
|
|
|
if (_size > size) {
|
|
|
|
fatal("TLB size less than the one in checkpoint!");
|
|
|
|
}
|
|
|
|
|
|
|
|
UNSERIALIZE_SCALAR(lruSeq);
|
|
|
|
|
|
|
|
for (uint32_t x = 0; x < _size; x++) {
|
|
|
|
TlbEntry *newEntry = freeList.front();
|
|
|
|
freeList.pop_front();
|
|
|
|
|
2015-07-07 10:51:03 +02:00
|
|
|
newEntry->unserializeSection(cp, csprintf("Entry%d", x));
|
2013-08-07 21:51:17 +02:00
|
|
|
newEntry->trieHandle = trie.insert(newEntry->vaddr,
|
|
|
|
TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry);
|
|
|
|
}
|
2007-09-25 02:39:56 +02:00
|
|
|
}
|
|
|
|
|
2012-10-15 14:12:35 +02:00
|
|
|
BaseMasterPort *
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
TLB::getMasterPort()
|
2012-03-01 18:37:03 +01:00
|
|
|
{
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
return &walker->getMasterPort("port");
|
2012-03-01 18:37:03 +01:00
|
|
|
}
|
|
|
|
|
2011-01-03 23:35:43 +01:00
|
|
|
} // namespace X86ISA
|
2007-09-25 02:39:56 +02:00
|
|
|
|
2009-04-09 07:21:27 +02:00
|
|
|
X86ISA::TLB *
|
|
|
|
X86TLBParams::create()
|
2007-08-27 05:24:18 +02:00
|
|
|
{
|
2009-04-09 07:21:27 +02:00
|
|
|
return new X86ISA::TLB(this);
|
2007-08-27 05:24:18 +02:00
|
|
|
}
|