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X86: Obey the wp bit of CR0.

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If cr0.wp ("write protect" bit) is clear then do not generate page faults when
writing to write-protected pages in kernel mode.
This commit is contained in:
Tim Harris 2011-02-07 15:18:52 -08:00
parent 6da83b8a1b
commit 44e5e7e053
1 changed files with 4 additions and 3 deletions
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7
src/arch/x86/tlb.cc
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@ -634,14 +634,15 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
// Do paging protection checks.
bool inUser = (m5Reg.cpl == 3 &&
!(flags & (CPL0FlagBit << FlagShift)));
if ((inUser && !entry->user) ||
(mode == Write && !entry->writable)) {
CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
bool badWrite = (!entry->writable && (inUser || cr0.wp));
if ((inUser && !entry->user) || (mode == Write && badWrite)) {
// The page must have been present to get into the TLB in
// the first place. We'll assume the reserved bits are
// fine even though we're not checking them.
return new PageFault(vaddr, true, mode, inUser, false);
}
if (storeCheck && !entry->writable) {
if (storeCheck && badWrite) {
// This would fault if this were a write, so return a page
// fault that reflects that happening.
return new PageFault(vaddr, true, Write, inUser, false);