style: [patch 3/22] reduce include dependencies in some headers

Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.

src/arch/alpha/process.cc

@@ -40,6 +40,7 @@
 #include "mem/page_table.hh"
 #include "sim/byteswap.hh"
 #include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
 #include "sim/system.hh"
 
 using namespace AlphaISA;

src/arch/alpha/process.hh

@@ -32,6 +32,7 @@
 #ifndef __ARCH_ALPHA_PROCESS_HH__
 #define __ARCH_ALPHA_PROCESS_HH__
 
+#include "mem/page_table.hh"
 #include "sim/process.hh"
 
 class AlphaLiveProcess : public LiveProcess

src/arch/arm/process.cc

@@ -53,6 +53,7 @@
 #include "mem/page_table.hh"
 #include "sim/byteswap.hh"
 #include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
 #include "sim/system.hh"
 
 using namespace std;

src/arch/arm/process.hh

@@ -48,6 +48,7 @@
 
 #include "arch/arm/intregs.hh"
 #include "base/loader/object_file.hh"
+#include "mem/page_table.hh"
 #include "sim/process.hh"
 
 class LiveProcess;

src/arch/mips/process.cc

@@ -41,6 +41,7 @@
 #include "mem/page_table.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
 #include "sim/system.hh"
 
 using namespace std;

src/arch/mips/process.hh

@@ -35,6 +35,7 @@
 #include <string>
 #include <vector>
 
+#include "mem/page_table.hh"
 #include "sim/process.hh"
 
 class LiveProcess;

src/arch/power/interrupts.hh

@@ -35,6 +35,7 @@
 #include "params/PowerInterrupts.hh"
 #include "sim/sim_object.hh"
 
+class BaseCPU;
 class ThreadContext;
 
 namespace PowerISA {

src/arch/power/process.cc

@@ -41,6 +41,7 @@
 #include "debug/Stack.hh"
 #include "mem/page_table.hh"
 #include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
 #include "sim/system.hh"
 
 using namespace std;

src/arch/power/process.hh

@@ -36,6 +36,7 @@
 #include <string>
 #include <vector>
 
+#include "mem/page_table.hh"
 #include "sim/process.hh"
 
 class LiveProcess;

src/arch/power/remote_gdb.cc

@@ -133,6 +133,7 @@
  * "Stub" to allow remote cpu to debug over a serial line using gdb.
  */
 
+
 #include "arch/power/remote_gdb.hh"
 
 #include <sys/signal.h>
@@ -144,6 +145,7 @@
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "debug/GDBMisc.hh"
+#include "mem/page_table.hh"
 #include "sim/byteswap.hh"
 
 using namespace std;

src/arch/riscv/interrupts.hh

@@ -35,6 +35,7 @@
 #include "params/RiscvInterrupts.hh"
 #include "sim/sim_object.hh"
 
+class BaseCPU;
 class ThreadContext;
 
 namespace RiscvISA {

src/arch/riscv/process.cc

@@ -44,6 +44,7 @@
 #include "mem/page_table.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
 #include "sim/system.hh"
 
 using namespace std;

src/arch/riscv/process.hh

@@ -35,6 +35,7 @@
 #include <string>
 #include <vector>
 
+#include "mem/page_table.hh"
 #include "sim/process.hh"
 
 class LiveProcess;

src/arch/sparc/process.cc

@@ -43,6 +43,7 @@
 #include "debug/Stack.hh"
 #include "mem/page_table.hh"
 #include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
 #include "sim/system.hh"
 
 using namespace std;

src/arch/sparc/process.hh

@@ -35,6 +35,7 @@
 #include <string>
 #include <vector>
 
+#include "mem/page_table.hh"
 #include "sim/byteswap.hh"
 #include "sim/process.hh"
 

src/arch/x86/isa_traits.hh

@@ -42,6 +42,7 @@
 
 #include "arch/x86/types.hh"
 #include "arch/x86/x86_traits.hh"
+#include "base/compiler.hh"
 #include "base/types.hh"
 
 namespace LittleEndianGuest {}

src/arch/x86/pagetable.hh

@@ -46,14 +46,13 @@
 #include <vector>
 
 #include "base/bitunion.hh"
-#include "base/misc.hh"
 #include "base/types.hh"
 #include "base/trie.hh"
-#include "cpu/thread_context.hh"
 #include "arch/x86/system.hh"
 #include "debug/MMU.hh"
 
 class Checkpoint;
+class ThreadContext;
 
 namespace X86ISA
 {

src/arch/x86/process.cc

@@ -59,6 +59,7 @@
 #include "mem/page_table.hh"
 #include "sim/process_impl.hh"
 #include "sim/syscall_desc.hh"
+#include "sim/syscall_return.hh"
 #include "sim/system.hh"
 
 using namespace std;

src/arch/x86/pseudo_inst.cc

@@ -31,9 +31,10 @@
 #include "arch/x86/pseudo_inst.hh"
 
 #include "arch/x86/system.hh"
+#include "cpu/thread_context.hh"
 #include "debug/PseudoInst.hh"
+#include "mem/se_translating_port_proxy.hh"
 #include "sim/process.hh"
-#include "sim/system.hh"
 
 using namespace X86ISA;
 

src/arch/x86/system.cc

@@ -39,19 +39,12 @@
 
 #include "arch/x86/system.hh"
 
-#include "arch/vtophys.hh"
 #include "arch/x86/bios/intelmp.hh"
 #include "arch/x86/bios/smbios.hh"
 #include "arch/x86/isa_traits.hh"
-#include "arch/x86/regs/misc.hh"
-#include "base/intmath.hh"
 #include "base/loader/object_file.hh"
-#include "base/loader/symtab.hh"
-#include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "mem/port_proxy.hh"
 #include "params/X86System.hh"
-#include "sim/byteswap.hh"
 
 using namespace LittleEndianGuest;
 using namespace X86ISA;

src/arch/x86/system.hh

@@ -44,11 +44,7 @@
 #include <vector>
 
 #include "arch/x86/regs/misc.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/pc_event.hh"
-#include "kern/system_events.hh"
 #include "params/X86System.hh"
-#include "sim/sim_object.hh"
 #include "sim/system.hh"
 
 namespace X86ISA

src/arch/x86/tlb.cc

@@ -45,17 +45,13 @@
 #include "arch/generic/mmapped_ipr.hh"
 #include "arch/x86/faults.hh"
 #include "arch/x86/insts/microldstop.hh"
-#include "arch/x86/pagetable.hh"
 #include "arch/x86/pagetable_walker.hh"
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/regs/msr.hh"
 #include "arch/x86/x86_traits.hh"
-#include "base/bitfield.hh"
 #include "base/trace.hh"
-#include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/TLB.hh"
-#include "mem/packet_access.hh"
 #include "mem/page_table.hh"
 #include "mem/request.hh"
 #include "sim/full_system.hh"

src/arch/x86/tlb.hh

@@ -41,20 +41,15 @@
 #define __ARCH_X86_TLB_HH__
 
 #include <list>
-#include <string>
 #include <vector>
 
 #include "arch/generic/tlb.hh"
-#include "arch/x86/regs/segment.hh"
 #include "arch/x86/pagetable.hh"
 #include "base/trie.hh"
-#include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
-#include "sim/sim_object.hh"
 
 class ThreadContext;
-class Packet;
 
 namespace X86ISA
 {

src/arch/x86/utility.cc

@@ -42,11 +42,10 @@
 
 #include "arch/x86/interrupts.hh"
 #include "arch/x86/registers.hh"
-#include "arch/x86/tlb.hh"
 #include "arch/x86/x86_traits.hh"
 #include "cpu/base.hh"
 #include "fputils/fp80.h"
-#include "sim/system.hh"
+#include "sim/full_system.hh"
 
 namespace X86ISA {
 

src/arch/x86/utility.hh

@@ -40,16 +40,10 @@
 #ifndef __ARCH_X86_UTILITY_HH__
 #define __ARCH_X86_UTILITY_HH__
 
-#include "arch/x86/regs/misc.hh"
-#include "arch/x86/types.hh"
-#include "base/misc.hh"
-#include "base/types.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "sim/full_system.hh"
 
-class ThreadContext;
-
 namespace X86ISA
 {
 

src/base/bitfield.hh

@@ -32,7 +32,7 @@
 #ifndef __BASE_BITFIELD_HH__
 #define __BASE_BITFIELD_HH__
 
-#include "base/types.hh"
+#include <inttypes.h>
 
 /**
  * Generate a 64-bit mask of 'nbits' 1s, right justified.

src/base/bitunion.hh

@@ -32,7 +32,6 @@
 #define __BASE_BITUNION_HH__
 
 #include "base/bitfield.hh"
-#include "base/types.hh"
 
 //      The following implements the BitUnion system of defining bitfields
 //on top of an underlying class. This is done through the pervasive use of

src/base/time.cc

@@ -35,6 +35,7 @@
 #include <iostream>
 #include <sstream>
 
+#include "base/misc.hh"
 #include "config/use_posix_clock.hh"
 #include "sim/core.hh"
 #include "sim/serialize.hh"

src/base/vnc/vncinput.cc

@@ -46,7 +46,8 @@
 
 #include <sys/types.h>
 
-#include "base/output.hh" //simout
+#include "base/misc.hh"
+#include "base/output.hh"
 #include "base/trace.hh"
 #include "debug/VNC.hh"
 

src/cpu/minor/buffers.hh

@@ -50,6 +50,7 @@
 #include <queue>
 #include <sstream>
 
+#include "base/misc.hh"
 #include "cpu/minor/trace.hh"
 #include "cpu/activity.hh"
 #include "cpu/timebuf.hh"

src/cpu/testers/directedtest/InvalidateGenerator.cc

@@ -29,6 +29,7 @@
 
 #include "cpu/testers/directedtest/InvalidateGenerator.hh"
 
+#include "base/trace.hh"
 #include "cpu/testers/directedtest/DirectedGenerator.hh"
 #include "cpu/testers/directedtest/RubyDirectedTester.hh"
 #include "debug/DirectedTest.hh"

src/cpu/testers/directedtest/RubyDirectedTester.cc

@@ -41,6 +41,7 @@
 
 #include "cpu/testers/directedtest/RubyDirectedTester.hh"
 
+#include "base/trace.hh"
 #include "cpu/testers/directedtest/DirectedGenerator.hh"
 #include "debug/DirectedTest.hh"
 #include "sim/sim_exit.hh"

src/cpu/testers/directedtest/SeriesRequestGenerator.cc

@@ -30,6 +30,7 @@
 #include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
 
 #include "base/random.hh"
+#include "base/trace.hh"
 #include "cpu/testers/directedtest/DirectedGenerator.hh"
 #include "cpu/testers/directedtest/RubyDirectedTester.hh"
 #include "debug/DirectedTest.hh"

src/cpu/testers/memtest/memtest.cc

@@ -46,6 +46,7 @@
 
 #include "base/random.hh"
 #include "base/statistics.hh"
+#include "base/trace.hh"
 #include "debug/MemTest.hh"
 #include "mem/mem_object.hh"
 #include "sim/sim_exit.hh"

src/cpu/testers/rubytest/Check.cc

@@ -30,6 +30,7 @@
 #include "cpu/testers/rubytest/Check.hh"
 
 #include "base/random.hh"
+#include "base/trace.hh"
 #include "debug/RubyTest.hh"
 #include "mem/ruby/common/SubBlock.hh"
 

src/cpu/testers/rubytest/CheckTable.cc

@@ -31,6 +31,7 @@
 
 #include "base/intmath.hh"
 #include "base/random.hh"
+#include "base/trace.hh"
 #include "cpu/testers/rubytest/Check.hh"
 #include "debug/RubyTest.hh"
 

src/cpu/testers/rubytest/RubyTester.cc

@@ -42,6 +42,7 @@
 #include "cpu/testers/rubytest/RubyTester.hh"
 
 #include "base/misc.hh"
+#include "base/trace.hh"
 #include "cpu/testers/rubytest/Check.hh"
 #include "debug/RubyTest.hh"
 #include "mem/ruby/common/SubBlock.hh"

src/dev/arm/flash_device.cc

@@ -54,6 +54,7 @@
 
 #include "dev/arm/flash_device.hh"
 
+#include "base/trace.hh"
 #include "debug/Drain.hh"
 
 /**

src/dev/mc146818.hh

@@ -34,6 +34,7 @@
 #define __DEV_MC146818_HH__
 
 #include "base/bitunion.hh"
+#include "base/misc.hh"
 #include "sim/eventq_impl.hh"
 
 /** Real-Time Clock (MC146818) */

src/dev/net/dist_iface.hh

@@ -83,6 +83,7 @@
 #include <thread>
 #include <utility>
 
+#include "base/misc.hh"
 #include "dev/net/dist_packet.hh"
 #include "dev/net/etherpkt.hh"
 #include "sim/core.hh"

src/dev/net/etherbus.cc

@@ -38,6 +38,7 @@
 #include <string>
 #include <vector>
 
+#include "base/misc.hh"
 #include "base/trace.hh"
 #include "debug/Ethernet.hh"
 #include "debug/EthernetData.hh"

src/dev/net/etherswitch.cc

@@ -36,7 +36,9 @@
 #include "dev/net/etherswitch.hh"
 
 #include "base/random.hh"
+#include "base/trace.hh"
 #include "debug/EthernetAll.hh"
+#include "sim/core.hh"
 
 using namespace std;
 

src/gpu-compute/vector_register_file.hh

@@ -39,6 +39,7 @@
 #include <list>
 
 #include "base/statistics.hh"
+#include "base/trace.hh"
 #include "base/types.hh"
 #include "debug/GPUVRF.hh"
 #include "gpu-compute/vector_register_state.hh"

src/kern/linux/linux.cc

@@ -33,7 +33,6 @@
 #include <cstdio>
 #include <string>
 
-#include "cpu/thread_context.hh"
 #include "debug/SyscallVerbose.hh"
 #include "sim/process.hh"
 #include "sim/system.hh"

src/kern/linux/linux.hh

@@ -36,9 +36,9 @@
 #include <string>
 
 #include "kern/operatingsystem.hh"
+#include "sim/process.hh"
 
 class ThreadContext;
-class LiveProcess;
 
 ///
 /// This class encapsulates the types, structures, constants,

src/mem/cache/prefetch/stride.cc

@@ -49,6 +49,7 @@
 #include "mem/cache/prefetch/stride.hh"
 
 #include "base/random.hh"
+#include "base/trace.hh"
 #include "debug/HWPrefetch.hh"
 
 StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)

src/mem/external_master.cc

@@ -43,6 +43,7 @@
 #include <cctype>
 #include <iomanip>
 
+#include "base/trace.hh"
 #include "debug/ExternalPort.hh"
 
 std::map<std::string, ExternalMaster::Handler *>

src/mem/external_slave.cc

@@ -42,6 +42,7 @@
 #include <cctype>
 #include <iomanip>
 
+#include "base/trace.hh"
 #include "debug/ExternalPort.hh"
 
 /** Implement a `stub' port which just responds to requests by printing

src/mem/mem_checker.hh

@@ -48,6 +48,7 @@
 #include <vector>
 
 #include "base/misc.hh"
+#include "base/trace.hh"
 #include "base/types.hh"
 #include "debug/MemChecker.hh"
 #include "params/MemChecker.hh"

src/mem/multi_level_page_table.hh

@@ -38,13 +38,12 @@
 
 #include <string>
 
-#include "arch/isa_traits.hh"
 #include "arch/tlb.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "mem/page_table.hh"
-#include "sim/serialize.hh"
-#include "sim/system.hh"
+
+class System;
 
 /**
  * This class implements an in-memory multi-level page table that can be

src/mem/multi_level_page_table_impl.hh

@@ -32,18 +32,15 @@
  * @file
  * Definitions of page table
  */
-#include <fstream>
-#include <map>
 #include <string>
 
-#include "base/bitfield.hh"
-#include "base/intmath.hh"
+#include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "debug/MMU.hh"
 #include "mem/multi_level_page_table.hh"
-#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "mem/page_table.hh"
 
 using namespace std;
 using namespace TheISA;

src/mem/page_table.cc

@@ -37,18 +37,13 @@
  */
 #include "mem/page_table.hh"
 
-#include <fstream>
-#include <map>
-#include <memory>
 #include <string>
 
-#include "base/bitfield.hh"
-#include "base/intmath.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "debug/MMU.hh"
 #include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/serialize.hh"
 
 using namespace std;
 using namespace TheISA;

src/mem/page_table.hh

@@ -42,13 +42,14 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/tlb.hh"
+#include "base/intmath.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "mem/request.hh"
 #include "sim/serialize.hh"
-#include "sim/system.hh"
 
 class ThreadContext;
+class System;
 
 /**
  * Declaration of base class for page table

src/mem/ruby/network/MessageBuffer.hh

@@ -41,6 +41,7 @@
 #include <string>
 #include <vector>
 
+#include "base/trace.hh"
 #include "debug/RubyQueue.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"

src/mem/ruby/structures/AbstractReplacementPolicy.cc

@@ -30,6 +30,8 @@
 
 #include "mem/ruby/structures/AbstractReplacementPolicy.hh"
 
+#include "base/misc.hh"
+
 AbstractReplacementPolicy::AbstractReplacementPolicy(const Params * p)
   : SimObject(p)
 {

src/mem/se_translating_port_proxy.hh

@@ -45,9 +45,9 @@
 #ifndef __MEM_SE_TRANSLATING_PORT_PROXY_HH__
 #define __MEM_SE_TRANSLATING_PORT_PROXY_HH__
 
-#include "mem/page_table.hh"
 #include "mem/port_proxy.hh"
 
+class PageTableBase;
 class Process;
 
 /**

src/mem/simple_mem.cc

@@ -45,6 +45,7 @@
 #include "mem/simple_mem.hh"
 
 #include "base/random.hh"
+#include "base/trace.hh"
 #include "debug/Drain.hh"
 
 using namespace std;

src/python/swig/pyevent.cc

@@ -32,6 +32,7 @@
 
 #include <Python.h>
 
+#include "base/misc.hh"
 #include "sim/async.hh"
 #include "sim/eventq.hh"
 

src/sim/SConscript

@@ -82,6 +82,9 @@ if env['TARGET_ISA'] != 'null':
     Source('syscall_emul.cc')
     Source('syscall_desc.cc')
 
+if env['TARGET_ISA'] != 'x86':
+    Source('microcode_rom.cc')
+
 DebugFlag('Checkpoint')
 DebugFlag('Config')
 DebugFlag('CxxConfig')

src/sim/arguments.cc

@@ -32,7 +32,6 @@
 
 #include "arch/utility.hh"
 #include "config/the_isa.hh"
-#include "cpu/thread_context.hh"
 
 Arguments::Data::~Data()
 {

src/sim/arguments.hh

@@ -34,7 +34,6 @@
 #include <cassert>
 #include <memory>
 
-#include "base/types.hh"
 #include "mem/fs_translating_port_proxy.hh"
 
 class ThreadContext;

src/sim/byteswap.hh

@@ -38,7 +38,6 @@
 #define __SIM_BYTE_SWAP_HH__
 
 #include "base/bigint.hh"
-#include "base/misc.hh"
 #include "base/types.hh"
 
 // This lets us figure out what the byte order of the host system is

src/sim/clock_domain.cc

@@ -47,6 +47,7 @@
 #include <algorithm>
 #include <functional>
 
+#include "base/trace.hh"
 #include "debug/ClockDomain.hh"
 #include "params/ClockDomain.hh"
 #include "params/DerivedClockDomain.hh"

src/sim/clocked_object.hh

@@ -51,7 +51,6 @@
 
 #include "base/callback.hh"
 #include "base/intmath.hh"
-#include "base/misc.hh"
 #include "enums/PwrState.hh"
 #include "params/ClockedObject.hh"
 #include "sim/core.hh"

src/sim/cxx_config.hh

@@ -57,8 +57,6 @@
 #include <string>
 #include <vector>
 
-#include "mem/port.hh"
-#include "params/SimObject.hh"
 #include "sim/sim_object.hh"
 
 class CxxConfigParams;

src/sim/cxx_config_ini.cc

@@ -39,6 +39,8 @@
 
 #include "sim/cxx_config_ini.hh"
 
+#include "base/str.hh"
+
 bool
 CxxIniFile::getParam(const std::string &object_name,
     const std::string &param_name,

src/sim/cxx_config_ini.hh

@@ -47,7 +47,6 @@
 #define __SIM_CXX_CONFIG_INI_HH__
 
 #include "base/inifile.hh"
-#include "base/str.hh"
 #include "sim/cxx_config.hh"
 
 /** CxxConfigManager interface for using .ini files */

src/sim/cxx_manager.cc

@@ -43,6 +43,7 @@
 #include <sstream>
 
 #include "base/str.hh"
+#include "base/trace.hh"
 #include "debug/CxxConfig.hh"
 #include "mem/mem_object.hh"
 #include "sim/serialize.hh"

src/sim/drain.hh

@@ -44,8 +44,6 @@
 #include <mutex>
 #include <unordered_set>
 
-#include "base/flags.hh"
-
 class Drainable;
 
 #ifndef SWIG // SWIG doesn't support strongly typed enums

src/sim/dvfs_handler.cc

@@ -45,9 +45,11 @@
 #include <utility>
 
 #include "base/misc.hh"
+#include "base/trace.hh"
 #include "debug/DVFS.hh"
 #include "params/DVFSHandler.hh"
 #include "sim/clock_domain.hh"
+#include "sim/eventq_impl.hh"
 #include "sim/stat_control.hh"
 #include "sim/voltage_domain.hh"
 
@@ -170,6 +172,30 @@ DVFSHandler::UpdateEvent::updatePerfLevel()
     d->perfLevel(perfLevelToSet);
 }
 
+double
+DVFSHandler::voltageAtPerfLevel(DomainID domain_id, PerfLevel perf_level) const
+{
+    VoltageDomain *d = findDomain(domain_id)->voltageDomain();
+    assert(d);
+    PerfLevel n = d->numVoltages();
+    if (perf_level < n)
+        return d->voltage(perf_level);
+
+    // Request outside of the range of the voltage domain
+    if (n == 1) {
+        DPRINTF(DVFS, "DVFS: Request for perf-level %i for single-point "\
+                "voltage domain %s.  Returning voltage at level 0: %.2f "\
+                "V\n", perf_level, d->name(), d->voltage(0));
+        // Special case for single point voltage domain -> same voltage for
+        // all points
+        return d->voltage(0);
+    }
+
+    warn("DVFSHandler %s reads illegal voltage level %u from "\
+         "VoltageDomain %s. Returning 0 V\n", name(), perf_level, d->name());
+    return 0.;
+}
+
 void
 DVFSHandler::serialize(CheckpointOut &cp) const
 {

src/sim/dvfs_handler.hh

@@ -53,13 +53,10 @@
 #include <vector>
 
 #include "debug/DVFS.hh"
-#include "params/ClockDomain.hh"
 #include "params/DVFSHandler.hh"
-#include "params/VoltageDomain.hh"
 #include "sim/clock_domain.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
-#include "sim/voltage_domain.hh"
 
 /**
  * DVFS Handler class, maintains a list of all the domains it can handle.
@@ -156,28 +153,7 @@ class DVFSHandler : public SimObject
      * @return Voltage for the requested performance level of the respective
      * domain
      */
-    double voltageAtPerfLevel(DomainID domain_id, PerfLevel perf_level) const
-    {
-        VoltageDomain *d = findDomain(domain_id)->voltageDomain();
-        assert(d);
-        PerfLevel n = d->numVoltages();
-        if (perf_level < n)
-            return d->voltage(perf_level);
-
-        // Request outside of the range of the voltage domain
-        if (n == 1) {
-            DPRINTF(DVFS, "DVFS: Request for perf-level %i for single-point "\
-                    "voltage domain %s.  Returning voltage at level 0: %.2f "\
-                    "V\n", perf_level, d->name(), d->voltage(0));
-            // Special case for single point voltage domain -> same voltage for
-            // all points
-            return d->voltage(0);
-        }
-
-        warn("DVFSHandler %s reads illegal voltage level %u from "\
-             "VoltageDomain %s. Returning 0 V\n", name(), perf_level, d->name());
-        return 0.;
-    }
+    double voltageAtPerfLevel(DomainID domain_id, PerfLevel perf_level) const;
 
     /**
      * Get the total number of available performance levels.

src/sim/eventq.hh

@@ -47,7 +47,6 @@
 #include <string>
 
 #include "base/flags.hh"
-#include "base/misc.hh"
 #include "base/types.hh"
 #include "debug/Event.hh"
 #include "sim/serialize.hh"

src/sim/fd_entry.hh

@@ -35,7 +35,9 @@
 #include <ostream>
 #include <string>
 
-#include "sim/emul_driver.hh"
+#include "sim/serialize.hh"
+
+class EmulatedDriver;
 
 /**
  * FDEntry is used to manage a single file descriptor mapping and metadata

src/sim/init_signals.cc

@@ -52,6 +52,7 @@
 
 #include "base/atomicio.hh"
 #include "base/cprintf.hh"
+#include "base/misc.hh"
 #include "sim/async.hh"
 #include "sim/backtrace.hh"
 #include "sim/core.hh"

src/sim/insttracer.hh

@@ -45,9 +45,8 @@
 #define __INSTRECORD_HH__
 
 #include "base/bigint.hh"
-#include "base/trace.hh"
 #include "base/types.hh"
-#include "cpu/inst_seq.hh"      // for InstSeqNum
+#include "cpu/inst_seq.hh"
 #include "cpu/static_inst.hh"
 #include "sim/sim_object.hh"
 

src/sim/microcode_rom.cc

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "sim/microcode_rom.hh"
+
+#include "base/misc.hh"
+#include "cpu/static_inst_fwd.hh"
+
+StaticInstPtr
+MicrocodeRom::fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop)
+{
+    panic("ROM based microcode isn't implemented.\n");
+}

src/sim/microcode_rom.hh

@@ -36,17 +36,16 @@
  * anything more.
  */
 
-#include "base/misc.hh"
-#include "cpu/static_inst.hh"
+#include <inttypes.h>
+
+#include "cpu/static_inst_fwd.hh"
+
+typedef uint16_t MicroPC;
 
 class MicrocodeRom
 {
   public:
-    StaticInstPtr
-    fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop)
-    {
-        panic("ROM based microcode isn't implemented.\n");
-    }
+    StaticInstPtr fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop);
 };
 
 #endif // __SIM_MICROCODE_ROM_HH__

src/sim/power/mathexpr_powermodel.hh

@@ -42,11 +42,13 @@
 
 #include <unordered_map>
 
-#include "base/statistics.hh"
 #include "params/MathExprPowerModel.hh"
 #include "sim/mathexpr.hh"
 #include "sim/power/power_model.hh"
-#include "sim/sim_object.hh"
+
+namespace Stats {
+    class Info;
+}
 
 /**
  * A Equation power model. The power is represented as a combination

src/sim/power/power_model.cc

@@ -42,7 +42,7 @@
 #include "base/statistics.hh"
 #include "params/PowerModel.hh"
 #include "params/PowerModelState.hh"
-#include "sim/sim_object.hh"
+#include "sim/clocked_object.hh"
 #include "sim/sub_system.hh"
 
 PowerModelState::PowerModelState(const Params *p)

src/sim/power/power_model.hh

@@ -43,9 +43,10 @@
 #include "base/statistics.hh"
 #include "params/PowerModel.hh"
 #include "params/PowerModelState.hh"
-#include "sim/power/thermal_model.hh"
 #include "sim/probe/probe.hh"
-#include "sim/sim_object.hh"
+
+class SimObject;
+class ClockedObject;
 
 /**
  * A PowerModelState is an abstract class used as interface to get power

src/sim/power/thermal_domain.cc

@@ -44,8 +44,11 @@
 #include "base/statistics.hh"
 #include "debug/ThermalDomain.hh"
 #include "params/ThermalDomain.hh"
+#include "sim/clocked_object.hh"
+#include "sim/linear_solver.hh"
 #include "sim/power/thermal_model.hh"
-#include "sim/sim_object.hh"
+#include "sim/probe/probe.hh"
+#include "sim/sub_system.hh"
 
 ThermalDomain::ThermalDomain(const Params *p)
     : SimObject(p), _initTemperature(p->initial_temperature),

src/sim/power/thermal_domain.hh

@@ -45,11 +45,11 @@
 #include "base/statistics.hh"
 #include "params/ThermalDomain.hh"
 #include "sim/power/thermal_entity.hh"
-#include "sim/probe/probe.hh"
 #include "sim/sim_object.hh"
-#include "sim/sub_system.hh"
 
+class SubSystem;
 class ThermalNode;
+template <class T> class ProbePointArg;
 
 /**
  * A ThermalDomain is used to group objects under that operate under

src/sim/power/thermal_entity.hh

@@ -40,8 +40,7 @@
 #ifndef __SIM_THERMAL_ENTITY_HH__
 #define __SIM_THERMAL_ENTITY_HH__
 
-#include "sim/linear_solver.hh"
-
+class LinearEquation;
 class ThermalNode;
 
 /**

src/sim/power/thermal_model.hh

@@ -42,7 +42,6 @@
 
 #include <vector>
 
-#include "base/statistics.hh"
 #include "params/ThermalCapacitor.hh"
 #include "params/ThermalModel.hh"
 #include "params/ThermalReference.hh"

src/sim/probe/probe.cc

@@ -40,6 +40,7 @@
 #include "sim/probe/probe.hh"
 
 #include "debug/ProbeVerbose.hh"
+#include "params/ProbeListenerObject.hh"
 
 ProbePoint::ProbePoint(ProbeManager *manager, const std::string& _name)
     : name(_name)

src/sim/probe/probe.hh

@@ -64,13 +64,14 @@
 #include <string>
 #include <vector>
 
+#include "base/compiler.hh"
 #include "base/trace.hh"
-#include "params/ProbeListenerObject.hh"
 #include "sim/sim_object.hh"
 
 /** Forward declare the ProbeManager. */
 class ProbeManager;
 class ProbeListener;
+class ProbeListenerObjectParams;
 
 /**
  * Name space containing shared probe point declarations.

src/sim/process.cc

@@ -48,9 +48,10 @@
 #include <fcntl.h>
 #include <unistd.h>
 
-#include <cstdio>
+#include <array>
 #include <map>
 #include <string>
+#include <vector>
 
 #include "base/intmath.hh"
 #include "base/loader/object_file.hh"
@@ -58,14 +59,11 @@
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
-#include "mem/multi_level_page_table.hh"
 #include "mem/page_table.hh"
 #include "mem/se_translating_port_proxy.hh"
 #include "params/LiveProcess.hh"
 #include "params/Process.hh"
-#include "sim/debug.hh"
-#include "sim/process_impl.hh"
-#include "sim/stats.hh"
+#include "sim/emul_driver.hh"
 #include "sim/syscall_desc.hh"
 #include "sim/system.hh"
 

src/sim/process.hh

@@ -34,6 +34,7 @@
 #define __PROCESS_HH__
 
 #include <array>
+#include <map>
 #include <string>
 #include <vector>
 
@@ -44,15 +45,16 @@
 #include "mem/se_translating_port_proxy.hh"
 #include "sim/fd_entry.hh"
 #include "sim/sim_object.hh"
-#include "sim/syscall_return.hh"
 
-class PageTable;
-struct ProcessParams;
 struct LiveProcessParams;
+struct ProcessParams;
+
+class EmulatedDriver;
+class PageTableBase;
 class SyscallDesc;
+class SyscallReturn;
 class System;
 class ThreadContext;
-class EmulatedDriver;
 
 template<class IntType>
 struct AuxVector

src/sim/process_impl.hh

@@ -36,7 +36,6 @@
 #include <vector>
 
 #include "mem/se_translating_port_proxy.hh"
-#include "sim/byteswap.hh"
 
 //This needs to be templated for cases where 32 bit pointers are needed.
 template<class AddrType>

src/sim/root.cc

@@ -31,13 +31,13 @@
  *          Gabe Black
  */
 
-#include "sim/root.hh"
-
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "debug/TimeSync.hh"
+#include "sim/eventq_impl.hh"
 #include "sim/full_system.hh"
+#include "sim/root.hh"
 
 Root *Root::_root = NULL;
 

src/sim/serialize.hh

@@ -59,14 +59,12 @@
 #include <vector>
 
 #include "base/bitunion.hh"
-#include "base/types.hh"
 
+class CheckpointIn;
 class IniFile;
 class Serializable;
-class CheckpointIn;
 class SimObject;
 class SimObjectResolver;
-class EventQueue;
 
 typedef std::ostream CheckpointOut;
 

src/sim/sim_exit.hh

@@ -35,7 +35,8 @@
 #include <string>
 
 #include "base/types.hh"
-#include "sim/core.hh"
+
+Tick curTick();
 
 // forward declaration
 class Callback;

src/sim/sim_object.cc

@@ -32,17 +32,11 @@
 
 #include "sim/sim_object.hh"
 
-#include <cassert>
-
-#include "base/callback.hh"
-#include "base/inifile.hh"
 #include "base/match.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
-#include "base/types.hh"
 #include "debug/Checkpoint.hh"
 #include "sim/probe/probe.hh"
-#include "sim/stats.hh"
 
 using namespace std;
 

src/sim/sim_object.hh

@@ -49,21 +49,18 @@
 #ifndef __SIM_OBJECT_HH__
 #define __SIM_OBJECT_HH__
 
-#include <iostream>
-#include <list>
-#include <map>
 #include <string>
 #include <vector>
 
-#include "enums/MemoryMode.hh"
 #include "params/SimObject.hh"
 #include "sim/drain.hh"
+#include "sim/eventq.hh"
 #include "sim/eventq_impl.hh"
 #include "sim/serialize.hh"
 
-class BaseCPU;
-class Event;
+class EventManager;
 class ProbeManager;
+
 /**
  * Abstract superclass for simulation objects.  Represents things that
  * correspond to physical components and can be specified via the

src/sim/simulate.hh

@@ -30,7 +30,8 @@
  */
 
 #include "base/types.hh"
-#include "sim/sim_events.hh"
+
+class GlobalSimLoopExitEvent;
 
 GlobalSimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
 extern GlobalSimLoopExitEvent *simulate_limit_event;

src/sim/stat_register.cc

@@ -39,6 +39,8 @@
 
 #include "sim/stat_register.hh"
 
+#include "base/statistics.hh"
+
 namespace Stats
 {
 

src/sim/stat_register.hh

@@ -44,8 +44,6 @@
 #ifndef __SIM_STAT_REGISTER_H__
 #define __SIM_STAT_REGISTER_H__
 
-#include "base/statistics.hh"
-
 namespace Stats
 {
 

src/sim/sub_system.hh

@@ -48,7 +48,6 @@
 #include <vector>
 
 #include "params/SubSystem.hh"
-#include "sim/power/thermal_domain.hh"
 #include "sim/sim_object.hh"
 
 class PowerModel;

src/sim/syscall_emul.cc

@@ -34,7 +34,6 @@
 #include <fcntl.h>
 #include <unistd.h>
 
-#include <cstdio>
 #include <iostream>
 #include <string>
 
@@ -42,7 +41,6 @@
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
-#include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "sim/process.hh"

src/sim/syscall_emul.hh

@@ -62,7 +62,7 @@
 /// application on the host machine.
 
 #ifdef __CYGWIN32__
-#include <sys/fcntl.h>  // for O_BINARY
+#include <sys/fcntl.h>
 
 #endif
 #include <fcntl.h>
@@ -78,8 +78,7 @@
 #include <cerrno>
 #include <string>
 
-#include "base/chunk_generator.hh"
-#include "base/intmath.hh"      // for RoundUp
+#include "base/intmath.hh"
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
@@ -88,13 +87,11 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
-#include "sim/byteswap.hh"
 #include "sim/emul_driver.hh"
 #include "sim/process.hh"
 #include "sim/syscall_debug_macros.hh"
 #include "sim/syscall_emul_buf.hh"
 #include "sim/syscall_return.hh"
-#include "sim/system.hh"
 
 class SyscallDesc;