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gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
sim_seconds 0.756343 # Number of seconds simulated
sim_ticks 756342731500 # Number of ticks simulated
final_tick 756342731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
host_inst_rate 137786 # Simulator instruction rate (inst/s)
host_op_rate 148444 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 67471289 # Simulator tick rate (ticks/s)
host_mem_usage 311496 # Number of bytes of host memory used
host_seconds 11209.85 # Real time elapsed on the host
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
sim_insts 1544563023 # Number of instructions simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_ops 1664032415 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 238887296 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 63148480 # Number of bytes read from this memory
system.physmem.bytes_read::total 302102080 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 104863424 # Number of bytes written to this memory
system.physmem.bytes_written::total 104863424 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3732614 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 986695 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4720345 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1638491 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1638491 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 87664 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 315845299 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 83491885 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 399424847 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 87664 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 87664 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 138645378 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 138645378 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 138645378 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 87664 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 315845299 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 83491885 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 538070225 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4720345 # Number of read requests accepted
system.physmem.writeReqs 1638491 # Number of write requests accepted
system.physmem.readBursts 4720345 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1638491 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 301644480 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 457600 # Total number of bytes read from write queue
system.physmem.bytesWritten 104860480 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 302102080 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 104863424 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 7150 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::0 296862 # Per bank write bursts
system.physmem.perBankRdBursts::1 294626 # Per bank write bursts
system.physmem.perBankRdBursts::2 288270 # Per bank write bursts
system.physmem.perBankRdBursts::3 292812 # Per bank write bursts
system.physmem.perBankRdBursts::4 290199 # Per bank write bursts
system.physmem.perBankRdBursts::5 289793 # Per bank write bursts
system.physmem.perBankRdBursts::6 284872 # Per bank write bursts
system.physmem.perBankRdBursts::7 281493 # Per bank write bursts
system.physmem.perBankRdBursts::8 297311 # Per bank write bursts
system.physmem.perBankRdBursts::9 303290 # Per bank write bursts
system.physmem.perBankRdBursts::10 295469 # Per bank write bursts
system.physmem.perBankRdBursts::11 301855 # Per bank write bursts
system.physmem.perBankRdBursts::12 303298 # Per bank write bursts
system.physmem.perBankRdBursts::13 302373 # Per bank write bursts
system.physmem.perBankRdBursts::14 297652 # Per bank write bursts
system.physmem.perBankRdBursts::15 293020 # Per bank write bursts
system.physmem.perBankWrBursts::0 104131 # Per bank write bursts
system.physmem.perBankWrBursts::1 101826 # Per bank write bursts
system.physmem.perBankWrBursts::2 99098 # Per bank write bursts
system.physmem.perBankWrBursts::3 99979 # Per bank write bursts
system.physmem.perBankWrBursts::4 99438 # Per bank write bursts
system.physmem.perBankWrBursts::5 99115 # Per bank write bursts
system.physmem.perBankWrBursts::6 102674 # Per bank write bursts
system.physmem.perBankWrBursts::7 104427 # Per bank write bursts
system.physmem.perBankWrBursts::8 105209 # Per bank write bursts
system.physmem.perBankWrBursts::9 104570 # Per bank write bursts
system.physmem.perBankWrBursts::10 102342 # Per bank write bursts
system.physmem.perBankWrBursts::11 102683 # Per bank write bursts
system.physmem.perBankWrBursts::12 102787 # Per bank write bursts
system.physmem.perBankWrBursts::13 102808 # Per bank write bursts
system.physmem.perBankWrBursts::14 104630 # Per bank write bursts
system.physmem.perBankWrBursts::15 102728 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.totGap 756342591500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readPktSize::6 4720345 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.writePktSize::6 1638491 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 2764600 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1036830 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 329452 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 239558 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 162691 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 91104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 40419 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 23320 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 17706 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 4471 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1653 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 733 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 418 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 229 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::15 22698 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 24488 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 59650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 74848 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 84172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 91913 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 98459 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 103044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 106253 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 107840 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 108834 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 109988 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 110978 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 113431 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 107071 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 104798 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 103128 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 101631 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3003 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1224 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 572 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesPerActivate::samples 4285614 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 94.853108 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 78.948636 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 101.693693 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 3410667 79.58% 79.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 676414 15.78% 95.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 97051 2.26% 97.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 35005 0.82% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 22710 0.53% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 12276 0.29% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7200 0.17% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5155 0.12% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 19136 0.45% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 4285614 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 98802 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 47.703225 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 32.303831 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 97.301104 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-127 94981 96.13% 96.13% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-255 1362 1.38% 97.51% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-383 759 0.77% 98.28% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::384-511 434 0.44% 98.72% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-639 380 0.38% 99.10% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::640-767 348 0.35% 99.46% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::768-895 273 0.28% 99.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::896-1023 148 0.15% 99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1151 67 0.07% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1152-1279 20 0.02% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1280-1407 9 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1408-1535 8 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-1663 4 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-2687 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2816-2943 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 98802 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 98802 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.583116 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.550078 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.089696 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 73349 74.24% 74.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1793 1.81% 76.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 18295 18.52% 94.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 3696 3.74% 98.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 920 0.93% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 398 0.40% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 161 0.16% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 94 0.10% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 50 0.05% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 24 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 14 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 5 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 98802 # Writes before turning the bus around for reads
system.physmem.totQLat 132475907765 # Total ticks spent queuing
system.physmem.totMemAccLat 220848314015 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 23565975000 # Total ticks spent in databus transfers
system.physmem.avgQLat 28107.45 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgMemAccLat 46857.45 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 398.82 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 138.64 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 399.42 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 138.65 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.busUtil 4.20 # Data bus utilization in percentage
system.physmem.busUtilRead 3.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 1.08 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing
system.physmem.readRowHits 1712938 # Number of row buffer hits during reads
system.physmem.writeRowHits 353078 # Number of row buffer hits during writes
system.physmem.readRowHitRate 36.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 21.55 # Row buffer hit rate for writes
system.physmem.avgGap 118943.56 # Average gap between requests
system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 16066436400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 8766408750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 18087404400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 5253193440 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 400853320515 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 102178887750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 600606152535 # Total energy per rank (pJ)
system.physmem_0.averagePower 794.094387 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 167492103071 # Time in different power states
system.physmem_0.memoryStateTime::REF 25255880000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 563593117929 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 16332729840 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 8911707750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 18675259200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 5363826480 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 402415744095 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 100808340750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 601908109395 # Total energy per rank (pJ)
system.physmem_1.averagePower 795.815775 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 165215512876 # Time in different power states
system.physmem_1.memoryStateTime::REF 25255880000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 565869633374 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 286251205 # Number of BP lookups
system.cpu.branchPred.condPredicted 223383370 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14630986 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 158738952 # Number of BTB lookups
system.cpu.branchPred.BTBHits 150334108 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.branchPred.BTBHitPct 94.705242 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 16640646 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.numCycles 1512685464 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.icacheStallCycles 13925295 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2067334861 # Number of instructions fetch has processed
system.cpu.fetch.Branches 286251205 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 166974754 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1484044715 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 29286501 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 1090 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 656878260 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 961 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1512614520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.464203 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.224459 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.rateDist::0 430302331 28.45% 28.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 465370544 30.77% 59.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 101420857 6.71% 65.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 515520788 34.08% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.rateDist::total 1512614520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.189234 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.366665 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 74740374 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 515177494 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 849893259 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 58160845 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 14642548 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 42195150 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2036986769 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 52385989 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 14642548 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 139815435 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 436624028 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 12701 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 837804287 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 83715521 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1976173031 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 26689335 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 45146280 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 125414 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1394915 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 22818803 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 1985649062 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 9127137269 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2432583454 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 143 # Number of floating rename lookups
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.rename.UndoneMaps 310750117 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 155 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 111721700 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 542489680 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 199288909 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 26826914 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 28715919 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1947778041 # Number of instructions added to the IQ (excludes non-spec)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.iqInstsIssued 1857580897 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 13541153 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 279193675 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 645796508 # Number of squashed operands that are examined and possibly removed from graph
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.issued_per_cycle::samples 1512614520 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.228060 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.150014 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.issued_per_cycle::0 560160519 37.03% 37.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 325201183 21.50% 58.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 378431439 25.02% 83.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 219774852 14.53% 98.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 29040355 1.92% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 6172 0.00% 100.00% # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.issued_per_cycle::total 1512614520 # Number of insts issued each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.fu_full::IntAlu 166509117 41.02% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 1974 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 191277328 47.12% 88.14% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 48123931 11.86% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::IntAlu 1138363415 61.28% 61.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 801029 0.04% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 532094788 28.64% 89.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 186321614 10.03% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::total 1857580897 # Type of FU issued
system.cpu.iq.rate 1.228002 # Inst issue rate
system.cpu.iq.fu_busy_cnt 405912350 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.218517 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5647229580 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2226984572 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1805831958 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2263493115 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 17832338 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 84183346 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 66238 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 13114 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 24441864 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 4579390 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4849629 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.iewSquashCycles 14642548 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 25281228 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1183865 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1947778336 # Number of instructions dispatched to IQ
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.iewDispLoadInsts 542489680 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 199288909 # Number of dispatched store instructions
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.iewIQFullEvents 158613 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1024253 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 13114 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 7709445 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8723908 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 16433353 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1827918594 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 516926976 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29662303 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.exec_nop 81 # number of nop insts executed
system.cpu.iew.exec_refs 698686621 # number of memory reference insts executed
system.cpu.iew.exec_branches 229598858 # Number of branches executed
system.cpu.iew.exec_stores 181759645 # Number of stores executed
system.cpu.iew.exec_rate 1.208393 # Inst execution rate
system.cpu.iew.wb_sent 1808851456 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1805832027 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1169265268 # num instructions producing a value
system.cpu.iew.wb_consumers 1689455879 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.wb_rate 1.193792 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.commitSquashedInsts 257820227 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.branchMispredicts 14630284 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1473146552 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.129577 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.040655 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.committed_per_cycle::0 893288218 60.64% 60.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 250810214 17.03% 77.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 109558722 7.44% 85.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 55058301 3.74% 88.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 29206870 1.98% 90.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 33934631 2.30% 93.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 24884814 1.69% 94.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 18117903 1.23% 96.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 58286879 3.96% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.committed_per_cycle::total 1473146552 # Number of insts commited each cycle
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 633153379 # Number of memory references committed
system.cpu.commit.loads 458306334 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 62 # Number of memory barriers committed
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.branches 213462426 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntAlu 1030178729 61.91% 61.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.bw_lim_events 58286879 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.rob.rob_reads 3336711734 # The number of ROB reads
system.cpu.rob.rob_writes 3883178493 # The number of ROB writes
system.cpu.timesIdled 871 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 70944 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.cpi 0.979361 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.979361 # CPI: Total CPI of All Threads
system.cpu.ipc 1.021073 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.021073 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2175874054 # number of integer regfile reads
system.cpu.int_regfile_writes 1261590215 # number of integer regfile writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fp_regfile_reads 38 # number of floating regfile reads
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fp_regfile_writes 51 # number of floating regfile writes
system.cpu.cc_regfile_reads 6966029517 # number of cc regfile reads
system.cpu.cc_regfile_writes 551971474 # number of cc regfile writes
system.cpu.misc_regfile_reads 675853074 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 17007297 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.963762 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 638259274 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 17007809 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37.527425 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 79888000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.963762 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.tag_accesses 1335624835 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1335624835 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 469463783 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 469463783 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 168795373 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 168795373 # number of WriteReq hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_hits::cpu.data 638259156 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 638259156 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 638259156 # number of overall hits
system.cpu.dcache.overall_hits::total 638259156 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 17258559 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 17258559 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3790674 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3790674 # number of WriteReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_misses::cpu.data 21049233 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 21049233 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21049235 # number of overall misses
system.cpu.dcache.overall_misses::total 21049235 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 392276819281 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 392276819281 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 143202458834 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 143202458834 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 535479278115 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 535479278115 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 535479278115 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 535479278115 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 486722342 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 486722342 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_accesses::cpu.data 659308389 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 659308389 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 659308391 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 659308391 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035459 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.035459 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021964 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.021964 # miss rate for WriteReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.031926 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.031926 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.031926 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.031926 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22729.407437 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22729.407437 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37777.571702 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37777.571702 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25439.372452 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25439.372452 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25439.370035 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25439.370035 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 19976216 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2938205 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1014245 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 66761 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.695651 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 44.010800 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.writebacks::writebacks 4837992 # number of writebacks
system.cpu.dcache.writebacks::total 4837992 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2988204 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2988204 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1053221 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1053221 # number of WriteReq MSHR hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 4041425 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4041425 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4041425 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4041425 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270355 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 14270355 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737453 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2737453 # number of WriteReq MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 17007808 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 17007808 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 17007809 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 17007809 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 303479537034 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 303479537034 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 110174073244 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 110174073244 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 413653610278 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 413653610278 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 413653672278 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 413653672278 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029319 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029319 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015861 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015861 # mshr miss rate for WriteReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025796 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025796 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21266.432197 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21266.432197 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40246.927799 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40246.927799 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24321.394637 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24321.394637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24321.396852 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24321.396852 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.replacements 591 # number of replacements
system.cpu.icache.tags.tagsinuse 445.749905 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 656876635 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1079 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 608782.794254 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 445.749905 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.870605 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.870605 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1313757597 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1313757597 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 656876635 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 656876635 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 656876635 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 656876635 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 656876635 # number of overall hits
system.cpu.icache.overall_hits::total 656876635 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1624 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1624 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1624 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1624 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1624 # number of overall misses
system.cpu.icache.overall_misses::total 1624 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 95182738 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 95182738 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 95182738 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 95182738 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 95182738 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 95182738 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 656878259 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 656878259 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 656878259 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 656878259 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 656878259 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 656878259 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58610.060345 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 58610.060345 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 58610.060345 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 58610.060345 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 15932 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 279 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 82.549223 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 39.857143 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 545 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 545 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 545 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 545 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 545 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 545 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1079 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1079 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1079 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1079 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1079 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1079 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69657739 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 69657739 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69657739 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 69657739 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69657739 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 69657739 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64557.682113 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64557.682113 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued 10957108 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 11640584 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 428597 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 4655192 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 4712285 # number of replacements
system.cpu.l2cache.tags.tagsinuse 16126.126522 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 15322460 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4728219 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 3.240641 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 29457635500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 5257.920148 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.981837 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 7532.490537 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3316.734000 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.320918 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001159 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.459747 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.202437 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.984261 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 762 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15172 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 562 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 192 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 487 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2381 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1270 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1696 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.046509 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.926025 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 357015786 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 357015786 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 43 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 11478119 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 11478162 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 4837992 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 4837992 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1752292 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1752292 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 43 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 13230411 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 13230454 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 43 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 13230411 # number of overall hits
system.cpu.l2cache.overall_hits::total 13230454 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 1036 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 2792203 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 2793239 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 985195 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 985195 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1036 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3777398 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 3778434 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1036 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3777398 # number of overall misses
system.cpu.l2cache.overall_misses::total 3778434 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68850750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 219170127718 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 219238978468 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95974587720 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 95974587720 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 68850750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 315144715438 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 315213566188 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 68850750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 315144715438 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 315213566188 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1079 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 14270322 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 14271401 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 4837992 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 4837992 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737487 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2737487 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1079 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 17007809 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 17008888 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1079 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 17007809 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 17008888 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960148 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195665 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.195723 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359890 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.359890 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960148 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.222098 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.222145 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960148 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.222098 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.222145 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66458.252896 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78493.622318 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 78489.158453 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97416.844097 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97416.844097 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 83424.393859 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 83424.393859 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1638491 # number of writebacks
system.cpu.l2cache.writebacks::total 1638491 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43338 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 43338 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3740 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 3740 # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 47078 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 47078 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 47078 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 47078 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1036 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748865 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 2749901 # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993225 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 993225 # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981455 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 981455 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1036 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3730320 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3731356 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1036 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3730320 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993225 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4724581 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59969750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 193568757616 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 193628727366 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68540364307 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87429015038 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87429015038 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59969750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 280997772654 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 281057742404 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59969750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 280997772654 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 349598106711 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192628 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192686 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358524 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358524 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.219377 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.277771 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57885.859073 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70417.702439 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70412.981182 # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69007.892781 # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89081.022602 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89081.022602 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75323.218263 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73995.579018 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 14271401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 14271401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 4837992 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 1352607 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2737487 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2737487 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2158 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38853610 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 38855768 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398131264 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1398200320 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1352607 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 23199492 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5.058303 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.234316 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 21846885 94.17% 94.17% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 1352607 5.83% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 23199492 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 15761436995 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1798250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 26002804288 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%)
system.membus.trans_dist::ReadReq 3738412 # Transaction distribution
system.membus.trans_dist::ReadResp 3738412 # Transaction distribution
system.membus.trans_dist::Writeback 1638491 # Transaction distribution
system.membus.trans_dist::ReadExReq 981933 # Transaction distribution
system.membus.trans_dist::ReadExResp 981933 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11079181 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 11079181 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406965504 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 406965504 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6358836 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 6358836 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 6358836 # Request fanout histogram
system.membus.reqLayer0.occupancy 20942586092 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 44003891862 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 5.8 # Layer utilization (%)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
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