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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

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Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
sim_seconds 1.860198 # Number of seconds simulated
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
sim_ticks 1860197780500 # Number of ticks simulated
final_tick 1860197780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
host_inst_rate 103834 # Simulator instruction rate (inst/s)
host_op_rate 103834 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3645751305 # Simulator tick rate (ticks/s)
host_mem_usage 355004 # Number of bytes of host memory used
host_seconds 510.24 # Real time elapsed on the host
sim_insts 52979882 # Number of instructions simulated
sim_ops 52979882 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24878976 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytes_read::total 28495232 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7515456 # Number of bytes written to this memory
system.physmem.bytes_written::total 7515456 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388734 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.num_reads::total 445238 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 117429 # Number of write requests responded to by this memory
system.physmem.num_writes::total 117429 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 518207 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 13374371 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bw_read::total 15318388 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 518207 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 518207 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4040138 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4040138 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4040138 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 518207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 13374371 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bw_total::total 19358526 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 445238 # Number of read requests accepted
system.physmem.writeReqs 117429 # Number of write requests accepted
system.physmem.readBursts 445238 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 117429 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28492032 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 3200 # Total number of bytes read from write queue
system.physmem.bytesWritten 7514752 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28495232 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7515456 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.neitherReadNorWriteReqs 179 # Number of requests that are neither read nor write
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::0 28229 # Per bank write bursts
system.physmem.perBankRdBursts::1 27970 # Per bank write bursts
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.perBankRdBursts::2 28433 # Per bank write bursts
system.physmem.perBankRdBursts::3 28029 # Per bank write bursts
system.physmem.perBankRdBursts::4 27802 # Per bank write bursts
system.physmem.perBankRdBursts::5 27222 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::6 27248 # Per bank write bursts
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.perBankRdBursts::7 27296 # Per bank write bursts
system.physmem.perBankRdBursts::8 27665 # Per bank write bursts
system.physmem.perBankRdBursts::9 27395 # Per bank write bursts
system.physmem.perBankRdBursts::10 27922 # Per bank write bursts
system.physmem.perBankRdBursts::11 27539 # Per bank write bursts
system.physmem.perBankRdBursts::12 27561 # Per bank write bursts
system.physmem.perBankRdBursts::13 28227 # Per bank write bursts
system.physmem.perBankRdBursts::14 28327 # Per bank write bursts
system.physmem.perBankRdBursts::15 28323 # Per bank write bursts
system.physmem.perBankWrBursts::0 7932 # Per bank write bursts
system.physmem.perBankWrBursts::1 7497 # Per bank write bursts
system.physmem.perBankWrBursts::2 7944 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::3 7517 # Per bank write bursts
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.perBankWrBursts::4 7343 # Per bank write bursts
system.physmem.perBankWrBursts::5 6680 # Per bank write bursts
system.physmem.perBankWrBursts::6 6761 # Per bank write bursts
system.physmem.perBankWrBursts::7 6683 # Per bank write bursts
system.physmem.perBankWrBursts::8 7104 # Per bank write bursts
system.physmem.perBankWrBursts::9 6801 # Per bank write bursts
system.physmem.perBankWrBursts::10 7313 # Per bank write bursts
system.physmem.perBankWrBursts::11 6981 # Per bank write bursts
system.physmem.perBankWrBursts::12 7123 # Per bank write bursts
system.physmem.perBankWrBursts::13 7875 # Per bank write bursts
system.physmem.perBankWrBursts::14 8050 # Per bank write bursts
system.physmem.perBankWrBursts::15 7814 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
system.physmem.totGap 1860192344000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.readPktSize::6 445238 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.writePktSize::6 117429 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 332275 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 66533 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19911 # What read queue length does an incoming req see
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.rdQLenPdf::4 2385 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2335 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1391 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1359 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1343 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1445 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1259 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1090 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 974 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 957 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 955 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.wrQLenPdf::0 4574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4622 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4638 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5300 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 6023 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5386 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5393 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5529 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4863 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4881 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4845 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5670 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5759 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5781 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5838 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5862 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5034 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4942 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5452 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5842 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 43301 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 831.507817 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 237.255649 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1940.687281 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 14819 34.22% 34.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 6274 14.49% 48.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 4433 10.24% 58.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 2614 6.04% 64.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 1636 3.78% 68.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 1435 3.31% 72.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 928 2.14% 74.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 854 1.97% 76.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 632 1.46% 77.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 524 1.21% 78.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 594 1.37% 80.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 623 1.44% 81.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 284 0.66% 82.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 262 0.61% 82.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 268 0.62% 83.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 398 0.92% 84.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 204 0.47% 84.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 163 0.38% 85.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 93 0.21% 85.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 193 0.45% 85.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 100 0.23% 86.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 353 0.82% 87.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 186 0.43% 87.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 655 1.51% 88.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 89 0.21% 89.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 40 0.09% 89.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 175 0.40% 89.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 79 0.18% 90.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 82 0.19% 90.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 104 0.24% 90.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 16 0.04% 90.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 102 0.24% 91.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 26 0.06% 91.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 14 0.03% 91.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 2 0.00% 91.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 17 0.04% 91.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 4 0.01% 91.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 25 0.06% 91.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 100 0.23% 91.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 15 0.03% 91.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 67 0.15% 91.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 42 0.10% 92.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 83 0.19% 92.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 68 0.16% 92.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 12 0.03% 92.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 94 0.22% 92.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 9 0.02% 92.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 5 0.01% 92.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 4 0.01% 92.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 22 0.05% 92.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 92 0.21% 93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 13 0.03% 93.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 40 0.09% 93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 80 0.18% 93.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 95 0.22% 94.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 21 0.05% 94.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 10 0.02% 94.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 1 0.00% 94.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739 13 0.03% 94.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 14 0.03% 94.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995 68 0.16% 94.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 65 0.15% 95.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 98 0.23% 95.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507 10 0.02% 95.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5955 13 0.03% 95.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083 81 0.19% 96.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 41 0.09% 96.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211 82 0.19% 96.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275 69 0.16% 96.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6339 14 0.03% 96.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467 21 0.05% 97.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723 2 0.00% 97.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851 22 0.05% 97.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979 14 0.03% 97.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107 80 0.18% 97.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 307 0.71% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427 17 0.04% 98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7491 2 0.00% 98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683 5 0.01% 98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875 1 0.00% 98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 16 0.04% 98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 330 0.76% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.32% # Bytes accessed per row activation
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9408-9411 2 0.00% 99.34% # Bytes accessed per row activation
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11648-11651 2 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13315 4 0.01% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699 7 0.02% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 40 0.09% 99.57% # Bytes accessed per row activation
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811 2 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.59% # Bytes accessed per row activation
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 174 0.40% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 43301 # Bytes accessed per row activation
system.physmem.totQLat 8362787000 # Total ticks spent queuing
system.physmem.totMemAccLat 15768695750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2225940000 # Total ticks spent in databus transfers
system.physmem.totBankLat 5179968750 # Total ticks spent accessing banks
system.physmem.avgQLat 18784.84 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 11635.46 # Average bank access latency per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.avgMemAccLat 35420.31 # Average memory access latency per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.busUtil 0.15 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.physmem.avgWrQLen 11.24 # Average write queue length when enqueuing
system.physmem.readRowHits 424550 # Number of row buffer hits during reads
system.physmem.writeRowHits 94755 # Number of row buffer hits during writes
system.physmem.readRowHitRate 95.36 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.69 # Row buffer hit rate for writes
system.physmem.avgGap 3306027.09 # Average gap between requests
system.physmem.pageHitRate 92.30 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.39 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 19401389 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 295980 # Transaction distribution
system.membus.trans_dist::ReadResp 295901 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::WriteReq 9598 # Transaction distribution
system.membus.trans_dist::WriteResp 9598 # Transaction distribution
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.trans_dist::Writeback 117429 # Transaction distribution
system.membus.trans_dist::UpgradeReq 181 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.membus.trans_dist::UpgradeResp 182 # Transaction distribution
system.membus.trans_dist::ReadExReq 156823 # Transaction distribution
system.membus.trans_dist::ReadExResp 156823 # Transaction distribution
system.membus.trans_dist::BadAddressError 79 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884143 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917357 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.pkt_count::total 1042036 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701632 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745780 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.tot_pkt_size::total 36054836 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 36054836 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.reqLayer0.occupancy 29837500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.reqLayer1.occupancy 1551324500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.reqLayer2.occupancy 96500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.respLayer1.occupancy 3763216294 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.membus.respLayer2.occupancy 376313495 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.replacements 41685 # number of replacements
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.tags.tagsinuse 1.261116 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.tags.warmup_cycle 1710341603000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.261116 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.overall_misses::total 41725 # number of overall misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.WriteReq_miss_latency::tsunami.ide 12974928560 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 12974928560 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 12996062443 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 12996062443 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 12996062443 # number of overall miss cycles
system.iocache.overall_miss_latency::total 12996062443 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312257.618406 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 312257.618406 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 311469.441414 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 311469.441414 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 401483 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.blocked::no_mshrs 29284 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 13.709978 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10812648570 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 10812648570 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 10824785453 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 10824785453 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 10824785453 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 10824785453 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260219.690268 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 260219.690268 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.branchPred.lookups 13863448 # Number of BP lookups
system.cpu.branchPred.condPredicted 11631259 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 399718 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9400932 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5821857 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.branchPred.BTBHitPct 61.928509 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 906521 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 39211 # Number of incorrect RAS predictions.
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dtb.read_hits 9926517 # DTB read hits
system.cpu.dtb.read_misses 41406 # DTB read misses
system.cpu.dtb.read_acv 531 # DTB read access violations
system.cpu.dtb.read_accesses 940700 # DTB read accesses
system.cpu.dtb.write_hits 6593963 # DTB write hits
system.cpu.dtb.write_misses 10630 # DTB write misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dtb.write_acv 410 # DTB write access violations
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dtb.write_accesses 338096 # DTB write accesses
system.cpu.dtb.data_hits 16520480 # DTB hits
system.cpu.dtb.data_misses 52036 # DTB misses
system.cpu.dtb.data_acv 941 # DTB access violations
system.cpu.dtb.data_accesses 1278796 # DTB accesses
system.cpu.itb.fetch_hits 1306353 # ITB hits
system.cpu.itb.fetch_misses 36823 # ITB misses
system.cpu.itb.fetch_acv 1069 # ITB acv
system.cpu.itb.fetch_accesses 1343176 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.numCycles 121966998 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.icacheStallCycles 28067964 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 70813073 # Number of instructions fetch has processed
system.cpu.fetch.Branches 13863448 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 6728378 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 13263425 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1999195 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 38181411 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 255000 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 364206 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 297 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 8556045 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 264477 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 81457086 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.869330 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.212823 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.rateDist::0 68193661 83.72% 83.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 852857 1.05% 84.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1696439 2.08% 86.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 825181 1.01% 87.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2758325 3.39% 91.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 561473 0.69% 91.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 645881 0.79% 92.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1010308 1.24% 93.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 4912961 6.03% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.fetch.rateDist::total 81457086 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.113666 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.580592 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 29256938 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 37863691 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 12127839 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 959156 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1249461 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 584263 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 42640 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 69481989 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 129319 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1249461 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 30407522 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 14148846 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 20005990 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 11332374 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4312891 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 65679549 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 7211 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 504797 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1541440 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 43855166 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 79746051 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 79567055 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 166544 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 38180329 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 5674829 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1682909 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 240455 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12257327 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 10441163 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6908790 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1318239 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 851396 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 58211664 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2050007 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 56814932 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 114609 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 6922962 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3587498 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1389025 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 81457086 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.697483 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.359485 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.issued_per_cycle::0 56746030 69.66% 69.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 10887232 13.37% 83.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 5162469 6.34% 89.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3392471 4.16% 93.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 2625915 3.22% 96.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1461124 1.79% 98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 753330 0.92% 99.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 332031 0.41% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 96484 0.12% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.issued_per_cycle::total 81457086 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.fu_full::IntAlu 91940 11.62% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.62% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 373423 47.20% 58.82% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 325849 41.18% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.FU_type_0::IntAlu 38737583 68.18% 68.19% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 61738 0.11% 68.30% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 10357242 18.23% 86.58% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 6672763 11.74% 98.33% # Type of FU issued
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iq.FU_type_0::total 56814932 # Type of FU issued
system.cpu.iq.rate 0.465822 # Inst issue rate
system.cpu.iq.fu_busy_cnt 791212 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013926 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 195300199 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 66861892 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 55573336 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 692571 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 336551 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 327871 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 57237458 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 361400 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 598272 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 1348718 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3201 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 14139 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 530806 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 17937 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 182742 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.iewSquashCycles 1249461 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 10237116 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 702035 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 63785040 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 690324 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 10441163 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 6908790 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1805677 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 512237 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 17569 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14139 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 202047 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 411314 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 613361 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 56348369 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 9996094 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 466562 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.exec_nop 3523369 # number of nop insts executed
system.cpu.iew.exec_refs 16615920 # number of memory reference insts executed
system.cpu.iew.exec_branches 8927027 # Number of branches executed
system.cpu.iew.exec_stores 6619826 # Number of stores executed
system.cpu.iew.exec_rate 0.461997 # Inst execution rate
system.cpu.iew.wb_sent 56016387 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 55901207 # cumulative count of insts written-back
system.cpu.iew.wb_producers 27709617 # num instructions producing a value
system.cpu.iew.wb_consumers 37531222 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.iew.wb_rate 0.458331 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.738308 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.commitSquashedInsts 7496348 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 660982 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 568504 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 80207625 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.700316 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.629380 # Number of insts commited each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.committed_per_cycle::0 59390670 74.05% 74.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 8659340 10.80% 84.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4620197 5.76% 90.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2517886 3.14% 93.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1507376 1.88% 95.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 612052 0.76% 96.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 525608 0.66% 97.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 522089 0.65% 97.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1852407 2.31% 100.00% # Number of insts commited each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.committed_per_cycle::total 80207625 # Number of insts commited each cycle
system.cpu.commit.committedInsts 56170683 # Number of instructions committed
system.cpu.commit.committedOps 56170683 # Number of ops (including micro ops) committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.refs 15470429 # Number of memory references committed
system.cpu.commit.loads 9092445 # Number of loads committed
system.cpu.commit.membars 226358 # Number of memory barriers committed
system.cpu.commit.branches 8439899 # Number of branches committed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.commit.int_insts 52020266 # Number of committed integer instructions.
system.cpu.commit.function_calls 740581 # Number of function calls committed.
system.cpu.commit.bw_lim_events 1852407 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.rob.rob_reads 141772543 # The number of ROB reads
system.cpu.rob.rob_writes 128585215 # The number of ROB writes
system.cpu.timesIdled 1193212 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 40509912 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3598422122 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 52979882 # Number of Instructions Simulated
system.cpu.committedOps 52979882 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 52979882 # Number of Instructions Simulated
system.cpu.cpi 2.302138 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.302138 # CPI: Total CPI of All Threads
system.cpu.ipc 0.434379 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.434379 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 73881277 # number of integer regfile reads
system.cpu.int_regfile_writes 40316653 # number of integer regfile writes
system.cpu.fp_regfile_reads 166009 # number of floating regfile reads
system.cpu.fp_regfile_writes 167434 # number of floating regfile writes
system.cpu.misc_regfile_reads 1986207 # number of misc regfile reads
system.cpu.misc_regfile_writes 938984 # number of misc regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.iobus.throughput 1454553 # Throughput (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51150 # Transaction distribution
system.iobus.trans_dist::WriteResp 51150 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2705756 # Total data (bytes)
system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.reqLayer29.occupancy 377738948 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.respLayer1.occupancy 42679505 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.toL2Bus.throughput 111941811 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2118263 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2118167 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.toL2Bus.trans_dist::Writeback 840743 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 342536 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 300985 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020543 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677710 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 5698253 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64653440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143572596 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 208226036 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 208215988 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 17920 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 2480284498 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1518802860 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 2192631666 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.tags.replacements 1009602 # number of replacements
system.cpu.icache.tags.tagsinuse 509.660060 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 7489391 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1010110 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 7.414431 # Average number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 509.660060 # Average occupied blocks per requestor
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.ReadReq_hits::cpu.inst 7489392 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7489392 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7489392 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7489392 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7489392 # number of overall hits
system.cpu.icache.overall_hits::total 7489392 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1066652 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1066652 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1066652 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1066652 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1066652 # number of overall misses
system.cpu.icache.overall_misses::total 1066652 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14896343949 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14896343949 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14896343949 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14896343949 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14896343949 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14896343949 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 8556044 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 8556044 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 8556044 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 8556044 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 8556044 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 8556044 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124666 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.124666 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.124666 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.124666 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.124666 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.124666 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13965.514478 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13965.514478 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13965.514478 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13965.514478 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 4660 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 23.417085 # average number of cycles each access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56319 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 56319 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 56319 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 56319 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 56319 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 56319 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010333 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1010333 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1010333 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1010333 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1010333 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1010333 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12206065633 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12206065633 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12206065633 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12206065633 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12206065633 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12206065633 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118084 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118084 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118084 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.118084 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118084 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.118084 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.230281 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.230281 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.230281 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.230281 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.230281 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.230281 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.tags.replacements 338298 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65338.001327 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2546240 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 403465 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 6.310932 # Average number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.tags.warmup_cycle 5511908750 # Cycle when the warmup percentage was hit.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 53847.908430 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5309.513440 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6180.579458 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.821654 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081017 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.094308 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996979 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 995146 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 827013 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1822159 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 840743 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 840743 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 185570 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 185570 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 995146 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1012583 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2007729 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 995146 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1012583 # number of overall hits
system.cpu.l2cache.overall_hits::total 2007729 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 273814 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 288878 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 115414 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 115414 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 389228 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 404292 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 389228 # number of overall misses
system.cpu.l2cache.overall_misses::total 404292 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1218545993 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17819527728 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 19038073721 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262498 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 262498 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 22999 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 22999 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9547009857 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9547009857 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1218545993 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 27366537585 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 28585083578 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1218545993 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 27366537585 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 28585083578 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010210 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1100827 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2111037 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 840743 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 840743 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 300984 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 300984 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 1010210 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1401811 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2412021 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1010210 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1401811 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2412021 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014912 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248735 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.136842 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383456 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383456 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014912 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.277661 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.167615 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014912 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.277661 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.167615 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80891.263476 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65078.950412 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65903.508474 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 6907.842105 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6907.842105 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 22999 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 22999 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82719.686147 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82719.686147 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80891.263476 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70309.786513 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70704.054441 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80891.263476 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70309.786513 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70704.054441 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.writebacks::writebacks 75917 # number of writebacks
system.cpu.l2cache.writebacks::total 75917 # number of writebacks
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273814 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 288877 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115414 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 115414 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 389228 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 404291 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 389228 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 404291 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1028470757 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14406345772 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15434816529 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 532033 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 532033 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8124534143 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8124534143 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1028470757 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22530879915 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 23559350672 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1028470757 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22530879915 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 23559350672 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333940000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333940000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882589500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882589500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216529500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216529500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248735 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136841 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383456 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383456 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277661 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.167615 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014911 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277661 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.167615 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68277.949744 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52613.620092 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53430.409929 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14000.868421 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14000.868421 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70394.702055 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70394.702055 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68277.949744 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57886.071698 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58273.250386 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68277.949744 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57886.071698 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58273.250386 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.tags.replacements 1401219 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.994567 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 11810743 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1401731 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 8.425827 # Average number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit.
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.994567 # Average occupied blocks per requestor
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.ReadReq_hits::cpu.data 7205308 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7205308 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4203634 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4203634 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 186044 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 186044 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 215517 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 215517 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 11408942 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 11408942 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 11408942 # number of overall hits
system.cpu.dcache.overall_hits::total 11408942 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1806790 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1806790 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1944128 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1944128 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22738 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22738 # number of LoadLockedReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.demand_misses::cpu.data 3750918 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3750918 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3750918 # number of overall misses
system.cpu.dcache.overall_misses::total 3750918 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40335866684 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 40335866684 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 77256495609 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 77256495609 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322518001 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 322518001 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 39001 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 39001 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 117592362293 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 117592362293 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 117592362293 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 117592362293 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9012098 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9012098 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6147762 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6147762 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208782 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 208782 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215519 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 215519 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15159860 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15159860 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15159860 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15159860 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200485 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.200485 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316233 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.316233 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108908 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108908 # miss rate for LoadLockedReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.247424 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.247424 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.247424 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.247424 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22324.601467 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22324.601467 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39738.379165 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39738.379165 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14184.097150 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.097150 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31350.288727 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31350.288727 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 3041849 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.blocked::no_mshrs 98391 # number of cycles access was blocked
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.915927 # average number of cycles each access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.writebacks::writebacks 840743 # number of writebacks
system.cpu.dcache.writebacks::total 840743 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722826 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 722826 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643736 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1643736 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5220 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5220 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2366562 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2366562 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2366562 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2366562 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083964 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1083964 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300392 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 300392 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17518 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17518 # number of LoadLockedReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 1384356 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1384356 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1384356 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1384356 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27183263254 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27183263254 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11761438359 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11761438359 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200916999 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200916999 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34999 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34999 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38944701613 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 38944701613 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38944701613 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 38944701613 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424030000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424030000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997779498 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997779498 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421809498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421809498 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120279 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120279 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048862 # mshr miss rate for WriteReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.091317 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091317 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25077.643957 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25077.643957 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39153.633782 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39153.633782 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11469.174506 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11469.174506 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.kern.ipl_ticks::0 1818029044000 97.73% 97.73% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 64103000 0.00% 97.74% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 561251500 0.03% 97.77% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 41542545500 2.23% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1860196944000 # number of cycles we spent at this ipl
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.kern.syscall::total 326 # number of syscalls executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.kern.callpal::total 191976 # number of callpals executed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1910
system.cpu.kern.mode_good::user 1740
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.kern.mode_good::idle 170
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.kern.mode_ticks::kernel 29636227500 1.59% 1.59% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 2736556500 0.15% 1.74% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1827824152000 98.26% 100.00% # number of ticks spent at the given mode
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink