2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 0.085490 # Number of seconds simulated
sim_ticks 85490431000 # Number of ticks simulated
final_tick 85490431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-02-10 10:08:27 +01:00
host_inst_rate 128362 # Simulator instruction rate (inst/s)
host_op_rate 135315 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 63688458 # Simulator tick rate (ticks/s)
host_mem_usage 319620 # Number of bytes of host memory used
host_seconds 1342.32 # Real time elapsed on the host
2015-04-30 21:17:43 +02:00
sim_insts 172303022 # Number of instructions simulated
sim_ops 181635954 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.inst 587136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 132032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 70784 # Number of bytes read from this memory
system.physmem.bytes_read::total 789952 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 587136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 587136 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 9174 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2063 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 1106 # Number of read requests responded to by this memory
system.physmem.num_reads::total 12343 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 6867856 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1544407 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 827976 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9240239 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6867856 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6867856 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6867856 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1544407 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 827976 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9240239 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 12344 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2015-11-06 09:26:50 +01:00
system.physmem.readBursts 12344 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2015-11-06 09:26:50 +01:00
system.physmem.bytesReadDRAM 790016 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2015-11-06 09:26:50 +01:00
system.physmem.bytesReadSys 790016 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2014-09-20 23:18:53 +02:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2015-11-06 09:26:50 +01:00
system.physmem.perBankRdBursts::0 1112 # Per bank write bursts
system.physmem.perBankRdBursts::1 371 # Per bank write bursts
system.physmem.perBankRdBursts::2 5091 # Per bank write bursts
system.physmem.perBankRdBursts::3 435 # Per bank write bursts
system.physmem.perBankRdBursts::4 1954 # Per bank write bursts
system.physmem.perBankRdBursts::5 426 # Per bank write bursts
system.physmem.perBankRdBursts::6 266 # Per bank write bursts
system.physmem.perBankRdBursts::7 369 # Per bank write bursts
system.physmem.perBankRdBursts::8 265 # Per bank write bursts
system.physmem.perBankRdBursts::9 221 # Per bank write bursts
system.physmem.perBankRdBursts::10 295 # Per bank write bursts
system.physmem.perBankRdBursts::11 323 # Per bank write bursts
system.physmem.perBankRdBursts::12 197 # Per bank write bursts
system.physmem.perBankRdBursts::13 249 # Per bank write bursts
system.physmem.perBankRdBursts::14 227 # Per bank write bursts
system.physmem.perBankRdBursts::15 543 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-11-06 09:26:50 +01:00
system.physmem.totGap 85490422000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.readPktSize::6 12344 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::0 10928 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.bytesPerActivate::samples 7242 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 108.822977 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 85.142878 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 132.567115 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 5271 72.78% 72.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 1523 21.03% 93.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 185 2.55% 96.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 87 1.20% 97.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 38 0.52% 98.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 26 0.36% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 17 0.23% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 18 0.25% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 77 1.06% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 7242 # Bytes accessed per row activation
system.physmem.totQLat 167084529 # Total ticks spent queuing
system.physmem.totMemAccLat 398534529 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 61720000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13535.69 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-11-06 09:26:50 +01:00
system.physmem.avgMemAccLat 32285.69 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 9.24 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.avgRdBWSys 9.24 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.busUtil 0.07 # Data bus utilization in percentage
system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2015-11-06 09:26:50 +01:00
system.physmem.readRowHits 5095 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2015-11-06 09:26:50 +01:00
system.physmem.readRowHitRate 41.28 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgGap 6925666.07 # Average gap between requests
system.physmem.pageHitRate 41.28 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 48527640 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 26478375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 78156000 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_0.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 17009559810 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 36370632750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 59116834815 # Total energy per rank (pJ)
system.physmem_0.averagePower 691.542258 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 60400646468 # Time in different power states
system.physmem_0.memoryStateTime::REF 2854540000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::ACT 22233687032 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.actEnergy 6199200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3382500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 17869800 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
2015-11-06 09:26:50 +01:00
system.physmem_1.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 3325437855 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 48374248500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 57310618095 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.413332 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 80466021414 # Time in different power states
system.physmem_1.memoryStateTime::REF 2854540000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::ACT 2165082586 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.lookups 85927149 # Number of BP lookups
system.cpu.branchPred.condPredicted 68408695 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6018080 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 40104766 # Number of BTB lookups
system.cpu.branchPred.BTBHits 39018080 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.BTBHitPct 97.290382 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 3702096 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 81897 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
2015-11-06 09:26:50 +01:00
system.cpu.numCycles 170980863 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu.fetch.icacheStallCycles 5755157 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 349305240 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85927149 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 42720176 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 158448180 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 12049937 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 2618 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
2014-12-23 15:31:20 +01:00
system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions
2015-11-06 09:26:50 +01:00
system.cpu.fetch.IcacheWaitRetryStallCycles 3916 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 78960236 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 19348 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 170234862 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.146650 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.050166 # Number of instructions fetched each cycle (Total)
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::0 17669518 10.38% 10.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 30211265 17.75% 28.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 31838913 18.70% 46.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 90515166 53.17% 100.00% # Number of instructions fetched each cycle (Total)
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::total 170234862 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.502554 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.042949 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17700032 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 17289472 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 122672401 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 6722857 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 5850100 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 11135652 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 190021 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 306632940 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 27644957 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 5850100 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 37887834 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 8551246 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 582035 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 108933106 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 8430541 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 278671233 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 13418761 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 3051568 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 841704 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 2280860 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 35921 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 27095 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 483139430 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1196998780 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 297599206 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3005965 # Number of floating rename lookups
2014-09-03 13:42:59 +02:00
system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed
2015-11-06 09:26:50 +01:00
system.cpu.rename.UndoneMaps 190162501 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 23526 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 23429 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13338905 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 34139598 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 14476816 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2548575 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1784456 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 264827834 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 45856 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 214914585 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5192491 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 83237736 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 219939522 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 640 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 170234862 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.262459 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.017804 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::0 53140673 31.22% 31.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 36118420 21.22% 52.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 65796647 38.65% 91.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 13561298 7.97% 99.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1570362 0.92% 99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 47243 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 219 0.00% 100.00% # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::total 170234862 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::IntAlu 35603971 66.12% 66.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 152944 0.28% 66.40% # attempts to use FU when none available
2015-07-03 16:15:03 +02:00
system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.40% # attempts to use FU when none available
2015-04-30 21:17:43 +02:00
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::SimdFloatCmp 35746 0.07% 66.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.47% # attempts to use FU when none available
2015-07-03 16:15:03 +02:00
system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::SimdFloatMisc 952 0.00% 66.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 34296 0.06% 66.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.54% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 14072260 26.13% 92.67% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 3948482 7.33% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::IntAlu 167357330 77.87% 77.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 918980 0.43% 78.30% # Type of FU issued
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 245699 0.11% 78.51% # Type of FU issued
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::SimdFloatMisc 460522 0.21% 78.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::MemRead 32005177 14.89% 93.78% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 13374016 6.22% 100.00% # Type of FU issued
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::total 214914585 # Type of FU issued
system.cpu.iq.rate 1.256951 # Inst issue rate
system.cpu.iq.fu_busy_cnt 53850162 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.250565 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 655153476 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 346106935 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 204606292 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3953209 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2011310 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1806290 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 266630626 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2134121 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1600828 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 6243454 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 7546 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 6949 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1832182 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 25935 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 794 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewSquashCycles 5850100 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 5682962 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 61282 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 264889651 # Number of instructions dispatched to IQ
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewDispLoadInsts 34139598 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 14476816 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 23448 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3916 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 54251 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 6949 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3234598 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 6482716 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 207529725 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 30719767 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 7384860 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-11-06 09:26:50 +01:00
system.cpu.iew.exec_nop 15961 # number of nop insts executed
system.cpu.iew.exec_refs 43859608 # number of memory reference insts executed
system.cpu.iew.exec_branches 44936158 # Number of branches executed
system.cpu.iew.exec_stores 13139841 # Number of stores executed
system.cpu.iew.exec_rate 1.213760 # Inst execution rate
system.cpu.iew.wb_sent 206746993 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 206412582 # cumulative count of insts written-back
system.cpu.iew.wb_producers 129474820 # num instructions producing a value
system.cpu.iew.wb_consumers 221691878 # num instructions consuming a value
system.cpu.iew.wb_rate 1.207226 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.584031 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 69543013 # The number of squashed insts skipped by commit
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
2015-11-06 09:26:50 +01:00
system.cpu.commit.branchMispredicts 5843212 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 158791205 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.143957 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.645227 # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::0 73988497 46.59% 46.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 41295308 26.01% 72.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 22556711 14.21% 86.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 9630949 6.07% 92.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3552216 2.24% 95.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2148211 1.35% 96.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1284578 0.81% 97.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 986502 0.62% 97.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 3348233 2.11% 100.00% # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::total 158791205 # Number of insts commited each cycle
2015-04-30 21:17:43 +02:00
system.cpu.commit.committedInsts 172317410 # Number of instructions committed
system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 40540778 # Number of memory references committed
system.cpu.commit.loads 27896144 # Number of loads committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 22408 # Number of memory barriers committed
2015-04-30 21:17:43 +02:00
system.cpu.commit.branches 40300312 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 143085667 # Number of committed integer instructions.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.bw_lim_events 3348233 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 406631126 # The number of ROB reads
system.cpu.rob.rob_writes 513844376 # The number of ROB writes
system.cpu.timesIdled 8957 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 746001 # Total number of cycles that the CPU has spent unscheduled due to idling
2015-04-30 21:17:43 +02:00
system.cpu.committedInsts 172303022 # Number of Instructions Simulated
system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated
2015-11-06 09:26:50 +01:00
system.cpu.cpi 0.992327 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.992327 # CPI: Total CPI of All Threads
system.cpu.ipc 1.007733 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.007733 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 218966975 # number of integer regfile reads
system.cpu.int_regfile_writes 114516229 # number of integer regfile writes
system.cpu.fp_regfile_reads 2904204 # number of floating regfile reads
system.cpu.fp_regfile_writes 2441504 # number of floating regfile writes
system.cpu.cc_regfile_reads 709589080 # number of cc regfile reads
system.cpu.cc_regfile_writes 229556340 # number of cc regfile writes
system.cpu.misc_regfile_reads 59312089 # number of misc regfile reads
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.replacements 72854 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.416253 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 41114439 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 73366 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 560.401807 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 507537500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.416253 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.998860 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998860 # Average percentage of cache occupancy
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tag_accesses 82527906 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 82527906 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 28728233 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28728233 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12341290 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12341290 # number of WriteReq hits
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_hits::cpu.data 41069523 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41069523 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 41069884 # number of overall hits
system.cpu.dcache.overall_hits::total 41069884 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 89457 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 89457 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 22997 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 22997 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses
2015-07-03 16:15:03 +02:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_misses::cpu.data 112454 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 112454 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 112572 # number of overall misses
system.cpu.dcache.overall_misses::total 112572 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1065753500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 1065753500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 241354499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 241354499 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2315500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 2315500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 1307107999 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1307107999 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1307107999 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1307107999 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 28817690 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28817690 # number of ReadReq accesses(hits+misses)
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_accesses::cpu.data 41181977 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 41181977 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 41182456 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 41182456 # number of overall (read+write) accesses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8940.154440 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8940.154440 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 11623.490485 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 11611.306533 # average overall miss latency
2015-07-03 16:15:03 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked_cycles::no_targets 10450 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets 12.066975 # average number of cycles each access was blocked
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.dcache.writebacks::writebacks 72854 # number of writebacks
system.cpu.dcache.writebacks::total 72854 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24777 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 24777 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14426 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 14426 # number of WriteReq MSHR hits
2015-07-03 16:15:03 +02:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 39203 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 39203 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 39203 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 39203 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64680 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 64680 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8571 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 8571 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 73251 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 73251 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 73366 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 73366 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 654439000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 654439000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86279999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86279999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 978000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 978000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 740718999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 740718999 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 741696999 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 741696999 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002244 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002244 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001781 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8504.347826 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8504.347826 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643 # average overall mshr miss latency
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.replacements 54401 # number of replacements
system.cpu.icache.tags.tagsinuse 510.602972 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 78901806 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 54913 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1436.851128 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 84733597500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.602972 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tag_accesses 157975329 # Number of tag accesses
system.cpu.icache.tags.data_accesses 157975329 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 78901806 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78901806 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78901806 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 78901806 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 78901806 # number of overall hits
system.cpu.icache.overall_hits::total 78901806 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 58402 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 58402 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 58402 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 58402 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 58402 # number of overall misses
system.cpu.icache.overall_misses::total 58402 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1157058425 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1157058425 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1157058425 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1157058425 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1157058425 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1157058425 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 78960208 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 78960208 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 78960208 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 78960208 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 78960208 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 78960208 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000740 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000740 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000740 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000740 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000740 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000740 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19811.965772 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19811.965772 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19811.965772 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19811.965772 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 72401 # number of cycles access was blocked
2015-04-30 21:17:43 +02:00
system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.blocked::no_mshrs 3397 # number of cycles access was blocked
2015-04-30 21:17:43 +02:00
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 21.313218 # average number of cycles each access was blocked
2015-04-30 21:17:43 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 54401 # number of writebacks
system.cpu.icache.writebacks::total 54401 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3488 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 3488 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 3488 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 3488 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 3488 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54914 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 54914 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 54914 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 54914 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 54914 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 54914 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1043630451 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1043630451 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1043630451 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1043630451 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1043630451 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1043630451 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19004.815730 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.prefetcher.pfSpanPage 1359 # number of prefetches not generated due to page crossing
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.tagsinuse 2148.551192 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 159756 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3199 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 49.939356 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 1987.164357 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 161.386835 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.121287 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009850 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.131137 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 254 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2945 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 83 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 156 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 854 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1654 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179749 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3989175 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3989175 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 64840 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 64840 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 51941 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 51941 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 8403 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8403 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 45734 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 45734 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 62891 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 62891 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 45734 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 71294 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 117028 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 45734 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 71294 # number of overall hits
system.cpu.l2cache.overall_hits::total 117028 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 237 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 237 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9180 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 9180 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1835 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1835 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 9180 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2072 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 11252 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 9180 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2072 # number of overall misses
system.cpu.l2cache.overall_misses::total 11252 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 19043000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 19043000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 687767000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 687767000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 141031000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 141031000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 687767000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 160074000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 847841000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 687767000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 160074000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 847841000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 64840 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 64840 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 51941 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 51941 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 8640 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 8640 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54914 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 54914 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64726 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 64726 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 54914 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 73366 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 128280 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 54914 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 73366 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 128280 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027431 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.027431 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167170 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167170 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.028350 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.028350 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167170 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.028242 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.087714 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167170 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.028242 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.087714 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80350.210970 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80350.210970 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74920.152505 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74920.152505 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76856.130790 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76856.130790 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74920.152505 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77255.791506 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75350.248845 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74920.152505 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77255.791506 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75350.248845 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2046 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 2046 # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 236 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 236 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9175 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9175 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1827 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1827 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 9175 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2063 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 11238 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9175 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2063 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2046 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 13284 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 66908651 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 66908651 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17421000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17421000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 632417000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 632417000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 129587000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 129587000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 632417000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147008000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 779425000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 632417000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147008000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66908651 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 846333651 # number of overall MSHR miss cycles
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027315 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027315 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167079 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028227 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028227 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.087605 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for overall accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.103555 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464 # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 255535 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 127274 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 11941 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.trans_dist::WritebackClean 62415 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::CleanEvict 11001 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 2383 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 8640 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 8640 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 54914 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 64726 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 164228 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 219586 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 383814 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6996096 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9358080 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 16354176 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoops 13384 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 141664 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.218517 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.539520 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::0 119230 84.16% 84.16% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 13912 9.82% 93.98% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 8522 6.02% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 141664 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 255022500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 82377983 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 110053990 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadResp 12107 # Transaction distribution
system.membus.trans_dist::ReadExReq 236 # Transaction distribution
system.membus.trans_dist::ReadExResp 236 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 12108 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24687 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 24687 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 789952 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 789952 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::samples 12344 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::0 12344 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 12344 # Request fanout histogram
system.membus.reqLayer0.occupancy 15598659 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.respLayer1.occupancy 66476550 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
