2011-01-18 23:30:06 +01:00
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---------- Begin Simulation Statistics ----------
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2014-01-24 22:29:34 +01:00
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sim_seconds 0.026912 # Number of seconds simulated
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sim_ticks 26911921000 # Number of ticks simulated
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final_tick 26911921000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-01-18 23:30:06 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2014-01-24 22:29:34 +01:00
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host_inst_rate 176190 # Simulator instruction rate (inst/s)
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host_op_rate 177456 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 52341651 # Simulator tick rate (ticks/s)
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host_mem_usage 402844 # Number of bytes of host memory used
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host_seconds 514.16 # Real time elapsed on the host
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2013-01-08 14:54:16 +01:00
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sim_insts 90589798 # Number of instructions simulated
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sim_ops 91240351 # Number of ops (including micro ops) simulated
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2014-01-24 22:29:33 +01:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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2014-01-24 22:29:34 +01:00
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system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 947776 # Number of bytes read from this memory
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system.physmem.bytes_read::total 993280 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 14809 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1690849 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 35217701 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 36908551 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1690849 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1690849 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1690849 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 35217701 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 36908551 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15520 # Number of read requests accepted
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2013-11-01 16:56:34 +01:00
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system.physmem.writeReqs 0 # Number of write requests accepted
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2014-01-24 22:29:34 +01:00
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system.physmem.readBursts 15520 # Number of DRAM read bursts, including those serviced by the write queue
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2013-11-01 16:56:34 +01:00
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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2014-01-24 22:29:34 +01:00
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system.physmem.bytesReadDRAM 993280 # Total number of bytes read from DRAM
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2013-11-01 16:56:34 +01:00
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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2014-01-24 22:29:34 +01:00
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system.physmem.bytesReadSys 993280 # Total read bytes from the system interface side
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2013-11-01 16:56:34 +01:00
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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2013-11-27 00:05:25 +01:00
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system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
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2014-01-24 22:29:34 +01:00
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system.physmem.perBankRdBursts::0 989 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.perBankRdBursts::1 886 # Per bank write bursts
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2013-11-27 00:05:25 +01:00
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system.physmem.perBankRdBursts::2 942 # Per bank write bursts
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2014-01-24 22:29:34 +01:00
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system.physmem.perBankRdBursts::3 1029 # Per bank write bursts
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system.physmem.perBankRdBursts::4 1049 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.perBankRdBursts::5 1105 # Per bank write bursts
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2014-01-24 22:29:34 +01:00
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system.physmem.perBankRdBursts::6 1079 # Per bank write bursts
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system.physmem.perBankRdBursts::7 1079 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
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2013-11-27 00:05:25 +01:00
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system.physmem.perBankRdBursts::9 959 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.perBankRdBursts::10 938 # Per bank write bursts
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system.physmem.perBankRdBursts::11 899 # Per bank write bursts
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system.physmem.perBankRdBursts::12 904 # Per bank write bursts
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system.physmem.perBankRdBursts::13 865 # Per bank write bursts
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system.physmem.perBankRdBursts::14 877 # Per bank write bursts
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system.physmem.perBankRdBursts::15 896 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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2014-01-24 22:29:34 +01:00
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system.physmem.totGap 26911727500 # Total gap between requests
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2013-11-01 16:56:34 +01:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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2014-01-24 22:29:34 +01:00
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system.physmem.readPktSize::6 15520 # Read request sizes (log2)
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2013-11-01 16:56:34 +01:00
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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2014-01-24 22:29:34 +01:00
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system.physmem.rdQLenPdf::0 11175 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 4158 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see
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2013-11-01 16:56:34 +01:00
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system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
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2013-05-30 18:54:18 +02:00
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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2012-10-30 14:35:32 +01:00
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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2014-01-24 22:29:34 +01:00
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system.physmem.bytesPerActivate::samples 622 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 1591.562701 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 476.433802 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 2197.906875 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-65 160 25.72% 25.72% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-129 68 10.93% 36.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-193 41 6.59% 43.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-257 21 3.38% 46.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-321 13 2.09% 48.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-385 6 0.96% 49.68% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-449 27 4.34% 54.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-513 12 1.93% 55.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-577 5 0.80% 56.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-641 10 1.61% 58.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-705 3 0.48% 58.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-769 4 0.64% 59.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-833 5 0.80% 60.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-897 8 1.29% 61.58% # Bytes accessed per row activation
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|
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system.physmem.bytesPerActivate::960-961 3 0.48% 62.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1089 6 0.96% 63.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1217 2 0.32% 64.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1409 4 0.64% 65.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1473 6 0.96% 66.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1537 19 3.05% 69.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1601 6 0.96% 70.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1665 6 0.96% 71.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792-1793 3 0.48% 72.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048-2049 6 0.96% 73.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176-2177 6 0.96% 74.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.40% # Bytes accessed per row activation
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|
|
system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.88% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::2560-2561 1 0.16% 76.05% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.37% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.53% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::2752-2753 5 0.80% 77.33% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::2816-2817 4 0.64% 77.97% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.30% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.78% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3072-3073 4 0.64% 79.42% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.74% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3200-3201 2 0.32% 80.06% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.39% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.87% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3456-3457 1 0.16% 81.03% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.35% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.51% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.99% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.48% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.80% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.96% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.12% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.28% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.76% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.08% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.24% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.73% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4480-4481 4 0.64% 85.37% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4544-4545 4 0.64% 86.01% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.17% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.66% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.98% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.30% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.46% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.78% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.94% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.26% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5120-5121 5 0.80% 89.07% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.55% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5248-5249 4 0.64% 90.19% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.51% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5440-5441 6 0.96% 91.48% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.96% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.12% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.28% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.44% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.60% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.09% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.25% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.57% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.73% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.05% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.53% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.69% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6528-6529 2 0.32% 95.02% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.18% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.66% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.82% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.98% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.14% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.30% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.46% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.78% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.95% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.11% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.27% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.43% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.59% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.75% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.07% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::8192-8193 12 1.93% 100.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::total 622 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.totQLat 103005000 # Total ticks spent queuing
|
|
|
|
|
system.physmem.totMemAccLat 356453750 # Total ticks spent from burst creation until serviced by the DRAM
|
|
|
|
|
system.physmem.totBusLat 77600000 # Total ticks spent in databus transfers
|
|
|
|
|
system.physmem.totBankLat 175848750 # Total ticks spent accessing banks
|
|
|
|
|
system.physmem.avgQLat 6636.92 # Average queueing delay per DRAM burst
|
|
|
|
|
system.physmem.avgBankLat 11330.46 # Average bank access latency per DRAM burst
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2014-01-24 22:29:34 +01:00
|
|
|
system.physmem.avgMemAccLat 22967.38 # Average memory access latency per DRAM burst
|
|
|
|
|
system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
2014-01-24 22:29:34 +01:00
|
|
|
system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
|
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
2013-01-31 13:49:16 +01:00
|
|
|
system.physmem.busUtil 0.29 # Data bus utilization in percentage
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
|
|
|
|
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
|
|
|
|
system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
|
|
|
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
2014-01-24 22:29:34 +01:00
|
|
|
system.physmem.readRowHits 14898 # Number of row buffer hits during reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
2014-01-24 22:29:34 +01:00
|
|
|
system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
2014-01-24 22:29:34 +01:00
|
|
|
system.physmem.avgGap 1734003.06 # Average gap between requests
|
|
|
|
|
system.physmem.pageHitRate 95.99 # Row buffer hit rate, read and write combined
|
|
|
|
|
system.physmem.prechargeAllPercent 0.99 # Percentage of time for which DRAM has all the banks in precharge state
|
|
|
|
|
system.membus.throughput 36908551 # Throughput (bytes/s)
|
|
|
|
|
system.membus.trans_dist::ReadReq 982 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 982 # Transaction distribution
|
2013-11-27 00:05:25 +01:00
|
|
|
system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
|
2014-01-24 22:29:34 +01:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31042 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 31042 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993280 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.tot_pkt_size::total 993280 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.data_through_bus 993280 # Total data (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.membus.reqLayer0.occupancy 19254500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.membus.respLayer1.occupancy 145212249 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.branchPred.lookups 26683530 # Number of BP lookups
|
|
|
|
|
system.cpu.branchPred.condPredicted 22001633 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.branchPred.condIncorrect 843091 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.branchPred.BTBLookups 11366562 # Number of BTB lookups
|
|
|
|
|
system.cpu.branchPred.BTBHits 11283436 # Number of BTB hits
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.branchPred.BTBHitPct 99.268679 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branchPred.usedRAS 69998 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.branchPred.RASInCorrect 165 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.numCycles 53823843 # number of cpu cycles simulated
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.fetch.icacheStallCycles 14173676 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 127895760 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 26683530 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 11353434 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 24037387 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 4765940 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.BlockedCycles 11314746 # Number of cycles fetch has spent blocked
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
|
|
|
|
|
system.cpu.fetch.CacheLines 13845039 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 329540 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 53432137 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.410093 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.214797 # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.fetch.rateDist::0 29433098 55.09% 55.09% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 3389468 6.34% 61.43% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 2029496 3.80% 65.23% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 1553729 2.91% 68.13% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 1668795 3.12% 71.26% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 2919650 5.46% 76.72% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 1509735 2.83% 79.55% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 1090422 2.04% 81.59% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 9837744 18.41% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.fetch.rateDist::total 53432137 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.495757 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 2.376192 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 16937041 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 9161066 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 22405812 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 1030640 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 3897578 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 4444113 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 8703 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 126077551 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 42669 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 3897578 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 18718868 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 3591285 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 186478 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 21552610 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 5485318 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 123153621 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 426233 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LSQFullEvents 4596906 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.FullRegisterEvents 1480 # Number of times there has been no free registers
|
|
|
|
|
system.cpu.rename.RenamedOperands 143604331 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 536493258 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 499981919 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 760 # Number of floating rename lookups
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.rename.UndoneMaps 36190145 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 4605 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 4603 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 12541075 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 29476574 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 5520683 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 2151148 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 1293650 # Number of conflicting stores.
|
|
|
|
|
system.cpu.iq.iqInstsAdded 118168195 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 8471 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 105168426 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 79356 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 26740210 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 65568590 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 53432137 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 1.968262 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.908954 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::0 15374181 28.77% 28.77% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 11650585 21.80% 50.58% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 8250698 15.44% 66.02% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 6826591 12.78% 78.80% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 4953996 9.27% 88.07% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 2948586 5.52% 93.59% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 2456814 4.60% 98.18% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 528614 0.99% 99.17% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 442072 0.83% 100.00% # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 53432137 # Number of insts issued each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.fu_full::IntAlu 45737 6.91% 6.91% # attempts to use FU when none available
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.fu_full::MemRead 340297 51.45% 58.36% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 275411 41.64% 100.00% # attempts to use FU when none available
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 74430007 70.77% 70.77% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 10980 0.01% 70.78% # Type of FU issued
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 130 0.00% 70.78% # Type of FU issued
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 172 0.00% 70.78% # Type of FU issued
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.FU_type_0::MemRead 25613380 24.35% 95.14% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 5113753 4.86% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 105168426 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 1.953938 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 661472 # FU busy when requested
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.int_inst_queue_reads 264509133 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 144921601 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 102693545 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 684 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 985 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 281 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 105829562 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 441614 # Number of loads that had data forwarded from stores
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 6902608 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6756 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 6465 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 775839 # Number of stores squashed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 31615 # Number of times an access to memory failed due to the cache being blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 3897578 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 958412 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 126923 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 118189357 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 310100 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 29476574 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 5520683 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 4583 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 65855 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 6705 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 6465 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 447219 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 445977 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 893196 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 104191790 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 25292626 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 976636 # Number of squashed instructions skipped in execute
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iew.exec_nop 12691 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 30349836 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 21326689 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 5057210 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 1.935792 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 102971901 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 102693826 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 62250392 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 104309215 # num instructions consuming a value
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iew.wb_rate 1.907962 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.596787 # average fanout of values written-back
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 26939334 # The number of squashed insts skipped by commit
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.commit.branchMispredicts 834485 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 49534559 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 1.842208 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.540547 # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 20043988 40.46% 40.46% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 13146531 26.54% 67.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 4167490 8.41% 75.42% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 3431351 6.93% 82.35% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 1535298 3.10% 85.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 726633 1.47% 86.91% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 954931 1.93% 88.84% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 253243 0.51% 89.35% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 5275094 10.65% 100.00% # Number of insts commited each cycle
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 49534559 # Number of insts commited each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.refs 27318810 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 22573966 # Number of loads committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.membars 3888 # Number of memory barriers committed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.branches 18732304 # Number of branches committed
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.commit.bw_lim_events 5275094 # number cycles where commit BW limit reached
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.rob.rob_reads 162446025 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 240301749 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 46102 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 391706 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.cpi 0.594149 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.594149 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.683079 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.683079 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 495606364 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 120553547 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 143 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 349 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 29209842 # number of misc regfile reads
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.toL2Bus.throughput 4497544713 # Throughput (bytes/s)
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 904632 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 904632 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 942884 # Transaction distribution
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 43696 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 43696 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1476 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838066 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 2839542 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47168 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120990272 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size::total 121037440 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.data_through_bus 121037440 # Total data (bytes)
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 1888491000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1225749 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1424096491 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.replacements 3 # number of replacements
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.icache.tags.tagsinuse 632.652083 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 13844045 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 737 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 18784.321574 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 632.652083 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.308912 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.308912 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 734 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.358398 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.icache.tags.tag_accesses 27690815 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 27690815 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 13844045 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 13844045 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 13844045 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 13844045 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 13844045 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 13844045 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 993 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 993 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 993 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 993 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 993 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 993 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 66969998 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 66969998 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 66969998 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 66969998 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 66969998 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 66969998 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 13845038 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 13845038 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 13845038 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 13845038 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 13845038 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 13845038 # number of overall (read+write) accesses
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67442.092649 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 67442.092649 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 67442.092649 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 67442.092649 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 594 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 59.400000 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 739 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 739 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50789000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 50789000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50789000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 50789000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50789000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 50789000 # number of overall MSHR miss cycles
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68726.657645 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68726.657645 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68726.657645 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 68726.657645 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68726.657645 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 68726.657645 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.tags.tagsinuse 10731.098995 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 1831378 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 15503 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 118.130555 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 9880.580291 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 618.669492 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 231.849212 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.301531 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018880 # Average percentage of cache occupancy
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007075 # Average percentage of cache occupancy
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.327487 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15503 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 515 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1301 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13618 # Occupied blocks per task id
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.473114 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 15188896 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 15188896 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 903612 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 903637 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 942884 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 942884 # number of Writeback hits
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 29158 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 29158 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 932770 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 932795 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 932770 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 932795 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 712 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 993 # number of ReadReq misses
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 712 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 14819 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 15531 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 712 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 14819 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 15531 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49793250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21247250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 71040500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 962911000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 962911000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 49793250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 984158250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 1033951500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 49793250 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 984158250 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 1033951500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 737 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 903893 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 904630 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 942884 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 942884 # number of Writeback accesses(hits+misses)
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43696 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 43696 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 737 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 947589 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 948326 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 737 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 947589 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 948326 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.966079 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000311 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.001098 # miss rate for ReadReq accesses
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.332708 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.332708 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966079 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015639 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.016377 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966079 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015639 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.016377 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69934.339888 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75612.989324 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71541.289023 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66234.076214 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66234.076214 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69934.339888 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66411.920507 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 66573.401584 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69934.339888 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66411.920507 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 66573.401584 # average overall miss latency
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 711 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 982 # number of ReadReq MSHR misses
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 711 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 14809 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 15520 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 711 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 14809 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 15520 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40836000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17269250 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58105250 # number of ReadReq MSHR miss cycles
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 780533500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 780533500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40836000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 797802750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 838638750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40836000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 797802750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 838638750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000300 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001086 # mshr miss rate for ReadReq accesses
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332708 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332708 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016366 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016366 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57434.599156 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63724.169742 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59170.315682 # average ReadReq mshr miss latency
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53689.193837 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53689.193837 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57434.599156 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53872.830711 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54036.001933 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57434.599156 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53872.830711 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54036.001933 # average overall mshr miss latency
|
2011-05-23 17:59:13 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.tags.replacements 943493 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 3671.741279 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 28144387 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 947589 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 29.701049 # Average number of references to valid blocks.
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit.
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 3671.741279 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.896421 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.896421 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 445 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3140 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.tags.tag_accesses 59988391 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 59988391 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23603738 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 23603738 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4532850 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 4532850 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3905 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3905 # number of LoadLockedReq hits
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 28136588 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 28136588 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 28136588 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 28136588 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1173883 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 1173883 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 202131 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 202131 # number of WriteReq misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 1376014 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 1376014 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 1376014 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 1376014 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893935229 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 13893935229 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8459874583 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 8459874583 # number of WriteReq miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 22353809812 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 22353809812 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 22353809812 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 22353809812 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 24777621 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 24777621 # number of ReadReq accesses(hits+misses)
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3912 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3912 # number of LoadLockedReq accesses(hits+misses)
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 29512602 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 29512602 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 29512602 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 29512602 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047377 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.047377 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042689 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.042689 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.877365 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.877365 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41853.424675 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41853.424675 # average WriteReq miss latency
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 16245.336030 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 16245.336030 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 154233 # number of cycles access was blocked
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.439522 # average number of cycles each access was blocked
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 942884 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269973 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 269973 # number of ReadReq MSHR hits
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 428423 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 428423 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 428423 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 428423 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903910 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 903910 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43681 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 43681 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 947591 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 947591 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 947591 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 947591 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994274260 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994274260 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319346668 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319346668 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313620928 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 11313620928 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313620928 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 11313620928 # number of overall MSHR miss cycles
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses
|
2013-11-27 00:05:25 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.713899 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.713899 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30204.131499 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30204.131499 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
