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gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt

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config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
sim_seconds 0.023455 # Number of seconds simulated
sim_ticks 23455364500 # Number of ticks simulated
final_tick 23455364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
host_inst_rate 164985 # Simulator instruction rate (inst/s)
host_op_rate 164985 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45970553 # Simulator tick rate (ticks/s)
host_mem_usage 272156 # Number of bytes of host memory used
host_seconds 510.23 # Real time elapsed on the host
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
sim_insts 84179709 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 84179709 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory
system.physmem.bytes_read::total 334592 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bw_read::cpu.inst 8354933 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5910119 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14265052 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8354933 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8354933 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8354933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5910119 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 14265052 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readReqs 5228 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankRdBursts::0 469 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::1 290 # Per bank write bursts
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankRdBursts::2 301 # Per bank write bursts
system.physmem.perBankRdBursts::3 519 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::4 220 # Per bank write bursts
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankRdBursts::5 227 # Per bank write bursts
system.physmem.perBankRdBursts::6 220 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::7 288 # Per bank write bursts
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankRdBursts::8 236 # Per bank write bursts
system.physmem.perBankRdBursts::9 278 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::10 248 # Per bank write bursts
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankRdBursts::11 255 # Per bank write bursts
system.physmem.perBankRdBursts::12 401 # Per bank write bursts
system.physmem.perBankRdBursts::13 338 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::14 491 # Per bank write bursts
system.physmem.perBankRdBursts::15 447 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.totGap 23455237500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 5228 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1321 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 339 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 526.348083 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 311.933424 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 425.197716 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 81 23.89% 23.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 64 18.88% 42.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 21 6.19% 48.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 17 5.01% 53.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 9 2.65% 56.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 8 2.36% 59.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7 2.06% 61.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 0.88% 61.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 129 38.05% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 339 # Bytes accessed per row activation
system.physmem.totQLat 42838250 # Total ticks spent queuing
system.physmem.totMemAccLat 141220750 # Total ticks spent from burst creation until serviced by the DRAM
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.totBankLat 72242500 # Total ticks spent accessing banks
system.physmem.avgQLat 8194.00 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 13818.38 # Average bank access latency per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgMemAccLat 27012.39 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 14.27 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgRdBWSys 14.27 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.busUtil 0.11 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.readRowHits 4346 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.readRowHitRate 83.13 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgGap 4486464.71 # Average gap between requests
system.physmem.pageHitRate 83.13 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 1.10 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 14265052 # Throughput (bytes/s)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.trans_dist::ReadReq 3523 # Transaction distribution
system.membus.trans_dist::ReadResp 3523 # Transaction distribution
system.membus.trans_dist::ReadExReq 1705 # Transaction distribution
system.membus.trans_dist::ReadExResp 1705 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 334592 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.reqLayer0.occupancy 6760500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.respLayer1.occupancy 48963750 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.branchPred.lookups 14848335 # Number of BP lookups
system.cpu.branchPred.condPredicted 10770516 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 922016 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8296689 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6955595 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.branchPred.BTBHitPct 83.835793 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1468520 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3112 # Number of incorrect RAS predictions.
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dtb.read_hits 23116922 # DTB read hits
system.cpu.dtb.read_misses 193562 # DTB read misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dtb.read_acv 4 # DTB read access violations
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dtb.read_accesses 23310484 # DTB read accesses
system.cpu.dtb.write_hits 7068693 # DTB write hits
system.cpu.dtb.write_misses 1118 # DTB write misses
system.cpu.dtb.write_acv 2 # DTB write access violations
system.cpu.dtb.write_accesses 7069811 # DTB write accesses
system.cpu.dtb.data_hits 30185615 # DTB hits
system.cpu.dtb.data_misses 194680 # DTB misses
system.cpu.dtb.data_acv 6 # DTB access violations
system.cpu.dtb.data_accesses 30380295 # DTB accesses
system.cpu.itb.fetch_hits 14732180 # ITB hits
system.cpu.itb.fetch_misses 100 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.itb.fetch_accesses 14732280 # ITB accesses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.numCycles 46910730 # number of cpu cycles simulated
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.fetch.icacheStallCycles 15458006 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 126949517 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14848335 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 8424115 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 22129467 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4471319 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 5547804 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2176 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 14732180 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 325492 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 46652781 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.721156 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.376288 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.fetch.rateDist::0 24523314 52.57% 52.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2362460 5.06% 57.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1191709 2.55% 60.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1744531 3.74% 63.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2756035 5.91% 69.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1149513 2.46% 72.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1216156 2.61% 74.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 771099 1.65% 76.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 10937964 23.45% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.fetch.rateDist::total 46652781 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.316523 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.706194 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17279755 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 4249359 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 20525557 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1094653 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3503457 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 2516236 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12079 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 123971467 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 32460 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3503457 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 18421615 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 960025 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 8092 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20456033 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3303559 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 121144333 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 398869 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2427038 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 88958437 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 157404324 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 150359413 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 7044910 # Number of floating rename lookups
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.rename.UndoneMaps 20531076 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 753 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 746 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 8762869 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 25364686 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 8245053 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2579677 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 916866 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 105436349 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1901 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 96572685 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 177506 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 20788885 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 15603704 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1512 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 46652781 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.070031 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.877189 # Number of insts issued each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.issued_per_cycle::0 12130850 26.00% 26.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 9330795 20.00% 46.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8389374 17.98% 63.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6281972 13.47% 77.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4924466 10.56% 88.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2864469 6.14% 94.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1724344 3.70% 97.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 801135 1.72% 99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 205376 0.44% 100.00% # Number of insts issued each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.issued_per_cycle::total 46652781 # Number of insts issued each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.fu_full::IntAlu 187827 11.99% 11.99% # attempts to use FU when none available
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.99% # attempts to use FU when none available
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.fu_full::FloatAdd 195 0.01% 12.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 7087 0.45% 12.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 5615 0.36% 12.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 842803 53.78% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 445934 28.46% 95.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 77665 4.96% 100.00% # attempts to use FU when none available
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::IntAlu 58739096 60.82% 60.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 479860 0.50% 61.32% # Type of FU issued
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::FloatAdd 2798014 2.90% 64.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 115391 0.12% 64.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2386555 2.47% 66.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 310970 0.32% 67.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 759904 0.79% 67.92% # Type of FU issued
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::MemRead 23830824 24.68% 92.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 7151745 7.41% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iq.FU_type_0::total 96572685 # Type of FU issued
system.cpu.iq.rate 2.058648 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1567126 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016227 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 226432918 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 117523015 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 87074868 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15109865 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 8738386 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7061397 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 90154911 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7984893 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1517468 # Number of loads that had data forwarded from stores
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 5368488 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 18513 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 34393 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1743950 # Number of stores squashed
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 10556 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 2089 # Number of times an access to memory failed due to the cache being blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.iewSquashCycles 3503457 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 134155 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17977 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 115673905 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 371989 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 25364686 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 8245053 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1901 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2671 # Number of times the IQ has become full, causing a stall
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.memOrderViolationEvents 34393 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 533358 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 495038 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1028396 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 95341973 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 23310954 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1230712 # Number of squashed instructions skipped in execute
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.exec_nop 10235655 # number of nop insts executed
system.cpu.iew.exec_refs 30380968 # number of memory reference insts executed
system.cpu.iew.exec_branches 12023807 # Number of branches executed
system.cpu.iew.exec_stores 7070014 # Number of stores executed
system.cpu.iew.exec_rate 2.032413 # Inst execution rate
system.cpu.iew.wb_sent 94656410 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 94136265 # cumulative count of insts written-back
system.cpu.iew.wb_producers 64475750 # num instructions producing a value
system.cpu.iew.wb_consumers 89852391 # num instructions consuming a value
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.iew.wb_rate 2.006711 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.717574 # average fanout of values written-back
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.commitSquashedInsts 23771863 # The number of squashed insts skipped by commit
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.branchMispredicts 910264 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 43149324 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.129884 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.746526 # Number of insts commited each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.committed_per_cycle::0 16704227 38.71% 38.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 9920088 22.99% 61.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4481212 10.39% 72.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2253745 5.22% 77.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1606057 3.72% 81.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1123881 2.60% 83.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 722151 1.67% 85.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 820935 1.90% 87.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5517028 12.79% 100.00% # Number of insts commited each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.committed_per_cycle::total 43149324 # Number of insts commited each cycle
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 26497301 # Number of memory references committed
system.cpu.commit.loads 19996198 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 10240685 # Number of branches committed
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.commit.bw_lim_events 5517028 # number cycles where commit BW limit reached
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.rob.rob_reads 153306174 # The number of ROB reads
system.cpu.rob.rob_writes 234877097 # The number of ROB writes
system.cpu.timesIdled 5272 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 257949 # Total number of cycles that the CPU has spent unscheduled due to idling
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.cpi 0.557269 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.557269 # CPI: Total CPI of All Threads
system.cpu.ipc 1.794466 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.794466 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 129050731 # number of integer regfile reads
system.cpu.int_regfile_writes 70522819 # number of integer regfile writes
system.cpu.fp_regfile_reads 6187407 # number of floating regfile reads
system.cpu.fp_regfile_writes 6043154 # number of floating regfile writes
system.cpu.misc_regfile_reads 714454 # number of misc regfile reads
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.throughput 37351626 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 11849 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 11849 # Transaction distribution
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22666 # Packet count per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.pkt_count::total 27269 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725312 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150784 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.tot_pkt_size::total 876096 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 876096 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.reqLayer0.occupancy 6953500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 17562000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3539750 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.tags.replacements 9398 # number of replacements
system.cpu.icache.tags.tagsinuse 1599.250917 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 14718111 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 11333 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1298.695050 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1599.250917 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.780884 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.780884 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1935 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 929 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.944824 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 29475691 # Number of tag accesses
system.cpu.icache.tags.data_accesses 29475691 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 14718111 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14718111 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14718111 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14718111 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14718111 # number of overall hits
system.cpu.icache.overall_hits::total 14718111 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 14068 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 14068 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 14068 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 14068 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 14068 # number of overall misses
system.cpu.icache.overall_misses::total 14068 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 413989500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 413989500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 413989500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 413989500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 413989500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 413989500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 14732179 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 14732179 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 14732179 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 14732179 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 14732179 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 14732179 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000955 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000955 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000955 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000955 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000955 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29427.743816 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 29427.743816 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 29427.743816 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 29427.743816 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 165 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 41.250000 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2735 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2735 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2735 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2735 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2735 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2735 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11333 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 11333 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 11333 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 11333 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 11333 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 11333 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305304500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 305304500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305304500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 305304500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305304500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 305304500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000769 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000769 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000769 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000769 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000769 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000769 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26939.424689 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26939.424689 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26939.424689 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 26939.424689 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26939.424689 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 26939.424689 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.tags.tagsinuse 2413.657208 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8341 # Total number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.tags.sampled_refs 3590 # Sample count of references to valid blocks.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.tags.avg_refs 2.323398 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 17.675331 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2012.279201 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 383.702676 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061410 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011710 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.073659 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3590 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 904 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2435 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109558 # Percentage of cache occupancy per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.tags.tag_accesses 114833 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 114833 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 8271 # number of ReadReq hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.ReadReq_hits::total 8326 # number of ReadReq hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_hits::cpu.inst 8271 # number of demand (read+write) hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_hits::total 8352 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 8271 # number of overall hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.overall_hits::total 8352 # number of overall hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 3062 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 461 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3523 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1705 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1705 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3062 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2166 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5228 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2166 # number of overall misses
system.cpu.l2cache.overall_misses::total 5228 # number of overall misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 211253500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 36622500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 247876000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125606750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 125606750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 211253500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 162229250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 373482750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 211253500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 162229250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 373482750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11333 # number of ReadReq accesses(hits+misses)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.data 516 # number of ReadReq accesses(hits+misses)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.ReadReq_accesses::total 11849 # number of ReadReq accesses(hits+misses)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_accesses::cpu.inst 11333 # number of demand (read+write) accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_accesses::cpu.data 2247 # number of demand (read+write) accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_accesses::total 13580 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 11333 # number of overall (read+write) accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_accesses::cpu.data 2247 # number of overall (read+write) accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.overall_accesses::total 13580 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.270184 # miss rate for ReadReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.893411 # miss rate for ReadReq accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.297325 # miss rate for ReadReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.270184 # miss rate for demand accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963952 # miss rate for demand accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_miss_rate::total 0.384978 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.270184 # miss rate for overall accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.overall_miss_rate::total 0.384978 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68991.998694 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79441.431670 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70359.352824 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73669.648094 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73669.648094 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68991.998694 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74898.084026 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71438.934583 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68991.998694 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74898.084026 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71438.934583 # average overall miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3062 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3523 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1705 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1705 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3062 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2166 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5228 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 172480500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30915000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 203395500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104707750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104707750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172480500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 135622750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 308103250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172480500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 135622750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 308103250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for ReadReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.297325 # mshr miss rate for ReadReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for demand accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for demand accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.384978 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for overall accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.384978 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56329.359895 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67060.737527 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.607721 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61412.170088 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61412.170088 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.tags.replacements 159 # number of replacements
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.tagsinuse 1460.308394 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 28078942 # Total number of references to valid blocks.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.avg_refs 12496.191366 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 1460.308394 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.356521 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.356521 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1391 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.tags.tag_accesses 56178581 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 56178581 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21585827 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21585827 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6492868 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6492868 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 247 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 247 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 28078695 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28078695 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28078695 # number of overall hits
system.cpu.dcache.overall_hits::total 28078695 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 989 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 989 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 8235 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 8235 # number of WriteReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.demand_misses::cpu.data 9224 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9224 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9224 # number of overall misses
system.cpu.dcache.overall_misses::total 9224 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 64012750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 64012750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 517866286 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 517866286 # number of WriteReq miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 581879036 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 581879036 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 581879036 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 581879036 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 21586816 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 21586816 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 248 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 28087919 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 28087919 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 28087919 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 28087919 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001267 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001267 # miss rate for WriteReq accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004032 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004032 # miss rate for LoadLockedReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64724.721941 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 64724.721941 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62886.009229 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62886.009229 # average WriteReq miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 63083.156548 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 63083.156548 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 24818 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.blocked::no_mshrs 346 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.728324 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.writebacks::writebacks 109 # number of writebacks
system.cpu.dcache.writebacks::total 109 # number of writebacks
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6504 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6504 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6978 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6978 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6978 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6978 # number of overall MSHR hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37612750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37612750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127737997 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 127737997 # number of WriteReq MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165350747 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 165350747 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 165350747 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 165350747 # number of overall MSHR miss cycles
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004032 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004032 # mshr miss rate for LoadLockedReq accesses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73034.466019 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73034.466019 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73794.336800 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73794.336800 # average WriteReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
---------- End Simulation Statistics ----------
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