2012-03-09 15:59:28 +01:00
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---------- Begin Simulation Statistics ----------
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2013-11-01 16:56:34 +01:00
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sim_seconds 0.000017 # Number of seconds simulated
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2014-03-23 16:12:19 +01:00
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sim_ticks 17056000 # Number of ticks simulated
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final_tick 17056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2012-03-09 15:59:28 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2014-03-23 16:12:19 +01:00
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host_inst_rate 29277 # Simulator instruction rate (inst/s)
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host_op_rate 36530 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 108745688 # Simulator tick rate (ticks/s)
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host_mem_usage 308972 # Number of bytes of host memory used
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host_seconds 0.16 # Real time elapsed on the host
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2013-01-08 14:54:16 +01:00
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sim_insts 4591 # Number of instructions simulated
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sim_ops 5729 # Number of ops (including micro ops) simulated
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2014-01-24 22:29:33 +01:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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2013-11-01 16:56:34 +01:00
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system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory
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2012-10-25 19:14:42 +02:00
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system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
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2013-11-01 16:56:34 +01:00
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system.physmem.bytes_read::total 25088 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 17280 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 270 # Number of read requests responded to by this memory
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2012-10-25 19:14:42 +02:00
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system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
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2013-11-01 16:56:34 +01:00
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system.physmem.num_reads::total 392 # Number of read requests responded to by this memory
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2014-03-23 16:12:19 +01:00
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system.physmem.bw_read::cpu.inst 1013133208 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 457786116 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1470919325 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1013133208 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1013133208 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1013133208 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 457786116 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1470919325 # Total bandwidth to/from this memory (bytes/s)
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2013-11-01 16:56:34 +01:00
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system.physmem.readReqs 392 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 392 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25088 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25088 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 86 # Per bank write bursts
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system.physmem.perBankRdBursts::1 46 # Per bank write bursts
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system.physmem.perBankRdBursts::2 20 # Per bank write bursts
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system.physmem.perBankRdBursts::3 42 # Per bank write bursts
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system.physmem.perBankRdBursts::4 17 # Per bank write bursts
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system.physmem.perBankRdBursts::5 34 # Per bank write bursts
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system.physmem.perBankRdBursts::6 35 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10 # Per bank write bursts
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system.physmem.perBankRdBursts::8 4 # Per bank write bursts
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system.physmem.perBankRdBursts::9 7 # Per bank write bursts
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system.physmem.perBankRdBursts::10 28 # Per bank write bursts
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system.physmem.perBankRdBursts::11 42 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9 # Per bank write bursts
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system.physmem.perBankRdBursts::13 6 # Per bank write bursts
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system.physmem.perBankRdBursts::14 0 # Per bank write bursts
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system.physmem.perBankRdBursts::15 6 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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2014-03-23 16:12:19 +01:00
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system.physmem.totGap 16998500 # Total gap between requests
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2013-11-01 16:56:34 +01:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 392 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see
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2014-03-23 16:12:19 +01:00
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system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
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2013-11-01 16:56:34 +01:00
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system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
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2013-06-27 11:49:51 +02:00
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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2012-11-02 17:50:06 +01:00
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
2014-03-23 16:12:19 +01:00
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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|
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 32 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 450 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 276.111928 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 399.674706 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 7 21.88% 21.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 8 25.00% 46.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 4 12.50% 59.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 1 3.12% 62.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2 6.25% 68.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1 3.12% 71.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 9 28.12% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 32 # Bytes accessed per row activation
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system.physmem.totQLat 4223500 # Total ticks spent queuing
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system.physmem.totMemAccLat 11614750 # Total ticks spent from burst creation until serviced by the DRAM
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2013-11-01 16:56:34 +01:00
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system.physmem.totBusLat 1960000 # Total ticks spent in databus transfers
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2014-03-23 16:12:19 +01:00
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system.physmem.totBankLat 5431250 # Total ticks spent accessing banks
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|
|
system.physmem.avgQLat 10774.23 # Average queueing delay per DRAM burst
|
|
|
|
|
system.physmem.avgBankLat 13855.23 # Average bank access latency per DRAM burst
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.avgMemAccLat 29629.46 # Average memory access latency per DRAM burst
|
|
|
|
|
system.physmem.avgRdBW 1470.92 # Average DRAM read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.avgRdBWSys 1470.92 # Average system read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
|
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.busUtil 11.49 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.readRowHits 326 # Number of row buffer hits during reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.readRowHitRate 83.16 # Row buffer hit rate for reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.avgGap 43363.52 # Average gap between requests
|
|
|
|
|
system.physmem.pageHitRate 83.16 # Row buffer hit rate, read and write combined
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
|
2014-03-23 16:12:19 +01:00
|
|
|
system.membus.throughput 1467166979 # Throughput (bytes/s)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.membus.trans_dist::ReadReq 351 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 350 # Transaction distribution
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.trans_dist::ReadExReq 41 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 41 # Transaction distribution
|
2013-11-01 16:56:34 +01:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 783 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 783 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25024 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.tot_pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.data_through_bus 25024 # Total data (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
2014-03-23 16:12:19 +01:00
|
|
|
system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
2014-03-23 16:12:19 +01:00
|
|
|
system.membus.respLayer1.occupancy 3645250 # Layer occupancy (ticks)
|
|
|
|
|
system.membus.respLayer1.utilization 21.4 # Layer utilization (%)
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.branchPred.lookups 2481 # Number of BP lookups
|
|
|
|
|
system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.branchPred.BTBHits 697 # Number of BTB hits
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target.
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.checker.dtb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.checker.dtb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.checker.dtb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.checker.dtb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.checker.dtb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.checker.dtb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.checker.dtb.accesses 0 # DTB accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.checker.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.checker.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.checker.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.checker.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.checker.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.checker.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.checker.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.checker.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.checker.itb.accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 13 # Number of system calls
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.checker.numCycles 5742 # number of cpu cycles simulated
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.numCycles 34113 # number of cpu cycles simulated
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.fetch.icacheStallCycles 6922 # Number of cycles fetch is stalled on an Icache miss
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.fetch.Insts 11923 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 2481 # Number of branches that fetch encountered
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.fetch.predictedBranches 990 # Number of branches that fetch has predicted taken
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.fetch.Cycles 2627 # Number of cycles fetch has run and was not squashing or blocked
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.fetch.SquashCycles 1612 # Number of cycles fetch has spent squashing
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.fetch.BlockedCycles 2574 # Number of cycles fetch has spent blocked
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.fetch.CacheLines 1947 # Number of cache lines fetched
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.fetch.rateDist::samples 13229 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 1.138559 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.553229 # Number of instructions fetched each cycle (Total)
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.fetch.rateDist::0 10602 80.14% 80.14% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 226 1.71% 81.85% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 203 1.53% 83.38% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 226 1.71% 85.09% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 222 1.68% 86.77% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 269 2.03% 88.80% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 92 0.70% 89.50% # Number of instructions fetched each cycle (Total)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.fetch.rateDist::7 145 1.10% 90.60% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 1244 9.40% 100.00% # Number of instructions fetched each cycle (Total)
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.fetch.rateDist::total 13229 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.072729 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 0.349515 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 6934 # Number of cycles decode is idle
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.decode.BlockedCycles 2849 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 2426 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.decode.SquashCycles 951 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.decode.DecodedInsts 13218 # Number of instructions handled by decode
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.rename.SquashCycles 951 # Number of cycles rename is squashing
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.rename.IdleCycles 7200 # Number of cycles rename is idle
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.rename.BlockCycles 361 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 2227 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups
|
2013-10-16 16:44:12 +02:00
|
|
|
system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.rename.skidInsts 666 # count of insts added to the skid buffer
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit.
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores.
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec)
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::samples 13229 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 0.674352 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.378841 # Number of insts issued each cycle
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::0 9649 72.94% 72.94% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 1315 9.94% 82.88% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 815 6.16% 89.04% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 543 4.10% 93.14% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 457 3.45% 96.60% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 260 1.97% 98.56% # Number of insts issued each cycle
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::6 123 0.93% 99.49% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 55 0.42% 99.91% # Number of insts issued each cycle
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 13229 # Number of insts issued each cycle
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.fu_full::IntAlu 8 3.57% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 139 62.05% 65.62% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 77 34.38% 100.00% # attempts to use FU when none available
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 5361 60.09% 60.09% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 2338 26.21% 86.44% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 1210 13.56% 100.00% # Type of FU issued
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.iq.rate 0.261513 # Inst issue rate
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.fu_busy_cnt 224 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.025109 # FU busy rate (busy events/executed inst)
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.iq.int_inst_queue_reads 31372 # Number of integer instruction queue reads
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.int_inst_queue_writes 16313 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iq.int_alu_accesses 9125 # Number of integer alu accesses
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1590 # Number of loads squashed
|
2012-10-25 19:14:42 +02:00
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 626 # Number of stores squashed
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 951 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 234 # Number of cycles IEW is blocking
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 11220 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 1564 # Number of dispatched store instructions
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 270 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iew.iewExecutedInsts 8523 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 2139 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iew.exec_refs 3299 # number of memory reference insts executed
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.iew.exec_branches 1437 # Number of branches executed
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.iew.exec_stores 1160 # Number of stores executed
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.iew.exec_rate 0.249846 # Inst execution rate
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iew.wb_sent 8226 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 3883 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 7788 # num instructions consuming a value
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.iew.wb_rate 0.236508 # insts written-back per cycle
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.iew.wb_fanout 0.498588 # average fanout of values written-back
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 5496 # The number of squashed insts skipped by commit
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
2013-03-28 00:36:21 +01:00
|
|
|
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::samples 12278 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.466607 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.298423 # Number of insts commited each cycle
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 9992 81.38% 81.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 1070 8.71% 90.10% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 401 3.27% 93.36% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 262 2.13% 95.50% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 176 1.43% 96.93% # Number of insts commited each cycle
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::5 172 1.40% 98.33% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 121 0.99% 100.00% # Number of insts commited each cycle
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 12278 # Number of insts commited each cycle
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.committedInsts 4591 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.refs 2138 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 1200 # Number of loads committed
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.commit.membars 12 # Number of memory barriers committed
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.branches 1007 # Number of branches committed
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.commit.function_calls 82 # Number of function calls committed.
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.rob.rob_reads 23225 # The number of ROB reads
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.rob.rob_writes 23415 # The number of ROB writes
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 20884 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.committedInsts 4591 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
|
|
|
|
|
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.cpi 7.430407 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 7.430407 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.134582 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.134582 # IPC: Total IPC of All Threads
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.int_regfile_reads 39210 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 7985 # number of integer regfile writes
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.misc_regfile_reads 3239 # number of misc regfile reads
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.toL2Bus.throughput 1636022514 # Throughput (bytes/s)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes)
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.toL2Bus.pkt_count::total 873 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18560 # Cumulative packet size per connected master and slave (bytes)
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.toL2Bus.tot_pkt_size::total 27904 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.data_through_bus 27904 # Total data (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 218500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%)
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 228745 # Layer occupancy (ticks)
|
|
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.replacements 4 # number of replacements
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.icache.tags.tagsinuse 147.751269 # Cycle average of tags in use
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.icache.tags.total_refs 1584 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 290 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 5.462069 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 147.751269 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.072144 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.072144 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 286 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.139648 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.icache.tags.tag_accesses 4184 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 4184 # Number of data accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1584 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 1584 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 1584 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 1584 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 1584 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 1584 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 363 # number of overall misses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24948500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 24948500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 24948500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 24948500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 24948500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 24948500 # number of overall miss cycles
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1947 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 1947 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 1947 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 1947 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 1947 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 1947 # number of overall (read+write) accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186441 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.186441 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.186441 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.186441 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.186441 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.186441 # miss rate for overall accesses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 68728.650138 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 68728.650138 # average overall miss latency
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 290 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 290 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 290 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 290 # number of overall MSHR misses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20177000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 20177000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20177000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 20177000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20177000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 20177000 # number of overall MSHR miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148947 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.148947 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148947 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.148947 # mshr miss rate for overall accesses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069 # average overall mshr miss latency
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.l2cache.tags.tagsinuse 186.152493 # Cycle average of tags in use
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks.
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 0.114286 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.100090 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.052403 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004245 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001436 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.005681 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 3887 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 3887 # Number of data accesses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.overall_hits::total 40 # number of overall hits
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 270 # number of ReadReq misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 270 # number of demand (read+write) misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_misses::total 397 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 270 # number of overall misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.overall_misses::total 397 # number of overall misses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19680500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6712250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 26392750 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3002000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3002000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 19680500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9714250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 29394750 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 19680500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9714250 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 29394750 # number of overall miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 290 # number of ReadReq accesses(hits+misses)
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 396 # number of ReadReq accesses(hits+misses)
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 290 # number of demand (read+write) accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::total 437 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 290 # number of overall (read+write) accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.overall_accesses::total 437 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931034 # miss rate for ReadReq accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.898990 # miss rate for ReadReq accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931034 # miss rate for demand accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.908467 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931034 # miss rate for overall accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.908467 # miss rate for overall accesses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436 # average overall miss latency
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 270 # number of ReadReq MSHR misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 270 # number of demand (read+write) MSHR misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 392 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 270 # number of overall MSHR misses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 392 # number of overall MSHR misses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16292000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5423750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21715750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2498500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2498500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16292000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7922250 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 24214250 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16292000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7922250 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 24214250 # number of overall MSHR miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for ReadReq accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886364 # mshr miss rate for ReadReq accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for demand accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.897025 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931034 # mshr miss rate for overall accesses
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897025 # mshr miss rate for overall accesses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918 # average overall mshr miss latency
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.dcache.tags.tagsinuse 87.338696 # Cycle average of tags in use
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.tags.total_refs 2394 # Total number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.tags.avg_refs 16.397260 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 87.338696 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.021323 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.021323 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.dcache.tags.tag_accesses 5930 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 5930 # Number of data accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1767 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 1767 # number of ReadReq hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 2373 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 189 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 189 # number of ReadReq misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 496 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 496 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 496 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 496 # number of overall misses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11160743 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 11160743 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20397000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 20397000 # number of WriteReq miss cycles
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 31557743 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 31557743 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 31557743 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 31557743 # number of overall miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses)
|
2013-01-08 14:54:16 +01:00
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096626 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.096626 # miss rate for ReadReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.172883 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.172883 # miss rate for overall accesses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414 # average WriteReq miss latency
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65000 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65000 # average LoadLockedReq miss latency
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 63624.481855 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 63624.481855 # average overall miss latency
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.666667 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 349 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 349 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 349 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 349 # number of overall MSHR hits
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7022255 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7022255 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3044000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3044000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10066255 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10066255 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10066255 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10066255 # number of overall MSHR miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170 # average overall mshr miss latency
|
|
|
|
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system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170 # average overall mshr miss latency
|
2012-03-09 15:59:28 +01:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
|
|
|
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|
---------- End Simulation Statistics ----------
|
