sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini

1948 lines
37 KiB
INI
Raw Normal View History

ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[root]
type=Root
children=system
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
full_system=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
sim_quantum=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
atags_addr=256
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
boot_loader=/dist/binaries/boot.arm
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
boot_release_addr=65528
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
cache_line_size=64
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
dtb_filename=
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
early_kernel_symbols=false
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
enable_context_switch_stats_dump=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
flags_addr=268435504
gic_cpu_addr=520093952
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
have_generic_timer=false
have_large_asid_64=false
have_lpae=false
have_security=false
have_virtualization=false
highest_el_is_64=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
init_param=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
load_addr_mask=268435455
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
load_offset=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
machine_type=RealView_PBX
mem_mode=timing
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
mem_ranges=0:134217727
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
memories=system.physmem system.realview.nvmem
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
multi_proc=true
stats: Update stats for ARM init param changes.
2012-01-10 01:08:20 +01:00
num_work_ids=16
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
panic_on_oops=true
panic_on_panic=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
phys_addr_range_64=40
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
readfile=tests/halt.sh
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
reset_addr_64=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
system_port=system.membus.slave[0]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.bridge]
type=Bridge
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
delay=50000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
ranges=268435456:520093695 1073741824:1610612735
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
req_size=16
resp_size=16
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
master=system.iobus.slave[0]
slave=system.membus.master[0]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cf0]
type=IdeDisk
children=image
delay=1000000
driveID=master
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
image=system.cf0.image
[system.cf0.image]
type=CowDiskImage
children=child
child=system.cf0.image.child
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
image_file=
read_only=false
table_size=65536
[system.cf0.image.child]
type=RawDiskImage
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
image_file=/dist/disks/linux-arm-ael.img
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
read_only=true
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.clk_domain]
type=SrcClockDomain
clock=1000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0]
type=DerivO3CPU
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
branchPred=system.cpu0.branchPred
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cachePorts=200
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
dstage2_mmu=system.cpu0.dstage2_mmu
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
dtb=system.cpu0.dtb
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
fetchBufferSize=64
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu0.interrupts
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
isa=system.cpu0.isa
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueToExecuteDelay=1
issueWidth=8
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
istage2_mmu=system.cpu0.istage2_mmu
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
needsTSO=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
numIQEntries=64
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
numPhysCCRegs=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
simpoint_start_insts=
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
switched_out=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tracer=system.cpu0.tracer
trapLatency=13
wbDepth=1
wbWidth=8
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
workload=
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
[system.cpu0.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.dcache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
assoc=4
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu0.dcache.tags
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
mem_side=system.toL2Bus.slave[1]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu0.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
[system.cpu0.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[5]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.dtb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=64
walker=system.cpu0.dtb.walker
[system.cpu0.dtb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
port=system.toL2Bus.slave[3]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.fuPool.FUList0]
type=FUDesc
children=opList
count=6
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu0.fuPool.FUList0.opList
[system.cpu0.fuPool.FUList0.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu0.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=IntMult
opLat=3
[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu0.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu0.fuPool.FUList2.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu0.fuPool.FUList2.opList2]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu0.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu0.fuPool.FUList3.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu0.fuPool.FUList3.opList2]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu0.fuPool.FUList4]
type=FUDesc
children=opList
count=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu0.fuPool.FUList4.opList
[system.cpu0.fuPool.FUList4.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=MemRead
opLat=1
[system.cpu0.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
[system.cpu0.fuPool.FUList5.opList00]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu0.fuPool.FUList5.opList01]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList02]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu0.fuPool.FUList5.opList03]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu0.fuPool.FUList5.opList04]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu0.fuPool.FUList5.opList05]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu0.fuPool.FUList5.opList06]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu0.fuPool.FUList5.opList07]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList08]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu0.fuPool.FUList5.opList09]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList10]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu0.fuPool.FUList5.opList11]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu0.fuPool.FUList5.opList12]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu0.fuPool.FUList5.opList13]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu0.fuPool.FUList5.opList14]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu0.fuPool.FUList5.opList15]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu0.fuPool.FUList5.opList16]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu0.fuPool.FUList5.opList17]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu0.fuPool.FUList5.opList18]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList19]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu0.fuPool.FUList6]
type=FUDesc
children=opList
count=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu0.fuPool.FUList6.opList
[system.cpu0.fuPool.FUList6.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu0.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
[system.cpu0.fuPool.FUList7.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=MemRead
opLat=1
[system.cpu0.fuPool.FUList7.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu0.fuPool.FUList8]
type=FUDesc
children=opList
count=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu0.fuPool.FUList8.opList
[system.cpu0.fuPool.FUList8.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu0.icache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
assoc=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu0.icache.tags
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
mem_side=system.toL2Bus.slave[0]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu0.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.interrupts]
type=ArmInterrupts
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
[system.cpu0.isa]
type=ArmISA
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
fpsid=1090793632
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr0=270536963
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_mmfr1=0
id_mmfr2=19070976
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr3=34611729
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_pfr0=49
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_pfr1=4113
midr=1091551472
system=system
[system.cpu0.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu0.istage2_mmu.stage2_tlb.walker
[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[4]
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.itb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=64
walker=system.cpu0.itb.walker
[system.cpu0.itb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
port=system.toL2Bus.slave[2]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu0.tracer]
type=ExeTracer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1]
type=DerivO3CPU
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
branchPred=system.cpu1.branchPred
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cachePorts=200
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
dstage2_mmu=system.cpu1.dstage2_mmu
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
dtb=system.cpu1.dtb
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
fetchBufferSize=64
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu1.interrupts
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
isa=system.cpu1.isa
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueToExecuteDelay=1
issueWidth=8
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
istage2_mmu=system.cpu1.istage2_mmu
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
needsTSO=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
numIQEntries=64
test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-16 16:44:12 +02:00
numPhysCCRegs=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
simpoint_start_insts=
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
switched_out=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tracer=system.cpu1.tracer
trapLatency=13
wbDepth=1
wbWidth=8
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
workload=
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
[system.cpu1.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.dcache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
assoc=4
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu1.dcache.tags
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
mem_side=system.toL2Bus.slave[7]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu1.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
[system.cpu1.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[11]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.dtb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=64
walker=system.cpu1.dtb.walker
[system.cpu1.dtb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
port=system.toL2Bus.slave[9]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.fuPool.FUList0]
type=FUDesc
children=opList
count=6
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu1.fuPool.FUList0.opList
[system.cpu1.fuPool.FUList0.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu1.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
[system.cpu1.fuPool.FUList1.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=IntMult
opLat=3
[system.cpu1.fuPool.FUList1.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu1.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
[system.cpu1.fuPool.FUList2.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu1.fuPool.FUList2.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu1.fuPool.FUList2.opList2]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu1.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
[system.cpu1.fuPool.FUList3.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu1.fuPool.FUList3.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu1.fuPool.FUList3.opList2]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu1.fuPool.FUList4]
type=FUDesc
children=opList
count=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu1.fuPool.FUList4.opList
[system.cpu1.fuPool.FUList4.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=MemRead
opLat=1
[system.cpu1.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
[system.cpu1.fuPool.FUList5.opList00]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu1.fuPool.FUList5.opList01]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList02]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu1.fuPool.FUList5.opList03]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu1.fuPool.FUList5.opList04]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu1.fuPool.FUList5.opList05]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu1.fuPool.FUList5.opList06]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu1.fuPool.FUList5.opList07]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList08]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu1.fuPool.FUList5.opList09]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList10]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu1.fuPool.FUList5.opList11]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu1.fuPool.FUList5.opList12]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu1.fuPool.FUList5.opList13]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu1.fuPool.FUList5.opList14]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu1.fuPool.FUList5.opList15]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu1.fuPool.FUList5.opList16]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu1.fuPool.FUList5.opList17]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu1.fuPool.FUList5.opList18]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList19]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu1.fuPool.FUList6]
type=FUDesc
children=opList
count=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu1.fuPool.FUList6.opList
[system.cpu1.fuPool.FUList6.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu1.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
[system.cpu1.fuPool.FUList7.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=MemRead
opLat=1
[system.cpu1.fuPool.FUList7.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu1.fuPool.FUList8]
type=FUDesc
children=opList
count=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
opList=system.cpu1.fuPool.FUList8.opList
[system.cpu1.fuPool.FUList8.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu1.icache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
assoc=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu1.icache.tags
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
mem_side=system.toL2Bus.slave[6]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu1.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=32768
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.interrupts]
type=ArmInterrupts
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
[system.cpu1.isa]
type=ArmISA
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
fpsid=1090793632
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr0=270536963
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_mmfr1=0
id_mmfr2=19070976
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr3=34611729
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_pfr0=49
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_pfr1=4113
midr=1091551472
system=system
[system.cpu1.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu1.istage2_mmu.stage2_tlb.walker
[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[10]
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.itb]
type=ArmTLB
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=64
walker=system.cpu1.itb.walker
[system.cpu1.itb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
port=system.toL2Bus.slave[8]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.cpu1.tracer]
type=ExeTracer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.intrctrl]
type=IntrControl
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sys=system
[system.iobus]
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
type=NoncoherentBus
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
header_cycles=1
use_default_range=false
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
width=8
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.iocache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
addr_ranges=0:134217727
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=false
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=50
is_top_level=true
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
max_miss_count=0
mshrs=20
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=1024
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.iocache.tags
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tgts_per_mshr=12
two_queue=false
write_buffers=8
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
cpu_side=system.iobus.master[25]
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
mem_side=system.membus.slave[2]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.iocache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=50
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=1024
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.l2c]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
addr_ranges=0:18446744073709551615
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
assoc=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=20
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
is_top_level=false
max_miss_count=0
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
mshrs=20
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
size=4194304
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.l2c.tags
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
tgts_per_mshr=12
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
two_queue=false
write_buffers=8
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
cpu_side=system.toL2Bus.master[0]
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
mem_side=system.membus.slave[1]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.l2c.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=20
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
size=4194304
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.membus]
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
type=CoherentBus
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
children=badaddr_responder
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
header_cycles=1
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system=system
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
use_default_range=false
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
width=8
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
default=system.membus.badaddr_responder.pio
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.membus.badaddr_responder]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
fake_mem=false
pio_addr=0
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pio_size=8
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=warn
pio=system.membus.default
[system.physmem]
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
type=SimpleDRAM
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
activation_limit=4
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
addr_mapping=RaBaChCo
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
banks_per_rank=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
burst_length=8
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
channels=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
conf_table_reported=true
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
mem_sched_policy=frfcfs
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
null=false
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
page_policy=open
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
range=0:134217727
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
ranks_per_channel=2
read_buffer_size=32
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
static_backend_latency=10000
static_frontend_latency=10000
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
tBURST=5000
tCL=13750
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
tRAS=35000
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
tRCD=13750
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
tREFI=7800000
tRFC=300000
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
tRP=13750
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
tRRD=6250
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
tWTR=7500
tXAW=40000
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
write_buffer_size=32
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
write_high_thresh_perc=70
write_low_thresh_perc=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
port=system.membus.master[6]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview]
type=RealView
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
intrctrl=system.intrctrl
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
max_mem_size=268435456
mem_start_addr=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pci_cfg_base=0
system=system
[system.realview.a9scu]
type=A9SCU
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pio_addr=520093696
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
pio=system.membus.master[4]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268451840
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[21]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.cf_ctrl]
type=IdeController
BAR0=402653184
BAR0LegacyIO=true
BAR0Size=16
BAR1=402653440
BAR1LegacyIO=true
BAR1Size=1
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
CapabilityPtr=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
CardbusCIS=0
ClassCode=1
Command=1
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
MSICAPMsgAddr=0
MSICAPMsgCtrl=0
MSICAPMsgData=0
MSICAPMsgUpperAddr=0
MSICAPNextCapability=0
MSICAPPendingBits=0
MSIXCAPBaseOffset=0
MSIXCAPCapId=0
MSIXCAPNextCapability=0
MSIXMsgCtrl=0
MSIXPbaOffset=0
MSIXTableOffset=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
MaximumLatency=0
MinimumGrant=0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
PMCAPBaseOffset=0
PMCAPCapId=0
PMCAPCapabilities=0
PMCAPCtrlStatus=0
PMCAPNextCapability=0
PXCAPBaseOffset=0
PXCAPCapId=0
PXCAPCapabilities=0
PXCAPDevCap2=0
PXCAPDevCapabilities=0
PXCAPDevCtrl=0
PXCAPDevCtrl2=0
PXCAPDevStatus=0
PXCAPLinkCap=0
PXCAPLinkCtrl=0
PXCAPLinkStatus=0
PXCAPNextCapability=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
config_latency=20000
ctrl_offset=2
disks=system.cf0
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
io_shift=1
pci_bus=2
pci_dev=7
pci_func=0
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=30000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
platform=system.realview
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
config=system.iobus.master[8]
dma=system.iobus.slave[2]
pio=system.iobus.master[7]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.clcd]
type=Pl111
amba_id=1315089
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
enable_capture=true
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
pixel_clock=41667
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
vnc=system.vncserver
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268632064
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[9]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.flash_fake]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
fake_mem=true
pio_addr=1073741824
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pio_size=536870912
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[24]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.gic]
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
type=Pl390
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
dist_pio_delay=10000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
int_latency=10000
it_lines=128
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
msix_addr=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
platform=system.realview
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
pio=system.membus.master[2]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268513280
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[16]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268517376
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[17]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268521472
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[18]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.kmi0]
type=Pl050
amba_id=1314896
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_delay=1000000
int_num=52
is_mouse=false
pio_addr=268460032
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
vnc=system.vncserver
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[5]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.kmi1]
type=Pl050
amba_id=1314896
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_delay=1000000
int_num=53
is_mouse=true
pio_addr=268464128
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
vnc=system.vncserver
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[6]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.l2x0_fake]
type=IsaFake
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
fake_mem=false
pio_addr=520101888
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pio_size=4095
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
pio=system.membus.master[3]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.local_cpu_timer]
type=CpuLocalTimer
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
pio_addr=520095232
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
pio=system.membus.master[5]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268455936
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[22]
[system.realview.nvmem]
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
type=SimpleMemory
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
bandwidth=73.000000
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
conf_table_reported=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
latency=30000
latency_var=0
null=false
range=2147483648:2214592511
port=system.membus.master[1]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.realview_io]
type=RealViewCtrl
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
idreg=0
pio_addr=268435456
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
proc_id0=201326592
proc_id1=201327138
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[1]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
[system.realview.rtc]
type=PL031
amba_id=3412017
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
gic=system.realview.gic
int_delay=100000
int_num=42
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
pio_addr=268529664
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
time=Thu Jan 1 00:00:00 2009
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[23]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268492800
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[20]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=269357056
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[13]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=true
pio_addr=268439552
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[14]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268488704
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[19]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.timer0]
type=Sp804
amba_id=1316868
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
clock0=1000000
clock1=1000000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_num0=36
int_num1=36
pio_addr=268505088
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[2]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.timer1]
type=Sp804
amba_id=1316868
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
clock0=1000000
clock1=1000000
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_num0=37
int_num1=37
pio_addr=268509184
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[3]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.uart]
type=Pl011
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
end_on_eot=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
gic=system.realview.gic
int_delay=100000
int_num=44
pio_addr=268472320
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
platform=system.realview
system=system
terminal=system.terminal
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[0]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268476416
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[10]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268480512
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[11]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268484608
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[12]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
ignore_access=false
pio_addr=268500992
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
pio_latency=100000
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system=system
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
pio=system.iobus.master[15]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.terminal]
type=Terminal
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.toL2Bus]
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
type=CoherentBus
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
header_cycles=1
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system=system
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
use_default_range=false
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
width=8
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
2012-03-09 15:59:29 +01:00
master=system.l2c.cpu_side
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
[system.vncserver]
type=VncServer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: Update stats for ARM init param changes.
2012-01-10 01:08:20 +01:00
frame_capture=false
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
number=0
port=5900
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.voltage_domain]
type=VoltageDomain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage=1.000000
Reference in a new issue Copy permalink