2013-03-01 19:20:30 +01:00
---------- Begin Simulation Statistics ----------
2016-05-31 12:07:18 +02:00
sim_seconds 2.823729 # Number of seconds simulated
sim_ticks 2823728611500 # Number of ticks simulated
final_tick 2823728611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2013-03-01 19:20:30 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-05-31 17:55:47 +02:00
host_inst_rate 192143 # Simulator instruction rate (inst/s)
host_op_rate 233071 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4415299854 # Simulator tick rate (ticks/s)
host_mem_usage 584992 # Number of bytes of host memory used
host_seconds 639.53 # Real time elapsed on the host
2016-05-31 12:07:18 +02:00
sim_insts 122881667 # Number of instructions simulated
sim_ops 149056790 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-05-31 12:07:18 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 538276 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 3140708 # Number of bytes read from this memory
2016-04-09 18:13:40 +02:00
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
2016-05-31 12:07:18 +02:00
system.physmem.bytes_read::cpu1.inst 122816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 897088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 339840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2003776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker 4480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 386816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 3512832 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-05-31 12:07:18 +02:00
system.physmem.bytes_read::total 10950024 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 538276 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 122816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 339840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 386816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1387748 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8235776 # Number of bytes written to this memory
2015-07-30 11:16:36 +02:00
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
2016-05-31 12:07:18 +02:00
system.physmem.bytes_written::total 8253300 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 16864 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 49593 # Number of read requests responded to by this memory
2016-04-09 18:13:40 +02:00
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.physmem.num_reads::cpu1.inst 1919 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 14017 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 5310 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 31309 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker 70 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 6044 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 54888 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.physmem.num_reads::total 180067 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 128684 # Number of write requests responded to by this memory
2015-07-30 11:16:36 +02:00
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
2016-05-31 12:07:18 +02:00
system.physmem.num_writes::total 133065 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 190626 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1112256 # Total read bandwidth from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_read::cpu1.inst 43494 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 317696 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 635 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 120352 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 709621 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker 1587 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 136988 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 1244040 # Total read bandwidth from this memory (bytes/s)
2015-07-30 11:16:36 +02:00
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_read::total 3877860 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 190626 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 43494 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 120352 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 136988 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 491459 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2916632 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6206 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2922838 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2916632 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 190626 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1118462 # Total bandwidth to/from this memory (bytes/s)
2016-04-09 18:13:40 +02:00
system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_total::cpu1.inst 43494 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 317696 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 635 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 120352 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 709621 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker 1587 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 136988 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 1244040 # Total bandwidth to/from this memory (bytes/s)
2015-07-30 11:16:36 +02:00
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
2016-05-31 12:07:18 +02:00
system.physmem.bw_total::total 6800697 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 113588 # Number of read requests accepted
system.physmem.writeReqs 68931 # Number of write requests accepted
system.physmem.readBursts 113588 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 68931 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 7262464 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue
system.physmem.bytesWritten 4410816 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 7269632 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4411584 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue
2015-07-30 11:16:36 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-05-31 12:07:18 +02:00
system.physmem.perBankRdBursts::0 7537 # Per bank write bursts
system.physmem.perBankRdBursts::1 6789 # Per bank write bursts
system.physmem.perBankRdBursts::2 7399 # Per bank write bursts
system.physmem.perBankRdBursts::3 7485 # Per bank write bursts
system.physmem.perBankRdBursts::4 7337 # Per bank write bursts
system.physmem.perBankRdBursts::5 7010 # Per bank write bursts
system.physmem.perBankRdBursts::6 7617 # Per bank write bursts
system.physmem.perBankRdBursts::7 7715 # Per bank write bursts
system.physmem.perBankRdBursts::8 6869 # Per bank write bursts
system.physmem.perBankRdBursts::9 7528 # Per bank write bursts
system.physmem.perBankRdBursts::10 7086 # Per bank write bursts
system.physmem.perBankRdBursts::11 6373 # Per bank write bursts
system.physmem.perBankRdBursts::12 6401 # Per bank write bursts
system.physmem.perBankRdBursts::13 7208 # Per bank write bursts
system.physmem.perBankRdBursts::14 6839 # Per bank write bursts
system.physmem.perBankRdBursts::15 6283 # Per bank write bursts
system.physmem.perBankWrBursts::0 4402 # Per bank write bursts
system.physmem.perBankWrBursts::1 3960 # Per bank write bursts
system.physmem.perBankWrBursts::2 4483 # Per bank write bursts
system.physmem.perBankWrBursts::3 4623 # Per bank write bursts
system.physmem.perBankWrBursts::4 4313 # Per bank write bursts
system.physmem.perBankWrBursts::5 4310 # Per bank write bursts
system.physmem.perBankWrBursts::6 4616 # Per bank write bursts
system.physmem.perBankWrBursts::7 4482 # Per bank write bursts
system.physmem.perBankWrBursts::8 4162 # Per bank write bursts
system.physmem.perBankWrBursts::9 4849 # Per bank write bursts
system.physmem.perBankWrBursts::10 4455 # Per bank write bursts
system.physmem.perBankWrBursts::11 3923 # Per bank write bursts
system.physmem.perBankWrBursts::12 3821 # Per bank write bursts
system.physmem.perBankWrBursts::13 4641 # Per bank write bursts
system.physmem.perBankWrBursts::14 4142 # Per bank write bursts
system.physmem.perBankWrBursts::15 3737 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-05-31 12:07:18 +02:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 2822156484500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-07-30 11:16:36 +02:00
system.physmem.readPktSize::2 0 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 0 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-05-31 12:07:18 +02:00
system.physmem.readPktSize::6 113588 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2015-07-30 11:16:36 +02:00
system.physmem.writePktSize::2 0 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-05-31 12:07:18 +02:00
system.physmem.writePktSize::6 68931 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 85837 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 24551 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2500 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
2015-07-30 11:16:36 +02:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
2013-11-01 16:56:34 +01:00
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
2013-03-01 19:20:30 +01:00
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2016-05-31 12:07:18 +02:00
system.physmem.wrQLenPdf::0 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 65 # What write queue length does an incoming req see
2016-04-09 18:13:40 +02:00
system.physmem.wrQLenPdf::4 65 # What write queue length does an incoming req see
2016-05-31 12:07:18 +02:00
system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1493 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3561 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 3756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3758 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3892 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4808 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4278 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4456 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 3883 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 3800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 3676 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 39396 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 296.306224 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 172.340600 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 326.184189 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 15747 39.97% 39.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 9259 23.50% 63.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 3829 9.72% 73.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2133 5.41% 78.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1523 3.87% 82.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 982 2.49% 84.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 643 1.63% 86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 644 1.63% 88.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4636 11.77% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 39396 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 3632 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 31.238987 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 631.062126 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 3630 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 3632 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 3632 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.975496 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.811099 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 10.084616 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 8 0.22% 0.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 2 0.06% 0.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 2 0.06% 0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 6 0.17% 0.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 3236 89.10% 89.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 53 1.46% 91.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 53 1.46% 92.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 39 1.07% 93.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 77 2.12% 95.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 40 1.10% 96.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 9 0.25% 97.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 10 0.28% 97.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 6 0.17% 97.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 6 0.17% 97.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 3 0.08% 97.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 3 0.08% 97.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 57 1.57% 99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 2 0.06% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 4 0.11% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 3 0.08% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.03% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.03% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.03% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.06% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.03% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 5 0.14% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 3632 # Writes before turning the bus around for reads
system.physmem.totQLat 1343217000 # Total ticks spent queuing
system.physmem.totMemAccLat 3470892000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 567380000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11837.01 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-05-31 12:07:18 +02:00
system.physmem.avgMemAccLat 30587.01 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.57 # Average DRAM read bandwidth in MiByte/s
2016-04-09 18:13:40 +02:00
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s
2016-05-31 12:07:18 +02:00
system.physmem.avgRdBWSys 2.57 # Average system read bandwidth in MiByte/s
2016-04-09 18:13:40 +02:00
system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2014-10-30 05:18:29 +01:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2016-05-31 12:07:18 +02:00
system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.43 # Average write queue length when enqueuing
system.physmem.readRowHits 93570 # Number of row buffer hits during reads
system.physmem.writeRowHits 49429 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 71.71 # Row buffer hit rate for writes
system.physmem.avgGap 15462261.38 # Average gap between requests
system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 157845240 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 85919625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 459334200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 228024720 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 71920019610 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1621544120250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1874104093725 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.482603 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2641247036500 # Time in different power states
system.physmem_0.memoryStateTime::REF 91875680000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-05-31 12:07:18 +02:00
system.physmem_0.memoryStateTime::ACT 18345228000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-05-31 12:07:18 +02:00
system.physmem_1.actEnergy 139988520 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 76201125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 425778600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 218570400 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 179708830080 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 71085149730 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1620445707000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1872100225455 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.494295 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2642466728000 # Time in different power states
system.physmem_1.memoryStateTime::REF 91875680000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-05-31 12:07:18 +02:00
system.physmem_1.memoryStateTime::ACT 17119309500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-11-03 17:14:42 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
2013-03-01 19:20:30 +01:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walks 4971 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 4971 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 4971 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 4971 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 4971 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 56876140626 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.265788 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -15117011624 -26.58% -26.58% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 71993152250 126.58% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 56876140626 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 2795 68.19% 68.19% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1304 31.81% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 4099 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4971 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4971 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4099 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4099 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 9070 # Table walker requests started/completed, data/inst
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-05-31 17:55:47 +02:00
system.cpu0.dtb.read_hits 12098971 # DTB read hits
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.read_misses 4249 # DTB read misses
2016-05-31 17:55:47 +02:00
system.cpu0.dtb.write_hits 9143699 # DTB write hits
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.write_misses 722 # DTB write misses
system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.flush_entries 2823 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.prefetch_faults 830 # Number of TLB faults due to prefetch
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.perms_faults 174 # Number of TLB faults due to permissions restrictions
2016-05-31 17:55:47 +02:00
system.cpu0.dtb.read_accesses 12103220 # DTB read accesses
system.cpu0.dtb.write_accesses 9144421 # DTB write accesses
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-05-31 17:55:47 +02:00
system.cpu0.dtb.hits 21242670 # DTB hits
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.misses 4971 # DTB misses
2016-05-31 17:55:47 +02:00
system.cpu0.dtb.accesses 21247641 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walks 2431 # Table walker walks requested
system.cpu0.itb.walker.walksShort 2431 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples 2431 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 2431 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 2431 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 56876140626 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 1.265790 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -15117125624 -26.58% -26.58% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 71993266250 126.58% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 56876140626 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 1312 74.72% 74.72% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 444 25.28% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 1756 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2431 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2431 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1756 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1756 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 4187 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 56920666 # ITB inst hits
system.cpu0.itb.inst_misses 2431 # ITB inst misses
2013-03-01 19:20:30 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2016-05-31 12:07:18 +02:00
system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-05-31 12:07:18 +02:00
system.cpu0.itb.flush_entries 1759 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-05-31 12:07:18 +02:00
system.cpu0.itb.inst_accesses 56923097 # ITB inst accesses
system.cpu0.itb.hits 56920666 # DTB hits
system.cpu0.itb.misses 2431 # DTB misses
system.cpu0.itb.accesses 56923097 # DTB accesses
system.cpu0.numCycles 68768248 # number of cpu cycles simulated
2013-03-01 19:20:30 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-05-31 12:07:18 +02:00
system.cpu0.kern.inst.quiesce 3086 # number of quiesce instructions executed
system.cpu0.committedInsts 55456471 # Number of instructions committed
system.cpu0.committedOps 67221308 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 58995481 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4380 # Number of float alu accesses
system.cpu0.num_func_calls 5787158 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 7357632 # number of instructions that are conditional controls
system.cpu0.num_int_insts 58995481 # number of integer instructions
system.cpu0.num_fp_insts 4380 # number of float instructions
system.cpu0.num_int_register_reads 108779991 # number of times the integer registers were read
2016-05-31 17:55:47 +02:00
system.cpu0.num_int_register_writes 41129875 # number of times the integer registers were written
2016-05-31 12:07:18 +02:00
system.cpu0.num_fp_register_reads 3339 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1042 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 204568240 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 24713959 # number of times the CC registers were written
system.cpu0.num_mem_refs 21830038 # number of memory refs
system.cpu0.num_load_insts 12248052 # Number of load instructions
system.cpu0.num_store_insts 9581986 # Number of store instructions
system.cpu0.num_idle_cycles 64949431.464966 # Number of idle cycles
system.cpu0.num_busy_cycles 3818816.535034 # Number of busy cycles
system.cpu0.not_idle_fraction 0.055532 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.944468 # Percentage of idle cycles
system.cpu0.Branches 13461051 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 46425629 67.96% 67.96% # Class of executed instruction
system.cpu0.op_class::IntMult 50781 0.07% 68.04% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 3880 0.01% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.04% # Class of executed instruction
system.cpu0.op_class::MemRead 12248052 17.93% 85.97% # Class of executed instruction
system.cpu0.op_class::MemWrite 9581986 14.03% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-05-31 12:07:18 +02:00
system.cpu0.op_class::total 68312506 # Class of executed instruction
system.cpu0.dcache.tags.replacements 833701 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.996712 # Cycle average of tags in use
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.tags.total_refs 45908569 # Total number of references to valid blocks.
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.sampled_refs 834213 # Sample count of references to valid blocks.
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.tags.avg_refs 55.032191 # Average number of references to valid blocks.
2014-11-03 17:14:42 +01:00
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.062806 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.552141 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.736312 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.645453 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941529 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022563 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009251 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data 0.026651 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.tags.tag_accesses 193086189 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 193086189 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 11466814 # number of ReadReq hits
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.ReadReq_hits::cpu1.data 3604015 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4048059 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data 6693194 # number of ReadReq hits
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.ReadReq_hits::total 25812082 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 8805127 # number of WriteReq hits
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.WriteReq_hits::cpu1.data 2681872 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 3150720 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data 4155645 # number of WriteReq hits
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.WriteReq_hits::total 18793364 # number of WriteReq hits
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178315 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 56771 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 67457 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data 85993 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 388536 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 216736 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 75016 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70705 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 88525 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 450982 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 217763 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76661 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73616 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 92634 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 460674 # number of StoreCondReq hits
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.demand_hits::cpu0.data 20271941 # number of demand (read+write) hits
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.demand_hits::cpu1.data 6285887 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 7198779 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data 10848839 # number of demand (read+write) hits
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.demand_hits::total 44605446 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20450256 # number of overall hits
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.overall_hits::cpu1.data 6342658 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 7266236 # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data 10934832 # number of overall hits
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.overall_hits::total 44993982 # number of overall hits
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.ReadReq_misses::cpu0.data 170779 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 51895 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 83860 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data 219596 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 526130 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 112315 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 34838 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 103940 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data 1226727 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1477820 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 53930 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 19459 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 19330 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data 42725 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 135444 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3695 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2338 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3825 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8068 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 17926 # number of LoadLockedReq misses
2016-04-09 18:13:40 +02:00
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 27 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 283094 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 86733 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 187800 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data 1446323 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2003950 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 337024 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 106192 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 207130 # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data 1489048 # number of overall misses
system.cpu0.dcache.overall_misses::total 2139394 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 835936000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1210061000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3349862000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5395859000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1273084500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5046790496 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 61121830312 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 67441705308 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28644500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 55618500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 110733000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 194996000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 615000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 615000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 2109020500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 6256851496 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 64471692312 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 72837564308 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 2109020500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 6256851496 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 64471692312 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 72837564308 # number of overall miss cycles
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11637593 # number of ReadReq accesses(hits+misses)
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.ReadReq_accesses::cpu1.data 3655910 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4131919 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data 6912790 # number of ReadReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.ReadReq_accesses::total 26338212 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 8917442 # number of WriteReq accesses(hits+misses)
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.WriteReq_accesses::cpu1.data 2716710 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 3254660 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data 5382372 # number of WriteReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.WriteReq_accesses::total 20271184 # number of WriteReq accesses(hits+misses)
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 232245 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76230 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86787 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 128718 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 523980 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 220431 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77354 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 74530 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 96593 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 468908 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 217765 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76661 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73616 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 92661 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 460703 # number of StoreCondReq accesses(hits+misses)
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.demand_accesses::cpu0.data 20555035 # number of demand (read+write) accesses
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.demand_accesses::cpu1.data 6372620 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7386579 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data 12295162 # number of demand (read+write) accesses
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.demand_accesses::total 46609396 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 20787280 # number of overall (read+write) accesses
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.overall_accesses::cpu1.data 6448850 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7473366 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data 12423880 # number of overall (read+write) accesses
2016-05-31 17:55:47 +02:00
system.cpu0.dcache.overall_accesses::total 47133376 # number of overall (read+write) accesses
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014675 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014195 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.020296 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031767 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.019976 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012595 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012824 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.031936 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.227916 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.072903 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.232212 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.255267 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.222729 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.331927 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.258491 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016763 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.030225 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.051322 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.083526 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038229 # miss rate for LoadLockedReq accesses
2016-04-09 18:13:40 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000291 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000063 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013772 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013610 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.025424 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data 0.117634 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.042995 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016213 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016467 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.027716 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119854 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.045390 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16108.218518 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14429.537324 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15254.658555 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10255.752381 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36542.984672 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48554.844102 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49825.128421 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45635.940309 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12251.710864 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14540.784314 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13724.962816 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10877.831083 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 22777.777778 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21206.896552 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24316.240647 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33316.568136 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44576.275363 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 36346.996835 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19860.446173 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30207.364921 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43297.255906 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 34045.886035 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 335985 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 31302 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 12606 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 672 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.652784 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 46.580357 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 692418 # number of writebacks
system.cpu0.dcache.writebacks::total 692418 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 104 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 8524 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 107233 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 115861 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 47971 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1130213 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1178184 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1643 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2350 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5425 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9418 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 104 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 56495 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data 1237446 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1294045 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 104 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 56495 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data 1237446 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1294045 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 51791 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75336 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112363 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 239490 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 34838 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 55969 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96514 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 187321 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19125 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15868 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 29717 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 64710 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 695 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1475 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2643 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4813 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 27 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 86629 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 131305 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data 208877 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 426811 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 105754 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 147173 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data 238594 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 491521 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3424 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 7115 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7790 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18329 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2828 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5194 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6258 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14280 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6252 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12309 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 14048 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32609 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782633000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1020579500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1612658500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3415871000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238246500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2646664500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4858846947 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8743757947 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 247386000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 228071000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 457589000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 933046000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8958000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27255500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 37981000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74194500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 588000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 588000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2020879500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3667244000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6471505447 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 12159628947 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2268265500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3895315000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6929094447 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 13092674947 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 601507000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1484874500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1676185500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3762567000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 601507000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1484874500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1676185500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3762567000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014166 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018233 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016254 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009093 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012824 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017197 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017931 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.250885 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.182838 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.230869 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123497 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008985 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019791 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.027362 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010264 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000291 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013594 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017776 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016989 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.009157 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016399 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019693 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019204 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.010428 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15111.370701 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13547.035946 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14352.220037 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14263.104931 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35542.984672 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47288.043381 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50343.441853 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46677.937588 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12935.215686 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14373.014873 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15398.223239 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14418.884253 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12889.208633 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18478.305085 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14370.412410 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15415.437357 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 21777.777778 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21777.777778 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23327.979083 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27929.203001 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30982.374541 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28489.492883 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21448.507858 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26467.592561 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29041.360835 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26637.061177 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175673.773364 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 208696.345748 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215171.437741 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205279.447869 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96210.332694 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 120633.235844 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119318.443907 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115384.311080 # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements 1971000 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.470268 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 93100004 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1971512 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 47.222641 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 12494493500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 436.802699 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.961360 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.140810 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.565400 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853130 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025315 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.049103 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst 0.071417 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998965 # Average percentage of cache occupancy
2015-07-30 11:16:36 +02:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 260 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
2015-07-30 11:16:36 +02:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-05-31 12:07:18 +02:00
system.cpu0.icache.tags.tag_accesses 97085384 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 97085384 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 56179314 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 17648655 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 9977787 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst 9294248 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 93100004 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 56179314 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 17648655 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 9977787 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst 9294248 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 93100004 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 56179314 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 17648655 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 9977787 # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst 9294248 # number of overall hits
system.cpu0.icache.overall_hits::total 93100004 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 743108 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 211772 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 473406 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst 585545 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 2013831 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 743108 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 211772 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 473406 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst 585545 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 2013831 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 743108 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 211772 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 473406 # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst 585545 # number of overall misses
system.cpu0.icache.overall_misses::total 2013831 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2898883500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6546923000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7956020485 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 17401826985 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2898883500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 6546923000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst 7956020485 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 17401826985 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2898883500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 6546923000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst 7956020485 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 17401826985 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 56922422 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 17860427 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 10451193 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst 9879793 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 95113835 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 56922422 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 17860427 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 10451193 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst 9879793 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 95113835 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 56922422 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 17860427 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 10451193 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst 9879793 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 95113835 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013055 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011857 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.045297 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.059267 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.021173 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013055 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011857 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.045297 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst 0.059267 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.021173 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013055 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011857 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.045297 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst 0.059267 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.021173 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13688.700584 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13829.404359 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13587.376692 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8641.155581 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13688.700584 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13829.404359 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13587.376692 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8641.155581 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13688.700584 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13829.404359 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13587.376692 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8641.155581 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4652 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-05-31 12:07:18 +02:00
system.cpu0.icache.blocked::no_mshrs 239 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-05-31 12:07:18 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.464435 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-05-31 12:07:18 +02:00
system.cpu0.icache.writebacks::writebacks 1971000 # number of writebacks
system.cpu0.icache.writebacks::total 1971000 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 42282 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 42282 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst 42282 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 42282 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst 42282 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 42282 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 211772 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 473406 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 543263 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1228441 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 211772 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 473406 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst 543263 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1228441 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 211772 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 473406 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst 543263 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1228441 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2687111500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6073517000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7028549489 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 15789177989 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2687111500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6073517000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7028549489 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 15789177989 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2687111500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6073517000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7028549489 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 15789177989 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011857 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045297 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054987 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012915 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011857 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045297 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054987 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011857 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045297 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054987 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12688.700584 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12937.655406 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12853.021015 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12688.700584 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12937.655406 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12853.021015 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12688.700584 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12937.655406 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12853.021015 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walks 2016 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 2016 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 564 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1452 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 2016 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 2016 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 2016 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 1645 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12118.844985 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10271.833283 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 6851.972198 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.91% 0.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::4096-6143 468 28.45% 29.36% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::6144-8191 121 7.36% 36.72% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::10240-12287 510 31.00% 67.72% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::12288-14335 106 6.44% 74.16% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::14336-16383 70 4.26% 78.42% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-18431 12 0.73% 79.15% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::22528-24575 321 19.51% 98.66% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-26623 22 1.34% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 1645 # Table walker service (enqueue to completion) latency
2015-07-31 18:04:59 +02:00
system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walkPageSizes::4K 1089 66.20% 66.20% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 556 33.80% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 1645 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2016 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2016 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1645 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1645 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 3661 # Table walker requests started/completed, data/inst
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.read_hits 3812918 # DTB read hits
system.cpu1.dtb.read_misses 1745 # DTB read misses
system.cpu1.dtb.write_hits 2796286 # DTB write hits
system.cpu1.dtb.write_misses 271 # DTB write misses
system.cpu1.dtb.flush_tlb 154 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.flush_entries 1302 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.prefetch_faults 243 # Number of TLB faults due to prefetch
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.perms_faults 87 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 3814663 # DTB read accesses
system.cpu1.dtb.write_accesses 2796557 # DTB write accesses
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.hits 6609204 # DTB hits
system.cpu1.dtb.misses 2016 # DTB misses
system.cpu1.dtb.accesses 6611220 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walks 1033 # Table walker walks requested
system.cpu1.itb.walker.walksShort 1033 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 205 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 828 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 1033 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 1033 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 1033 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 765 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12816.993464 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10782.034364 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 7152.863364 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-6143 258 33.73% 33.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::10240-12287 199 26.01% 59.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-14335 58 7.58% 67.32% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::14336-16383 58 7.58% 74.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-18431 1 0.13% 75.03% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::22528-24575 183 23.92% 98.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-26623 8 1.05% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 765 # Table walker service (enqueue to completion) latency
2015-07-31 18:04:59 +02:00
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkPageSizes::4K 560 73.20% 73.20% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 205 26.80% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 765 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1033 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1033 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 765 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 765 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 1798 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 17860427 # ITB inst hits
system.cpu1.itb.inst_misses 1033 # ITB inst misses
2013-03-01 19:20:30 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2016-05-31 12:07:18 +02:00
system.cpu1.itb.flush_tlb 154 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-05-31 12:07:18 +02:00
system.cpu1.itb.flush_entries 792 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-05-31 12:07:18 +02:00
system.cpu1.itb.inst_accesses 17861460 # ITB inst accesses
system.cpu1.itb.hits 17860427 # DTB hits
system.cpu1.itb.misses 1033 # DTB misses
system.cpu1.itb.accesses 17861460 # DTB accesses
system.cpu1.numCycles 143797366 # number of cpu cycles simulated
2013-03-01 19:20:30 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
2016-05-31 12:07:18 +02:00
system.cpu1.committedInsts 17268414 # Number of instructions committed
system.cpu1.committedOps 20827213 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 18584422 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1582 # Number of float alu accesses
system.cpu1.num_func_calls 1992181 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 2177842 # number of instructions that are conditional controls
system.cpu1.num_int_insts 18584422 # number of integer instructions
system.cpu1.num_fp_insts 1582 # number of float instructions
system.cpu1.num_int_register_reads 34435383 # number of times the integer registers were read
system.cpu1.num_int_register_writes 13029372 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1129 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 454 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 75826477 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 7417953 # number of times the CC registers were written
system.cpu1.num_mem_refs 6811480 # number of memory refs
system.cpu1.num_load_insts 3856412 # Number of load instructions
system.cpu1.num_store_insts 2955068 # Number of store instructions
system.cpu1.num_idle_cycles 136802879.005961 # Number of idle cycles
system.cpu1.num_busy_cycles 6994486.994039 # Number of busy cycles
system.cpu1.not_idle_fraction 0.048641 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.951359 # Percentage of idle cycles
system.cpu1.Branches 4283216 # Number of branches fetched
system.cpu1.op_class::No_OpClass 49 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 14611363 68.15% 68.15% # Class of executed instruction
system.cpu1.op_class::IntMult 16029 0.07% 68.23% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 979 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.23% # Class of executed instruction
system.cpu1.op_class::MemRead 3856412 17.99% 86.22% # Class of executed instruction
system.cpu1.op_class::MemWrite 2955068 13.78% 100.00% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-05-31 12:07:18 +02:00
system.cpu1.op_class::total 21439900 # Class of executed instruction
system.cpu2.branchPred.lookups 5566129 # Number of BP lookups
system.cpu2.branchPred.condPredicted 2825980 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 493463 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 3182486 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 1660276 # Number of BTB hits
2013-03-01 19:20:30 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-05-31 12:07:18 +02:00
system.cpu2.branchPred.BTBHitPct 52.169153 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 1582499 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 327011 # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups 671898 # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits 638941 # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses 32957 # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted 21982 # Number of mispredicted indirect branches.
2014-12-23 15:31:20 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu2.dtb.walker.walks 11822 # Table walker walks requested
system.cpu2.dtb.walker.walksShort 11822 # Table walker walks initiated with short descriptors
system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7337 # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4485 # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples 11822 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0 11822 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 11822 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 2048 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 12710.205078 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 10939.246339 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 6922.657260 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-8191 574 28.03% 28.03% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1046 51.07% 79.10% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::16384-24575 414 20.21% 99.32% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::24576-32767 12 0.59% 99.90% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 2048 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 2000043000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000043000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000043000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K 1270 62.01% 62.01% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::1M 778 37.99% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 2048 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 11822 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 11822 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2048 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2048 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 13870 # Table walker requests started/completed, data/inst
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
2016-05-31 12:07:18 +02:00
system.cpu2.dtb.read_hits 4336552 # DTB read hits
system.cpu2.dtb.read_misses 10662 # DTB read misses
system.cpu2.dtb.write_hits 3355101 # DTB write hits
system.cpu2.dtb.write_misses 1160 # DTB write misses
system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-05-31 12:07:18 +02:00
system.cpu2.dtb.flush_entries 1478 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 270 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu2.dtb.perms_faults 127 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 4347214 # DTB read accesses
system.cpu2.dtb.write_accesses 3356261 # DTB write accesses
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
2016-05-31 12:07:18 +02:00
system.cpu2.dtb.hits 7691653 # DTB hits
system.cpu2.dtb.misses 11822 # DTB misses
system.cpu2.dtb.accesses 7703475 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu2.itb.walker.walks 1331 # Table walker walks requested
system.cpu2.itb.walker.walksShort 1331 # Table walker walks initiated with short descriptors
system.cpu2.itb.walker.walksShortTerminationLevel::Level1 253 # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1078 # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples 1331 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0 1331 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 1331 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 850 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 12864.705882 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 11157.048638 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 6541.427390 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::4096-6143 256 30.12% 30.12% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::10240-12287 237 27.88% 58.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::12288-14335 63 7.41% 65.41% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::14336-16383 116 13.65% 79.06% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::22528-24575 176 20.71% 99.76% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::24576-26623 2 0.24% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 850 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 2000028500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000028500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000028500 # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K 607 71.41% 71.41% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::1M 243 28.59% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 850 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1331 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1331 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 850 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 850 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 2181 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 10452986 # ITB inst hits
system.cpu2.itb.inst_misses 1331 # ITB inst misses
2013-03-01 19:20:30 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
2016-05-31 12:07:18 +02:00
system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-05-31 12:07:18 +02:00
system.cpu2.itb.flush_entries 885 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu2.itb.perms_faults 1709 # Number of TLB faults due to permissions restrictions
2013-03-01 19:20:30 +01:00
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
2016-05-31 12:07:18 +02:00
system.cpu2.itb.inst_accesses 10454317 # ITB inst accesses
system.cpu2.itb.hits 10452986 # DTB hits
system.cpu2.itb.misses 1331 # DTB misses
system.cpu2.itb.accesses 10454317 # DTB accesses
system.cpu2.numCycles 141973763 # number of cpu cycles simulated
2013-03-01 19:20:30 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-05-31 12:07:18 +02:00
system.cpu2.committedInsts 19207375 # Number of instructions committed
system.cpu2.committedOps 23288496 # Number of ops (including micro ops) committed
system.cpu2.discardedOps 1385563 # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends 546 # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles 36865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi 7.391628 # CPI: cycles per instruction
system.cpu2.ipc 0.135288 # IPC: instructions per cycle
system.cpu2.op_class_0::No_OpClass 48 0.00% 0.00% # Class of committed instruction
system.cpu2.op_class_0::IntAlu 15543125 66.74% 66.74% # Class of committed instruction
system.cpu2.op_class_0::IntMult 18693 0.08% 66.82% # Class of committed instruction
system.cpu2.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMisc 1356 0.01% 66.83% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction
system.cpu2.op_class_0::MemRead 4252165 18.26% 85.09% # Class of committed instruction
system.cpu2.op_class_0::MemWrite 3473109 14.91% 100.00% # Class of committed instruction
2016-04-09 18:13:40 +02:00
system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-05-31 12:07:18 +02:00
system.cpu2.op_class_0::total 23288496 # Class of committed instruction
2015-07-30 11:16:36 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
2016-05-31 12:07:18 +02:00
system.cpu2.tickCycles 41357618 # Number of cycles that the object actually ticked
system.cpu2.idleCycles 100616145 # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups 13553669 # Number of BP lookups
system.cpu3.branchPred.condPredicted 7461566 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 296736 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 8400668 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 4438644 # Number of BTB hits
2015-07-30 11:16:36 +02:00
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-05-31 12:07:18 +02:00
system.cpu3.branchPred.BTBHitPct 52.836798 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 3086842 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 16263 # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups 2014355 # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits 1952666 # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses 61689 # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted 18072 # Number of mispredicted indirect branches.
2015-07-30 11:16:36 +02:00
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu3.dtb.walker.walks 34281 # Table walker walks requested
system.cpu3.dtb.walker.walksShort 34281 # Table walker walks initiated with short descriptors
system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10962 # Level at which table walker walks with short descriptors terminate
system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8120 # Level at which table walker walks with short descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore 15199 # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples 19082 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean 497.143905 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 3025.740716 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-8191 18625 97.61% 97.61% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::8192-16383 304 1.59% 99.20% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::16384-24575 96 0.50% 99.70% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::24576-32767 29 0.15% 99.85% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::32768-40959 9 0.05% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::40960-49151 16 0.08% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::49152-57343 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total 19082 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples 6403 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 11721.380603 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 9562.982056 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 7657.065586 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-8191 2445 38.19% 38.19% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2784 43.48% 81.66% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::16384-24575 982 15.34% 97.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::24576-32767 97 1.51% 98.52% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::32768-40959 43 0.67% 99.19% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::40960-49151 36 0.56% 99.75% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::49152-57343 11 0.17% 99.92% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-73727 1 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total 6403 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -8551346564 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean 0.449587 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::stdev 0.363024 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-1 -8598250064 100.55% 100.55% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::2-3 33569000 -0.39% 100.16% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-5 6441000 -0.08% 100.08% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::6-7 2603000 -0.03% 100.05% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-9 1836000 -0.02% 100.03% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::10-11 609000 -0.01% 100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-13 358000 -0.00% 100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::14-15 901500 -0.01% 100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-17 248500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::18-19 75500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-21 42000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::22-23 21500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-25 24500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::26-27 20500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-29 9000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::30-31 144500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -8551346564 # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K 1841 71.89% 71.89% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::1M 720 28.11% 100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total 2561 # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34281 # Table walker requests started/completed, data/inst
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34281 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2561 # Table walker requests started/completed, data/inst
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2561 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total 36842 # Table walker requests started/completed, data/inst
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
2016-05-31 12:07:18 +02:00
system.cpu3.dtb.read_hits 7461875 # DTB read hits
system.cpu3.dtb.read_misses 28710 # DTB read misses
system.cpu3.dtb.write_hits 5703324 # DTB write hits
system.cpu3.dtb.write_misses 5571 # DTB write misses
system.cpu3.dtb.flush_tlb 157 # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-05-31 12:07:18 +02:00
system.cpu3.dtb.flush_entries 1703 # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 376 # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu3.dtb.perms_faults 330 # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses 7490585 # DTB read accesses
system.cpu3.dtb.write_accesses 5708895 # DTB write accesses
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
2016-05-31 12:07:18 +02:00
system.cpu3.dtb.hits 13165199 # DTB hits
system.cpu3.dtb.misses 34281 # DTB misses
system.cpu3.dtb.accesses 13199480 # DTB accesses
2015-07-30 11:16:36 +02:00
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-05-31 12:07:18 +02:00
system.cpu3.itb.walker.walks 4255 # Table walker walks requested
system.cpu3.itb.walker.walksShort 4255 # Table walker walks initiated with short descriptors
system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1348 # Level at which table walker walks with short descriptors terminate
system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2480 # Level at which table walker walks with short descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore 427 # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples 3828 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean 1433.646813 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 5723.775049 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-8191 3573 93.34% 93.34% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::8192-16383 172 4.49% 97.83% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::16384-24575 42 1.10% 98.93% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::24576-32767 19 0.50% 99.43% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.63% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::40960-49151 2 0.05% 99.69% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::49152-57343 3 0.08% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::57344-65535 3 0.08% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-73727 3 0.08% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-106495 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total 3828 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples 1607 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 11553.827007 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 9422.694802 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 7714.919558 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-8191 693 43.12% 43.12% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::8192-16383 629 39.14% 82.27% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::16384-24575 247 15.37% 97.64% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::24576-32767 18 1.12% 98.76% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::32768-40959 11 0.68% 99.44% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::40960-49151 4 0.25% 99.69% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::49152-57343 2 0.12% 99.81% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::57344-65535 2 0.12% 99.94% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total 1607 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -8760206064 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean 0.998053 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev 0.036484 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0 -15003296 0.17% 0.17% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1 -8746780268 99.85% 100.02% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2 1238500 -0.01% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3 234500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4 77000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5 27500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -8760206064 # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K 845 71.61% 71.61% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::1M 335 28.39% 100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total 1180 # Table walker page sizes translated
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4255 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4255 # Table walker requests started/completed, data/inst
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-05-31 12:07:18 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1180 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1180 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total 5435 # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits 9881127 # ITB inst hits
system.cpu3.itb.inst_misses 4255 # ITB inst misses
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
2016-05-31 12:07:18 +02:00
system.cpu3.itb.flush_tlb 157 # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA
2015-07-30 11:16:36 +02:00
system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-05-31 12:07:18 +02:00
system.cpu3.itb.flush_entries 1190 # Number of entries that have been flushed from TLB
2015-07-30 11:16:36 +02:00
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-05-31 12:07:18 +02:00
system.cpu3.itb.perms_faults 704 # Number of TLB faults due to permissions restrictions
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
2016-05-31 12:07:18 +02:00
system.cpu3.itb.inst_accesses 9885382 # ITB inst accesses
system.cpu3.itb.hits 9881127 # DTB hits
system.cpu3.itb.misses 4255 # DTB misses
system.cpu3.itb.accesses 9885382 # DTB accesses
system.cpu3.numCycles 55785273 # number of cpu cycles simulated
2015-07-30 11:16:36 +02:00
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-05-31 12:07:18 +02:00
system.cpu3.fetch.icacheStallCycles 20908003 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 53885921 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 13553669 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 9478152 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 32386359 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 1568366 # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles 62721 # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles 789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles 205 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles 111844 # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles 71140 # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines 9879794 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 204446 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes 2262 # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples 54325621 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.196451 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.331638 # Number of instructions fetched each cycle (Total)
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-05-31 12:07:18 +02:00
system.cpu3.fetch.rateDist::0 39861207 73.37% 73.37% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 1851185 3.41% 76.78% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 1193872 2.20% 78.98% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 3684209 6.78% 85.76% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 942616 1.74% 87.50% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 608186 1.12% 88.62% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 2968602 5.46% 94.08% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 642558 1.18% 95.26% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 2573186 4.74% 100.00% # Number of instructions fetched each cycle (Total)
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-05-31 12:07:18 +02:00
system.cpu3.fetch.rateDist::total 54325621 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.242961 # Number of branch fetches per cycle
system.cpu3.fetch.rate 0.965952 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 14640830 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 30019697 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 7950688 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 1013386 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 700819 # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved 1055619 # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred 84442 # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts 46804919 # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts 276831 # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles 700819 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 15165685 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 3026849 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 21377967 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 8430789 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 5623288 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 44934032 # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents 688 # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents 1185922 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 108960 # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents 3941702 # Number of times rename has blocked due to SQ full
system.cpu3.rename.RenamedOperands 46859897 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 206328923 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 50493322 # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups 4028 # Number of floating rename lookups
system.cpu3.rename.CommittedMaps 39227152 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 7632745 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 719514 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 667644 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 5723010 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 7961886 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 6281204 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 1151663 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 1548732 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 43283754 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 518690 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 41211343 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 55539 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 6082671 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 14073441 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 54569 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 54325621 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 0.758599 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.457347 # Number of insts issued each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-05-31 12:07:18 +02:00
system.cpu3.iq.issued_per_cycle::0 38109275 70.15% 70.15% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 5329887 9.81% 79.96% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 4096389 7.54% 87.50% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 3334773 6.14% 93.64% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 1373143 2.53% 96.17% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 820036 1.51% 97.68% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 873869 1.61% 99.29% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 257599 0.47% 99.76% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 130650 0.24% 100.00% # Number of insts issued each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-05-31 12:07:18 +02:00
system.cpu3.iq.issued_per_cycle::total 54325621 # Number of insts issued each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu3.iq.fu_full::IntAlu 64574 10.28% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 290075 46.19% 56.47% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 273390 43.53% 100.00% # attempts to use FU when none available
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-05-31 12:07:18 +02:00
system.cpu3.iq.FU_type_0::No_OpClass 62 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 27512271 66.76% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 31067 0.08% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.83% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 2328 0.01% 66.84% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 66.84% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.84% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 7676586 18.63% 85.47% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 5989019 14.53% 100.00% # Type of FU issued
2015-07-30 11:16:36 +02:00
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-05-31 12:07:18 +02:00
system.cpu3.iq.FU_type_0::total 41211343 # Type of FU issued
system.cpu3.iq.rate 0.738750 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 628039 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.015239 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 137423296 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 49907895 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 40057354 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 8589 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 4965 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 3611 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 41834646 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 4674 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 172531 # Number of loads that had data forwarded from stores
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-05-31 12:07:18 +02:00
system.cpu3.iew.lsq.thread0.squashedLoads 1192076 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 1205 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 28350 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 578137 # Number of stores squashed
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-05-31 12:07:18 +02:00
system.cpu3.iew.lsq.thread0.rescheduledLoads 104077 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 43928 # Number of times an access to memory failed due to the cache being blocked
2015-07-30 11:16:36 +02:00
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-05-31 12:07:18 +02:00
system.cpu3.iew.iewSquashCycles 700819 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 2631103 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 281724 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 43863625 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 65733 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 7961886 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 6281204 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 267636 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 25569 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 250025 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 28350 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 127807 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 129932 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 257739 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 40889959 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 7546719 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 287191 # Number of squashed instructions skipped in execute
2015-07-30 11:16:36 +02:00
system.cpu3.iew.exec_swp 0 # number of swp insts executed
2016-05-31 12:07:18 +02:00
system.cpu3.iew.exec_nop 61181 # number of nop insts executed
system.cpu3.iew.exec_refs 13479054 # number of memory reference insts executed
system.cpu3.iew.exec_branches 7536416 # Number of branches executed
system.cpu3.iew.exec_stores 5932335 # Number of stores executed
system.cpu3.iew.exec_rate 0.732988 # Inst execution rate
system.cpu3.iew.wb_sent 40598245 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 40060965 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 21086862 # num instructions producing a value
system.cpu3.iew.wb_consumers 37255215 # num instructions consuming a value
system.cpu3.iew.wb_rate 0.718128 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.566011 # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts 6097187 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 464121 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 213352 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 53027988 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 0.712050 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 1.609623 # Number of insts commited each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-05-31 12:07:18 +02:00
system.cpu3.commit.committed_per_cycle::0 38640336 72.87% 72.87% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 6301176 11.88% 84.75% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 3204029 6.04% 90.79% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 1405492 2.65% 93.44% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 791559 1.49% 94.94% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 551412 1.04% 95.98% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 959183 1.81% 97.78% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 243958 0.46% 98.24% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 930843 1.76% 100.00% # Number of insts commited each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-05-31 12:07:18 +02:00
system.cpu3.commit.committed_per_cycle::total 53027988 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 30988188 # Number of instructions committed
system.cpu3.commit.committedOps 37758554 # Number of ops (including micro ops) committed
2015-07-30 11:16:36 +02:00
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
2016-05-31 12:07:18 +02:00
system.cpu3.commit.refs 12472877 # Number of memory references committed
system.cpu3.commit.loads 6769810 # Number of loads committed
system.cpu3.commit.membars 181184 # Number of memory barriers committed
system.cpu3.commit.branches 7122308 # Number of branches committed
system.cpu3.commit.fp_insts 3347 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 32924881 # Number of committed integer instructions.
system.cpu3.commit.function_calls 1244375 # Number of function calls committed.
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-05-31 12:07:18 +02:00
system.cpu3.commit.op_class_0::IntAlu 25253254 66.88% 66.88% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 30097 0.08% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.96% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc 2326 0.01% 66.97% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.97% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.97% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.97% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead 6769810 17.93% 84.90% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 5703067 15.10% 100.00% # Class of committed instruction
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-05-31 12:07:18 +02:00
system.cpu3.commit.op_class_0::total 37758554 # Class of committed instruction
system.cpu3.commit.bw_lim_events 930843 # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads 90355965 # The number of ROB reads
system.cpu3.rob.rob_writes 89008997 # The number of ROB writes
system.cpu3.timesIdled 227180 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 1459652 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 5161855344 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 30949407 # Number of Instructions Simulated
system.cpu3.committedOps 37719773 # Number of Ops (including micro ops) Simulated
system.cpu3.cpi 1.802467 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 1.802467 # CPI: Total CPI of All Threads
system.cpu3.ipc 0.554795 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 0.554795 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 44810806 # number of integer regfile reads
system.cpu3.int_regfile_writes 25112765 # number of integer regfile writes
system.cpu3.fp_regfile_reads 14550 # number of floating regfile reads
system.cpu3.fp_regfile_writes 12084 # number of floating regfile writes
system.cpu3.cc_regfile_reads 144202792 # number of cc regfile reads
system.cpu3.cc_regfile_writes 15932581 # number of cc regfile writes
system.cpu3.misc_regfile_reads 74870960 # number of misc regfile reads
system.cpu3.misc_regfile_writes 343753 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 30152 # Transaction distribution
system.iobus.trans_dist::ReadResp 30152 # Transaction distribution
2015-07-30 11:16:36 +02:00
system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
system.iobus.trans_dist::WriteResp 59010 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178324 # Packet count per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 30018500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer2.occupancy 228500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer3.occupancy 20000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer10.occupancy 1500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks)
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer23.occupancy 3980500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer24.occupancy 22050500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer25.occupancy 72564537 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.respLayer0.occupancy 50308000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.iocache.tags.replacements 36410 # number of replacements
system.iocache.tags.tagsinuse 1.002475 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 248713478009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.002475 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062655 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062655 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-05-31 12:07:18 +02:00
system.iocache.tags.tag_accesses 327996 # Number of tag accesses
system.iocache.tags.data_accesses 327996 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses
system.iocache.ReadReq_misses::total 220 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-04-21 10:48:24 +02:00
system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses
system.iocache.demand_misses::total 36444 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36444 # number of overall misses
system.iocache.overall_misses::total 36444 # number of overall misses
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_miss_latency::realview.ide 16064414 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 16064414 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 1679848123 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 1679848123 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 1695912537 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1695912537 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 1695912537 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1695912537 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-05-31 12:07:18 +02:00
system.iocache.demand_accesses::realview.ide 36444 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36444 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36444 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36444 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2016-05-31 12:07:18 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 73020.063636 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 73020.063636 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46373.899155 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 46373.899155 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 46534.752963 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 46534.752963 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 46534.752963 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 46534.752963 # average overall miss latency
2016-02-10 10:08:27 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2013-03-01 19:20:30 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2013-03-01 19:20:30 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2013-03-01 19:20:30 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-05-31 12:07:18 +02:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 135 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 135 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 13984 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 13984 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 14119 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 14119 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 14119 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 14119 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 9314414 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 9314414 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 979789535 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 979789535 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 989103949 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 989103949 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 989103949 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 989103949 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.613636 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.386042 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.386042 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.387416 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.387416 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.387416 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.387416 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68995.659259 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68995.659259 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70065.041118 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70065.041118 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70054.816134 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70054.816134 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70054.816134 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70054.816134 # average overall mshr miss latency
system.l2c.tags.replacements 100820 # number of replacements
system.l2c.tags.tagsinuse 65104.875407 # Cycle average of tags in use
system.l2c.tags.total_refs 5136845 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 165990 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 30.946714 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 79348480000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 49045.638268 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902700 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.002962 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4655.400387 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 1832.462463 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000002 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 777.111964 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 859.577397 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.871513 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006796 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2228.936773 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 823.872322 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker 51.838280 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker 0.001832 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 2977.448230 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 1828.803519 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.748377 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
2016-05-31 12:07:18 +02:00
system.l2c.tags.occ_percent::cpu0.inst 0.071036 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.027961 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.011858 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.013116 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000318 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.034011 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.012571 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000791 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.045432 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.027905 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993422 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65111 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2175 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 8177 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54718 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.993515 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 45392022 # Number of tag accesses
system.l2c.tags.data_accesses 45392022 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 4238 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 2128 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 1538 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 869 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 12508 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 1155 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker 20749 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker 3757 # number of ReadReq hits
system.l2c.ReadReq_hits::total 46942 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 692418 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 692418 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 1933833 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 1933833 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 5 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 8 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data 33 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 59 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 19 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 20 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 66454 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 22443 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 25986 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data 44665 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 159548 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 735257 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 209850 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 468084 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 537076 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1950267 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 223299 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 69198 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 90522 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 140283 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 523302 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 4238 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 2128 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 735257 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 289753 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 1538 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 869 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 209850 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 91641 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 12508 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 1155 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 468084 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 116508 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker 20749 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker 3757 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 537076 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 184948 # number of demand (read+write) hits
system.l2c.demand_hits::total 2680059 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 4238 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 2128 # number of overall hits
system.l2c.overall_hits::cpu0.inst 735257 # number of overall hits
system.l2c.overall_hits::cpu0.data 289753 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 1538 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 869 # number of overall hits
system.l2c.overall_hits::cpu1.inst 209850 # number of overall hits
system.l2c.overall_hits::cpu1.data 91641 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 12508 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 1155 # number of overall hits
system.l2c.overall_hits::cpu2.inst 468084 # number of overall hits
system.l2c.overall_hits::cpu2.data 116508 # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker 20749 # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker 3757 # number of overall hits
system.l2c.overall_hits::cpu3.inst 537076 # number of overall hits
system.l2c.overall_hits::cpu3.data 184948 # number of overall hits
system.l2c.overall_hits::total 2680059 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
2016-04-09 18:13:40 +02:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_misses::cpu2.dtb.walker 28 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker 70 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::total 108 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1106 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 476 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 434 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 737 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2753 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
2016-04-09 18:13:40 +02:00
system.l2c.SCUpgradeReq_misses::cpu3.data 8 # number of SCUpgradeReq misses
2016-05-31 12:07:18 +02:00
system.l2c.SCUpgradeReq_misses::total 9 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 44742 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 11914 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 29542 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 51083 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 137281 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 7847 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 1919 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 5317 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst 6049 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 21132 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 5105 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 2413 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 2156 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data 4436 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 14110 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7847 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 49847 # number of demand (read+write) misses
2016-04-09 18:13:40 +02:00
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
2016-05-31 12:07:18 +02:00
system.l2c.demand_misses::cpu1.inst 1919 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 14327 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 28 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 5317 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 31698 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker 70 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 6049 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 55519 # number of demand (read+write) misses
system.l2c.demand_misses::total 172631 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 7847 # number of overall misses
system.l2c.overall_misses::cpu0.data 49847 # number of overall misses
2016-04-09 18:13:40 +02:00
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
2016-05-31 12:07:18 +02:00
system.l2c.overall_misses::cpu1.inst 1919 # number of overall misses
system.l2c.overall_misses::cpu1.data 14327 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 28 # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu2.inst 5317 # number of overall misses
system.l2c.overall_misses::cpu2.data 31698 # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker 70 # number of overall misses
system.l2c.overall_misses::cpu3.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu3.inst 6049 # number of overall misses
system.l2c.overall_misses::cpu3.data 55519 # number of overall misses
system.l2c.overall_misses::total 172631 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 97500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2372500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker 83500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 6041500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.itb.walker 84000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 8679000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 29500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 146500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data 262500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 438500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu3.data 220500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 220500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 936065500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 2275299000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 4215756000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7427120500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 158684500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 437741000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 503851499 # number of ReadCleanReq miss cycles
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system.l2c.WritebackDirty_accesses::writebacks 692418 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 692418 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 1933833 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 1933833 # number of WritebackClean accesses(hits+misses)
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2016-04-09 18:13:40 +02:00
system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses)
2016-05-31 12:07:18 +02:00
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system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989605 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.981900 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 0.957143 # miss rate for UpgradeReq accesses
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system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.011137 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.010719 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.022351 # miss rate for ReadSharedReq accesses
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system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.023263 # miss rate for ReadSharedReq accesses
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2014-11-12 15:05:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-05-31 12:07:18 +02:00
system.l2c.writebacks::writebacks 92494 # number of writebacks
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2016-04-09 18:13:40 +02:00
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2016-05-31 12:07:18 +02:00
system.l2c.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
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2016-04-09 18:13:40 +02:00
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2016-05-31 12:07:18 +02:00
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2016-04-09 18:13:40 +02:00
system.l2c.overall_mshr_hits::cpu3.inst 5 # number of overall MSHR hits
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_hits::cpu3.data 45 # number of overall MSHR hits
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2016-04-09 18:13:40 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
2016-05-31 12:07:18 +02:00
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system.l2c.UpgradeReq_mshr_misses::cpu1.data 476 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 434 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 737 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 1647 # number of UpgradeReq MSHR misses
2016-04-09 18:13:40 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 8 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses
2016-05-31 12:07:18 +02:00
system.l2c.ReadExReq_mshr_misses::cpu1.data 11914 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 29542 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 51083 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 92539 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1919 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5313 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 6044 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 13276 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2413 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 2135 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 4391 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 8939 # number of ReadSharedReq MSHR misses
2016-04-09 18:13:40 +02:00
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
2016-05-31 12:07:18 +02:00
system.l2c.demand_mshr_misses::cpu1.inst 1919 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 14327 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 28 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 5313 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 31677 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker 70 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 6044 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 55474 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 114855 # number of demand (read+write) MSHR misses
2016-04-09 18:13:40 +02:00
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_misses::cpu1.inst 1919 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 14327 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 28 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 5313 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 31677 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker 70 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 6044 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 55474 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 114855 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3424 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 7115 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data 7790 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 18329 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2828 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 5194 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data 6258 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 14280 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6252 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 12309 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data 14048 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 32609 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 87500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2092500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 73500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 5341500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 74000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 7669000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 9032000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 8238000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 14019000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 31289000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 256500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 256500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 816925500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1979879000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 3704926000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 6501730500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 139494500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 384461500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 443095000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 967051000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 178677500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 155184000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 345817500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 679679000 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 87500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 139494500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 995603000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2092500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 73500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 384461500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 2135063000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 5341500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 74000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 443095000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 4050743500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 8156129500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 87500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 139494500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 995603000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2092500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 73500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 384461500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 2135063000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 5341500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 74000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 443095000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 4050743500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 8156129500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 558688000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1395919500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1578780500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3533388000 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 558688000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1395919500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1578780500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 3533388000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000650 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002234 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000865 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003362 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.002147 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989605 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.981900 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.957143 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.585704 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.296296 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.275862 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.346771 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.532020 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.533515 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.311759 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009062 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011223 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.011128 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006734 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033696 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.023037 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.030342 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016633 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000650 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009062 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.135201 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002234 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000865 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011223 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.213736 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003362 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011128 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.230693 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.040262 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000650 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009062 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.135201 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002234 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000865 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011223 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.213736 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003362 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.000266 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011128 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.230693 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.040262 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 75930.693069 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18974.789916 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18981.566820 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19021.709634 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18997.571342 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 32062.500000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 32062.500000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68568.532819 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67019.125313 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72527.572774 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 70259.355515 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73311.548643 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72842.045797 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74047.865727 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72685.714286 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78755.978137 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76035.238841 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73311.548643 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73020.577207 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 71012.402595 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 87500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72691.245440 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69491.379912 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74732.142857 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72362.412949 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67401.048079 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 76307.142857 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73311.548643 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73020.577207 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 71012.402595 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163168.224299 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196193.886156 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202667.586650 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192775.819739 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89361.484325 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113406.409944 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112384.716686 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 108356.220675 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 348991 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 146410 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-07-30 11:16:36 +02:00
system.membus.trans_dist::ReadReq 40114 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.membus.trans_dist::ReadResp 75609 # Transaction distribution
2015-07-30 11:16:36 +02:00
system.membus.trans_dist::WriteReq 27565 # Transaction distribution
system.membus.trans_dist::WriteResp 27565 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.membus.trans_dist::WritebackDirty 128684 # Transaction distribution
system.membus.trans_dist::CleanEvict 8545 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4547 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1834 # Transaction distribution
system.membus.trans_dist::ReadExReq 135487 # Transaction distribution
system.membus.trans_dist::ReadExResp 135487 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 35495 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 22240 # Transaction distribution
2015-07-30 11:16:36 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 476439 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 583891 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95179 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 95179 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 679070 # Packet count per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16891580 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 17054705 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 19376305 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 335 # Total snoops (count)
system.membus.snoop_fanout::samples 342553 # Request fanout histogram
system.membus.snoop_fanout::mean 0.015446 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.123318 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::0 337262 98.46% 98.46% # Request fanout histogram
system.membus.snoop_fanout::1 5291 1.54% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::total 342553 # Request fanout histogram
system.membus.reqLayer0.occupancy 56458000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.membus.reqLayer2.occupancy 682999 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.membus.reqLayer5.occupancy 493971550 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.membus.respLayer2.occupancy 649041000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.membus.respLayer3.occupancy 721087 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoop_filter.tot_requests 5640723 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2834949 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 44718 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 306 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-05-31 12:07:18 +02:00
system.toL2Bus.trans_dist::ReadReq 110707 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2619793 # Transaction distribution
2015-07-30 11:16:36 +02:00
system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.toL2Bus.trans_dist::WritebackDirty 747367 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1971000 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 146335 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2812 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2841 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 296829 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296829 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1971549 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 537547 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 4488 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5931996 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2625304 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25197 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99111 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 8681608 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252349880 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97897081 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 40804 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 174056 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 350461821 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 123025 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 4134634 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.021870 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.146260 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoop_fanout::0 4044208 97.81% 97.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 90426 2.19% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoop_fanout::total 4134634 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 3415021456 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoopLayer0.occupancy 230913 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer0.occupancy 1843284752 # Layer occupancy (ticks)
2015-07-30 11:16:36 +02:00
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer1.occupancy 768458163 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer2.occupancy 10591473 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer3.occupancy 47113721 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-30 11:16:36 +02:00
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
2013-03-01 19:20:30 +01:00
---------- End Simulation Statistics ----------
