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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

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Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
sim_seconds 1.905651 # Number of seconds simulated
sim_ticks 1905651402000 # Number of ticks simulated
final_tick 1905651402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_inst_rate 124387 # Simulator instruction rate (inst/s)
host_op_rate 124387 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4179760275 # Simulator tick rate (ticks/s)
host_mem_usage 352908 # Number of bytes of host memory used
host_seconds 455.92 # Real time elapsed on the host
sim_insts 56710998 # Number of instructions simulated
sim_ops 56710998 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytes_read::cpu0.inst 897600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24800576 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 78720 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 431296 # Number of bytes read from this memory
system.physmem.bytes_read::total 28857792 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 897600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 78720 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7816896 # Number of bytes written to this memory
system.physmem.bytes_written::total 7816896 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 14025 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 387509 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1230 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 6739 # Number of read requests responded to by this memory
system.physmem.num_reads::total 450903 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 122139 # Number of write requests responded to by this memory
system.physmem.num_writes::total 122139 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 471020 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 13014225 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1390391 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 41309 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 226325 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15143269 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 471020 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 41309 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 512329 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4101955 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4101955 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4101955 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 471020 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 13014225 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1390391 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 41309 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 226325 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19245224 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 450903 # Number of read requests accepted
system.physmem.writeReqs 122139 # Number of write requests accepted
system.physmem.readBursts 450903 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 122139 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28848704 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue
system.physmem.bytesWritten 7815360 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28857792 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7816896 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.neitherReadNorWriteReqs 4858 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 28020 # Per bank write bursts
system.physmem.perBankRdBursts::1 28240 # Per bank write bursts
system.physmem.perBankRdBursts::2 28746 # Per bank write bursts
system.physmem.perBankRdBursts::3 28309 # Per bank write bursts
system.physmem.perBankRdBursts::4 27973 # Per bank write bursts
system.physmem.perBankRdBursts::5 28180 # Per bank write bursts
system.physmem.perBankRdBursts::6 28116 # Per bank write bursts
system.physmem.perBankRdBursts::7 27456 # Per bank write bursts
system.physmem.perBankRdBursts::8 27700 # Per bank write bursts
system.physmem.perBankRdBursts::9 28070 # Per bank write bursts
system.physmem.perBankRdBursts::10 27744 # Per bank write bursts
system.physmem.perBankRdBursts::11 28151 # Per bank write bursts
system.physmem.perBankRdBursts::12 28476 # Per bank write bursts
system.physmem.perBankRdBursts::13 28764 # Per bank write bursts
system.physmem.perBankRdBursts::14 28477 # Per bank write bursts
system.physmem.perBankRdBursts::15 28339 # Per bank write bursts
system.physmem.perBankWrBursts::0 7807 # Per bank write bursts
system.physmem.perBankWrBursts::1 7750 # Per bank write bursts
system.physmem.perBankWrBursts::2 8222 # Per bank write bursts
system.physmem.perBankWrBursts::3 7743 # Per bank write bursts
system.physmem.perBankWrBursts::4 7390 # Per bank write bursts
system.physmem.perBankWrBursts::5 7636 # Per bank write bursts
system.physmem.perBankWrBursts::6 7609 # Per bank write bursts
system.physmem.perBankWrBursts::7 6913 # Per bank write bursts
system.physmem.perBankWrBursts::8 6944 # Per bank write bursts
system.physmem.perBankWrBursts::9 7275 # Per bank write bursts
system.physmem.perBankWrBursts::10 7157 # Per bank write bursts
system.physmem.perBankWrBursts::11 7547 # Per bank write bursts
system.physmem.perBankWrBursts::12 7916 # Per bank write bursts
system.physmem.perBankWrBursts::13 8234 # Per bank write bursts
system.physmem.perBankWrBursts::14 8082 # Per bank write bursts
system.physmem.perBankWrBursts::15 7890 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
system.physmem.totGap 1905651381000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.readPktSize::6 450903 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.writePktSize::6 122139 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 319686 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 41704 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 44614 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8998 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2006 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 4380 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 3959 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2562 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2247 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 2201 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 2095 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1635 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1944 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1926 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 2121 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1207 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 885 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 2413 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3733 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5369 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5553 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 6174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7038 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6311 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6522 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6544 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6265 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 950 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 934 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 906 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1002 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1094 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1000 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1239 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1407 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1623 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1831 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 2000 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1809 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1691 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1834 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 1598 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 810 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 31 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 66611 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 550.416718 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 337.147598 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 420.487836 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14710 22.08% 22.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11156 16.75% 38.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5022 7.54% 46.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2851 4.28% 50.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2435 3.66% 54.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1624 2.44% 56.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1521 2.28% 59.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1728 2.59% 61.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 25564 38.38% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 66611 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7169 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 62.875994 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2479.971838 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 7166 99.96% 99.96% # Reads before turning the bus around for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdPerTurnAround::total 7169 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7169 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.033756 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.809188 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 3.694603 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 5699 79.50% 79.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 43 0.60% 80.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 713 9.95% 90.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 256 3.57% 93.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 102 1.42% 95.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 22 0.31% 95.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 28 0.39% 95.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 86 1.20% 96.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 18 0.25% 97.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 42 0.59% 97.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 15 0.21% 97.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 21 0.29% 98.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 11 0.15% 98.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 10 0.14% 98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 3 0.04% 98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 26 0.36% 98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32 2 0.03% 99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35 2 0.03% 99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36 2 0.03% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37 1 0.01% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38 1 0.01% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39 4 0.06% 99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40 3 0.04% 99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::41 6 0.08% 99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43 1 0.01% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44 3 0.04% 99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::45 5 0.07% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::47 11 0.15% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48 5 0.07% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::49 4 0.06% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50 1 0.01% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::51 1 0.01% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::55 1 0.01% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56 7 0.10% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::57 11 0.15% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7169 # Writes before turning the bus around for reads
system.physmem.totQLat 8930594750 # Total ticks spent queuing
system.physmem.totMemAccLat 17382363500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2253805000 # Total ticks spent in databus transfers
system.physmem.avgQLat 19812.26 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.avgMemAccLat 38562.26 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.busUtil 0.15 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.90 # Average write queue length when enqueuing
system.physmem.readRowHits 407659 # Number of row buffer hits during reads
system.physmem.writeRowHits 98604 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes
system.physmem.avgGap 3325500.37 # Average gap between requests
system.physmem.pageHitRate 88.37 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 1804524317000 # Time in different power states
system.physmem.memoryStateTime::REF 63633700000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 37488657000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 19303809 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 296468 # Transaction distribution
system.membus.trans_dist::ReadResp 296393 # Transaction distribution
system.membus.trans_dist::WriteReq 13039 # Transaction distribution
system.membus.trans_dist::WriteResp 13039 # Transaction distribution
system.membus.trans_dist::Writeback 122139 # Transaction distribution
system.membus.trans_dist::UpgradeReq 9699 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 5540 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4861 # Transaction distribution
system.membus.trans_dist::ReadExReq 162690 # Transaction distribution
system.membus.trans_dist::ReadExResp 162297 # Transaction distribution
system.membus.trans_dist::BadAddressError 75 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40466 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920381 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 960997 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1085644 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73690 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31367808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 31441498 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 36748378 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 36748378 # Total data (bytes)
system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 37884500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer1.occupancy 1609423248 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer2.occupancy 94500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.respLayer1.occupancy 3824980631 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.respLayer2.occupancy 376652994 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.l2c.tags.replacements 343977 # number of replacements
system.l2c.tags.tagsinuse 65252.773158 # Cycle average of tags in use
system.l2c.tags.total_refs 2582565 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 408968 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 6.314834 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 7103141750 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 53523.190376 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5304.878115 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6147.677864 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 207.477812 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 69.548991 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.816699 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.080946 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.093806 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.003166 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.001061 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995678 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 64991 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 3387 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 4556 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4338 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 52483 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.991684 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 27108862 # Number of tag accesses
system.l2c.tags.data_accesses 27108862 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst 867616 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 736617 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 210128 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 67910 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1882271 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 822208 # number of Writeback hits
system.l2c.Writeback_hits::total 822208 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 261 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 430 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 154436 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 25581 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 180017 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 867616 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 891053 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 210128 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 93491 # number of demand (read+write) hits
system.l2c.demand_hits::total 2062288 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 867616 # number of overall hits
system.l2c.overall_hits::cpu0.data 891053 # number of overall hits
system.l2c.overall_hits::cpu1.inst 210128 # number of overall hits
system.l2c.overall_hits::cpu1.data 93491 # number of overall hits
system.l2c.overall_hits::total 2062288 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 14035 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 273392 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 1238 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 452 # number of ReadReq misses
system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2673 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1056 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 3729 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 406 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 434 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 840 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 114695 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 6342 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 121037 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 14035 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 388087 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 1238 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 6794 # number of demand (read+write) misses
system.l2c.demand_misses::total 410154 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 14035 # number of overall misses
system.l2c.overall_misses::cpu0.data 388087 # number of overall misses
system.l2c.overall_misses::cpu1.inst 1238 # number of overall misses
system.l2c.overall_misses::cpu1.data 6794 # number of overall misses
system.l2c.overall_misses::total 410154 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 1067454245 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 17881620237 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 96862500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 35356999 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 19081293981 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 964468 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 4567794 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 5532262 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 972461 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114995 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 1087456 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 9393947733 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 639497214 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10033444947 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1067454245 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 27275567970 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 96862500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 674854213 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 29114738928 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1067454245 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 27275567970 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 96862500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 674854213 # number of overall miss cycles
system.l2c.overall_miss_latency::total 29114738928 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 881651 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 1010009 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 211366 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 68362 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2171388 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 822208 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 822208 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2842 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1317 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 4159 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 455 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.l2c.SCUpgradeReq_accesses::cpu1.data 458 # number of SCUpgradeReq accesses(hits+misses)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.l2c.SCUpgradeReq_accesses::total 913 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 269131 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 31923 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 301054 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 881651 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1279140 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 211366 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 100285 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2472442 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 881651 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1279140 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 211366 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 100285 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2472442 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015919 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.270683 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.005857 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.006612 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.133148 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940535 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.801822 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.896610 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.892308 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947598 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.920044 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.426168 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.198666 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.402044 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.015919 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.303397 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005857 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.067747 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.165890 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.015919 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.303397 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005857 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.067747 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.165890 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76056.590310 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 65406.523369 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78241.114701 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 78223.449115 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 65998.519565 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 360.818556 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4325.562500 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 1483.577903 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2395.224138 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 264.965438 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 1294.590476 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81903.724949 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100835.259224 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 82895.684353 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 70984.895742 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 70984.895742 # average overall miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.l2c.writebacks::writebacks 80619 # number of writebacks
system.l2c.writebacks::total 80619 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst 14026 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 273392 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 1230 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 451 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 289099 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2673 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1056 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 3729 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 406 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 434 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 840 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 114695 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 6342 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 121037 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 14026 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 388087 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 1230 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 6793 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 410136 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 14026 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 388087 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 1230 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 6793 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 410136 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 890067005 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14473617763 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 80840000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 29712501 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 15474237269 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26950129 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10569046 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 37519175 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4153902 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4341434 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 8495336 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7989750261 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 560973786 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8550724047 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 890067005 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 22463368024 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 80840000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 590686287 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 24024961316 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 890067005 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 22463368024 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 80840000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 590686287 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 24024961316 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367392500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22035500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1389428000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2022747000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 583651500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2606398500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3390139500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 605687000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 3995826500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.270683 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006597 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.133140 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940535 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.801822 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.896610 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.892308 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.947598 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.920044 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.426168 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198666 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.402044 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.165883 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.165883 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52940.897184 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65881.376940 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 53525.737789 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.352787 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.566288 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.457495 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10231.285714 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.304147 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10113.495238 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69660.841894 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 88453.766320 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 70645.538530 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.tags.replacements 41695 # number of replacements
system.iocache.tags.tagsinuse 0.491978 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.tags.warmup_cycle 1712295759000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 0.491978 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.030749 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.030749 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375543 # Number of tag accesses
system.iocache.tags.data_accesses 375543 # Number of data accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
system.iocache.overall_misses::total 41727 # number of overall misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.ReadReq_miss_latency::tsunami.ide 21492883 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21492883 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 12499299192 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 12499299192 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 12520792075 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 12520792075 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 12520792075 # number of overall miss cycles
system.iocache.overall_miss_latency::total 12520792075 # number of overall miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122816.474286 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122816.474286 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 300811.012514 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 300811.012514 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 300064.516380 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 300064.516380 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 367481 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.blocked::no_mshrs 28552 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 12.870587 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12390883 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12390883 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10336377204 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 10336377204 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 10348768087 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 10348768087 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 10348768087 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 10348768087 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.branchPred.lookups 12477942 # Number of BP lookups
system.cpu0.branchPred.condPredicted 10513633 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 331474 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 8127728 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 5283638 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.branchPred.BTBHitPct 65.007564 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 797741 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 28790 # Number of incorrect RAS predictions.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.dtb.read_hits 8879185 # DTB read hits
system.cpu0.dtb.read_misses 30734 # DTB read misses
system.cpu0.dtb.read_acv 556 # DTB read access violations
system.cpu0.dtb.read_accesses 627584 # DTB read accesses
system.cpu0.dtb.write_hits 5815647 # DTB write hits
system.cpu0.dtb.write_misses 8173 # DTB write misses
system.cpu0.dtb.write_acv 357 # DTB write access violations
system.cpu0.dtb.write_accesses 210225 # DTB write accesses
system.cpu0.dtb.data_hits 14694832 # DTB hits
system.cpu0.dtb.data_misses 38907 # DTB misses
system.cpu0.dtb.data_acv 913 # DTB access violations
system.cpu0.dtb.data_accesses 837809 # DTB accesses
system.cpu0.itb.fetch_hits 998260 # ITB hits
system.cpu0.itb.fetch_misses 27519 # ITB misses
system.cpu0.itb.fetch_acv 894 # ITB acv
system.cpu0.itb.fetch_accesses 1025779 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.numCycles 116074371 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.fetch.icacheStallCycles 25123779 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 63882467 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 12477942 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 6081379 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 12010156 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1699076 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 37307525 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 31946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 195411 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 352959 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 7722540 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 223615 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 76113904 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.839301 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.177052 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.fetch.rateDist::0 64103748 84.22% 84.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 767865 1.01% 85.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1567652 2.06% 87.29% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 704812 0.93% 88.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 2586726 3.40% 91.61% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 521075 0.68% 92.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 575522 0.76% 93.05% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 832581 1.09% 94.15% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4453923 5.85% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.fetch.rateDist::total 76113904 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.107500 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.550358 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 26378411 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 36826325 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 10921760 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 930988 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1056419 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 512680 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 35852 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 62713959 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 107463 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1056419 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 27400432 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 14971568 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 18343259 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 10229394 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 4112830 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 59339079 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 7155 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 639099 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 1437135 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 39727133 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 72236857 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 72098194 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 129082 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 34929896 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 4797229 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1458801 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 212309 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 11241570 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 9288070 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 6084553 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1139915 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 737819 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 52640864 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1816659 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 51478960 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 92665 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 5869250 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 3045578 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 1230018 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 76113904 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.676341 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.327493 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iq.issued_per_cycle::0 53257398 69.97% 69.97% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 10376788 13.63% 83.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 4704231 6.18% 89.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 3091331 4.06% 93.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2445214 3.21% 97.06% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1217468 1.60% 98.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 651050 0.86% 99.51% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 318171 0.42% 99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 52253 0.07% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iq.issued_per_cycle::total 76113904 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iq.fu_full::IntAlu 82049 12.02% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.02% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 319124 46.77% 58.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 281213 41.21% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 35464091 68.89% 68.90% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 56550 0.11% 69.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 15746 0.03% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.04% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 9235082 17.94% 86.98% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5882526 11.43% 98.41% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 819301 1.59% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iq.FU_type_0::total 51478960 # Type of FU issued
system.cpu0.iq.rate 0.443500 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 682386 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.013256 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 179291609 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 60070073 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 50439032 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 555265 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 269219 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 261959 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 51867113 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 290448 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 544569 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 1116578 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3845 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 12782 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 445374 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 18457 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 142389 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iew.iewSquashCycles 1056419 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 10732956 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 797506 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 57687159 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 618379 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 9288070 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6084553 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 1600267 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 582946 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 5458 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 12782 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 164537 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 351989 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 516526 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 51092894 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 8933351 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 386065 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iew.exec_nop 3229636 # number of nop insts executed
system.cpu0.iew.exec_refs 14770817 # number of memory reference insts executed
system.cpu0.iew.exec_branches 8136394 # Number of branches executed
system.cpu0.iew.exec_stores 5837466 # Number of stores executed
system.cpu0.iew.exec_rate 0.440174 # Inst execution rate
system.cpu0.iew.wb_sent 50791046 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 50700991 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 25278333 # num instructions producing a value
system.cpu0.iew.wb_consumers 34060542 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.iew.wb_rate 0.436797 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.742159 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.commit.commitSquashedInsts 6334928 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 586641 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 480870 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 75057485 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.682787 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.597640 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.commit.committed_per_cycle::0 55774455 74.31% 74.31% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 8026658 10.69% 85.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 4417430 5.89% 90.89% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2392691 3.19% 94.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1323184 1.76% 95.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 562724 0.75% 96.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 473653 0.63% 97.22% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 433129 0.58% 97.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1653561 2.20% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.commit.committed_per_cycle::total 75057485 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 51248256 # Number of instructions committed
system.cpu0.commit.committedOps 51248256 # Number of ops (including micro ops) committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.commit.refs 13810671 # Number of memory references committed
system.cpu0.commit.loads 8171492 # Number of loads committed
system.cpu0.commit.membars 199624 # Number of memory barriers committed
system.cpu0.commit.branches 7741114 # Number of branches committed
system.cpu0.commit.fp_insts 259898 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 47457125 # Number of committed integer instructions.
system.cpu0.commit.function_calls 657479 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 2951389 5.76% 5.76% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 33388118 65.15% 70.91% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 55525 0.11% 71.02% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.02% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 15746 0.03% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 1879 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.05% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 8371116 16.33% 87.39% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 5645183 11.02% 98.40% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 819300 1.60% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 51248256 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1653561 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.rob.rob_reads 130790454 # The number of ROB reads
system.cpu0.rob.rob_writes 116222813 # The number of ROB writes
system.cpu0.timesIdled 1101169 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 39960467 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 3695221845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 48300626 # Number of Instructions Simulated
system.cpu0.committedOps 48300626 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 48300626 # Number of Instructions Simulated
system.cpu0.cpi 2.403165 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.403165 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.416118 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.416118 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 67219449 # number of integer regfile reads
system.cpu0.int_regfile_writes 36695614 # number of integer regfile writes
system.cpu0.fp_regfile_reads 128632 # number of floating regfile reads
system.cpu0.fp_regfile_writes 130173 # number of floating regfile writes
system.cpu0.misc_regfile_reads 1801385 # number of misc regfile reads
system.cpu0.misc_regfile_writes 820377 # number of misc regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.toL2Bus.throughput 111416521 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2199115 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2199023 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 13039 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 13039 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 822208 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 9837 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 5613 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 15450 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 343877 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 302328 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1763397 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369225 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 422759 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 294489 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5849870 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56425664 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130205428 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13527424 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10778278 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 210936794 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 210926490 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 1394560 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4971595549 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.toL2Bus.respLayer0.occupancy 3972568555 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.toL2Bus.respLayer1.occupancy 5889953047 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.toL2Bus.respLayer2.occupancy 951834487 # Layer occupancy (ticks)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.toL2Bus.respLayer3.occupancy 507907991 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 1435370 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7369 # Transaction distribution
system.iobus.trans_dist::ReadResp 7369 # Transaction distribution
system.iobus.trans_dist::WriteReq 54591 # Transaction distribution
system.iobus.trans_dist::WriteResp 54591 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11870 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.pkt_count_system.bridge.master::total 40466 # Packet count per connected master and slave (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.pkt_count::total 123920 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47480 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.tot_pkt_size_system.bridge.master::total 73690 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.tot_pkt_size::total 2735314 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2735314 # Total data (bytes)
system.iobus.reqLayer0.occupancy 11225000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.reqLayer29.occupancy 380163081 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.respLayer0.occupancy 27427000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.respLayer1.occupancy 43193006 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.icache.tags.replacements 881127 # number of replacements
system.cpu0.icache.tags.tagsinuse 509.683312 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 6795719 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 881636 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 7.708078 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 26872936250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.683312 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995475 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.995475 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 8604286 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 8604286 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 6795719 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 6795719 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 6795719 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 6795719 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 6795719 # number of overall hits
system.cpu0.icache.overall_hits::total 6795719 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 926821 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 926821 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 926821 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 926821 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 926821 # number of overall misses
system.cpu0.icache.overall_misses::total 926821 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13137729759 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 13137729759 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 13137729759 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 13137729759 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 13137729759 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 13137729759 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 7722540 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 7722540 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 7722540 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 7722540 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 7722540 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 7722540 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120015 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.120015 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120015 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.120015 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120015 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.120015 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14175.045407 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14175.045407 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 3568 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 70 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.629139 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45075 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 45075 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 45075 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 45075 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 45075 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 45075 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 881746 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 881746 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 881746 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 881746 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 881746 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 881746 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814665187 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814665187 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814665187 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10814665187 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814665187 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10814665187 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114178 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.114178 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.114178 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.dcache.tags.replacements 1281204 # number of replacements
system.cpu0.dcache.tags.tagsinuse 505.636705 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 10489009 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1281716 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 8.183567 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 26139000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.636705 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987572 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.987572 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.dcache.tags.tag_accesses 56677841 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 56677841 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6448265 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6448265 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3678309 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3678309 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 163487 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 163487 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188240 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 188240 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10126574 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 10126574 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10126574 # number of overall hits
system.cpu0.dcache.overall_hits::total 10126574 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1590441 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1590441 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1755180 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1755180 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20486 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 20486 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2716 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 2716 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 3345621 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 3345621 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3345621 # number of overall misses
system.cpu0.dcache.overall_misses::total 3345621 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40624107085 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 40624107085 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78713383276 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 78713383276 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 300049994 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 300049994 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20153405 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 20153405 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 119337490361 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 119337490361 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8038706 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8038706 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5433489 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5433489 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183973 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 183973 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190956 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 190956 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 13472195 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 13472195 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 13472195 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 13472195 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197848 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.197848 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323030 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.323030 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111353 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111353 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014223 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014223 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248335 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.248335 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248335 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.248335 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7420.252209 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7420.252209 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 35669.757681 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 35669.757681 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 2966485 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 566 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 48680 # number of cycles access was blocked
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.938476 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 80.857143 # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.dcache.writebacks::writebacks 754427 # number of writebacks
system.cpu0.dcache.writebacks::total 754427 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 586151 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 586151 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1480465 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1480465 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4562 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4562 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 2066616 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 2066616 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 2066616 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 2066616 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1004290 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 1004290 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274715 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 274715 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15924 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15924 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2716 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2716 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1279005 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1279005 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1279005 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1279005 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27273016452 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27273016452 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11562486348 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11562486348 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175781505 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175781505 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14720595 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14720595 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38835502800 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 38835502800 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38835502800 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 38835502800 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459363000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459363000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2145424499 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2145424499 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3604787499 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3604787499 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124932 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124932 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050560 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050560 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086556 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086556 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014223 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014223 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.094937 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.094937 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5419.953976 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5419.953976 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.branchPred.lookups 2485884 # Number of BP lookups
system.cpu1.branchPred.condPredicted 2055798 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 72106 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 1444173 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 831190 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.branchPred.BTBHitPct 57.554739 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 170291 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 7410 # Number of incorrect RAS predictions.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.dtb.read_hits 1846757 # DTB read hits
system.cpu1.dtb.read_misses 10485 # DTB read misses
system.cpu1.dtb.read_acv 25 # DTB read access violations
system.cpu1.dtb.read_accesses 320297 # DTB read accesses
system.cpu1.dtb.write_hits 1188866 # DTB write hits
system.cpu1.dtb.write_misses 1998 # DTB write misses
system.cpu1.dtb.write_acv 67 # DTB write access violations
system.cpu1.dtb.write_accesses 130212 # DTB write accesses
system.cpu1.dtb.data_hits 3035623 # DTB hits
system.cpu1.dtb.data_misses 12483 # DTB misses
system.cpu1.dtb.data_acv 92 # DTB access violations
system.cpu1.dtb.data_accesses 450509 # DTB accesses
system.cpu1.itb.fetch_hits 420713 # ITB hits
system.cpu1.itb.fetch_misses 6600 # ITB misses
system.cpu1.itb.fetch_acv 223 # ITB acv
system.cpu1.itb.fetch_accesses 427313 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.numCycles 14964653 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.fetch.icacheStallCycles 5680448 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 11756636 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 2485884 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 1001481 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 2105616 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 381271 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 5937724 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 62153 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 48156 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 1420733 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 48517 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 14103634 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.833589 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.209447 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.fetch.rateDist::0 11998018 85.07% 85.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 134082 0.95% 86.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 225201 1.60% 87.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 169062 1.20% 88.82% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 292225 2.07% 90.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 115066 0.82% 91.70% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 124219 0.88% 92.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 190666 1.35% 93.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 855095 6.06% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.fetch.rateDist::total 14103634 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.166117 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.785627 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 5621005 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 6169812 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 1969307 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 106628 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 236881 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 108171 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 6940 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 11535490 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 20476 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 236881 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 5819966 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 414819 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 5141752 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 1873919 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 616295 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 10688130 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 72 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 55241 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 150444 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 7038513 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 12788456 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 12730882 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 51827 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 5999158 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1039355 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 430985 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 39680 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 1897434 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 1953635 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 1261748 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 176061 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 98445 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 9382355 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 465021 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 9121330 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 28823 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 1378008 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 697882 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 334259 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 14103634 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.646736 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.322598 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iq.issued_per_cycle::0 10102268 71.63% 71.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 1834449 13.01% 84.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 778460 5.52% 90.16% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 526095 3.73% 93.89% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 451675 3.20% 97.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 203961 1.45% 98.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 130101 0.92% 99.46% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 68435 0.49% 99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 8190 0.06% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iq.issued_per_cycle::total 14103634 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iq.fu_full::IntAlu 3122 1.64% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.64% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 102805 54.10% 55.74% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 84113 44.26% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 5686452 62.34% 62.38% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 15839 0.17% 62.55% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.55% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 10725 0.12% 62.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 1931464 21.18% 83.87% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 1211908 13.29% 97.15% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 259653 2.85% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iq.FU_type_0::total 9121330 # Type of FU issued
system.cpu1.iq.rate 0.609525 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 190040 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.020835 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 32366807 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 11130082 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 8856102 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 198350 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 96900 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 93876 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 9204439 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 103405 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 88797 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 277499 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 1209 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 1676 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 126244 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 334 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 13648 # Number of times an access to memory failed due to the cache being blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iew.iewSquashCycles 236881 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 252351 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 39276 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 10330457 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 142523 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 1953635 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 1261748 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 421576 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 32385 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 1813 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 1676 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 32559 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 96048 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 128607 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 9031900 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 1864128 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 89430 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iew.exec_nop 483081 # number of nop insts executed
system.cpu1.iew.exec_refs 3060773 # number of memory reference insts executed
system.cpu1.iew.exec_branches 1345265 # Number of branches executed
system.cpu1.iew.exec_stores 1196645 # Number of stores executed
system.cpu1.iew.exec_rate 0.603549 # Inst execution rate
system.cpu1.iew.wb_sent 8976284 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 8949978 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 4203498 # num instructions producing a value
system.cpu1.iew.wb_consumers 5915948 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.iew.wb_rate 0.598075 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.710537 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.commit.commitSquashedInsts 1403439 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 130762 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 120016 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 13866753 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.637072 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.578145 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.commit.committed_per_cycle::0 10553407 76.11% 76.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 1550482 11.18% 87.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 573583 4.14% 91.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 351937 2.54% 93.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 252477 1.82% 95.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 99182 0.72% 96.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 104002 0.75% 97.25% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 102635 0.74% 97.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 279048 2.01% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.commit.committed_per_cycle::total 13866753 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 8834118 # Number of instructions committed
system.cpu1.commit.committedOps 8834118 # Number of ops (including micro ops) committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.commit.refs 2811640 # Number of memory references committed
system.cpu1.commit.loads 1676136 # Number of loads committed
system.cpu1.commit.membars 41495 # Number of memory barriers committed
system.cpu1.commit.branches 1262292 # Number of branches committed
system.cpu1.commit.fp_insts 92546 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 8189363 # Number of committed integer instructions.
system.cpu1.commit.function_calls 139415 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 427272 4.84% 4.84% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 5265448 59.60% 64.44% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 15610 0.18% 64.62% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.62% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 10725 0.12% 64.74% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 1763 0.02% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 1717631 19.44% 84.20% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 1136016 12.86% 97.06% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 259653 2.94% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 8834118 # Class of committed instruction
system.cpu1.commit.bw_lim_events 279048 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.rob.rob_reads 23736453 # The number of ROB reads
system.cpu1.rob.rob_writes 20710450 # The number of ROB writes
system.cpu1.timesIdled 126022 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 861019 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3795679739 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 8410372 # Number of Instructions Simulated
system.cpu1.committedOps 8410372 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 8410372 # Number of Instructions Simulated
system.cpu1.cpi 1.779309 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.779309 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.562016 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.562016 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 11653751 # number of integer regfile reads
system.cpu1.int_regfile_writes 6367365 # number of integer regfile writes
system.cpu1.fp_regfile_reads 51509 # number of floating regfile reads
system.cpu1.fp_regfile_writes 51143 # number of floating regfile writes
system.cpu1.misc_regfile_reads 926936 # number of misc regfile reads
system.cpu1.misc_regfile_writes 206554 # number of misc regfile writes
system.cpu1.icache.tags.replacements 210820 # number of replacements
system.cpu1.icache.tags.tagsinuse 470.468430 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 1201520 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 211332 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 5.685462 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 1879665276250 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.468430 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918884 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.918884 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.icache.tags.tag_accesses 1632124 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 1632124 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 1201520 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1201520 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 1201520 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 1201520 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 1201520 # number of overall hits
system.cpu1.icache.overall_hits::total 1201520 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 219211 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 219211 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 219211 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 219211 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 219211 # number of overall misses
system.cpu1.icache.overall_misses::total 219211 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2949137410 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 2949137410 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 2949137410 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 2949137410 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 2949137410 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 2949137410 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 1420731 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 1420731 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 1420731 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 1420731 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 1420731 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 1420731 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154295 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.154295 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154295 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.154295 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154295 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.154295 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.418898 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.418898 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13453.418898 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13453.418898 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.380952 # average number of cycles each access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7818 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 7818 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 7818 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 7818 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 7818 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 7818 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211393 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 211393 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 211393 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 211393 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 211393 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 211393 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2447786762 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 2447786762 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2447786762 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 2447786762 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2447786762 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 2447786762 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148792 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.148792 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.148792 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.dcache.tags.replacements 102235 # number of replacements
system.cpu1.dcache.tags.tagsinuse 491.253867 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 2477501 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 102637 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 24.138478 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 45814117000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.253867 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959480 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.959480 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 11642464 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 11642464 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 1521331 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 1521331 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 890954 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 890954 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30283 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 30283 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29173 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 29173 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 2412285 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 2412285 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 2412285 # number of overall hits
system.cpu1.dcache.overall_hits::total 2412285 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 196472 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 196472 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 206616 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 206616 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5011 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 5011 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2898 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 2898 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 403088 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 403088 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 403088 # number of overall misses
system.cpu1.dcache.overall_misses::total 403088 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2745758970 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 2745758970 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6806020354 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 6806020354 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50048997 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 50048997 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21170434 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 21170434 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 9551779324 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 9551779324 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 9551779324 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 9551779324 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 1717803 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 1717803 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1097570 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1097570 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 35294 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 35294 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32071 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 32071 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 2815373 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 2815373 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 2815373 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 2815373 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114374 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.114374 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188249 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.188249 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.141979 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.141979 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090362 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090362 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143174 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.143174 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143174 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.143174 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13975.319486 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13975.319486 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32940.432270 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 32940.432270 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9987.826182 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9987.826182 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7305.187716 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7305.187716 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 23696.511243 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 23696.511243 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 206242 # number of cycles access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.dcache.blocked::no_mshrs 3728 # number of cycles access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 55.322425 # average number of cycles each access was blocked
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.dcache.writebacks::writebacks 67781 # number of writebacks
system.cpu1.dcache.writebacks::total 67781 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 121809 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 121809 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 169922 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 169922 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 539 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 539 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 291731 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 291731 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 291731 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 291731 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 74663 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 74663 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36694 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 36694 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4472 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4472 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2897 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 2897 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 111357 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 111357 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 111357 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 111357 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 836811454 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 836811454 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 998585721 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 998585721 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34130252 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34130252 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15375566 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15375566 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1835397175 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 1835397175 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1835397175 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 1835397175 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23621500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23621500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 617644004 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 617644004 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641265504 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641265504 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043464 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043464 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033432 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033432 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.126707 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.126707 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090331 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090331 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.039553 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.039553 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7631.988372 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7631.988372 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5307.409734 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5307.409734 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.kern.inst.quiesce 6589 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 184914 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 65370 40.53% 40.53% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1926 1.19% 41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 186 0.12% 41.92% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 93691 58.08% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 161304 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 64362 49.21% 49.21% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1926 1.47% 50.79% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 64176 49.07% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 130781 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1863832959500 97.81% 97.81% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 63684000 0.00% 97.81% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 569763500 0.03% 97.84% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 89287000 0.00% 97.84% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 41094897500 2.16% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1905650591500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.984580 # fraction of swpipl calls that actually changed the ipl
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.kern.ipl_used::31 0.684975 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.810773 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed
system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed
system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed
system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed
system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed
system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed
system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed
system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed
system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed
system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed
system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed
system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed
system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed
system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed
system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed
system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 211 # number of syscalls executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.kern.callpal::wripir 277 0.16% 0.16% # number of callpals executed
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3529 2.08% 2.24% # number of callpals executed
system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed
system.cpu0.kern.callpal::swpipl 154533 90.92% 93.20% # number of callpals executed
system.cpu0.kern.callpal::rdps 6537 3.85% 97.04% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed
system.cpu0.kern.callpal::wrusp 4 0.00% 97.05% # number of callpals executed
system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed
system.cpu0.kern.callpal::rti 4527 2.66% 99.72% # number of callpals executed
system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed
system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 169959 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 7072 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.kern.mode_good::kernel 1286
system.cpu0.kern.mode_good::user 1287
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_good::idle 0
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.kern.mode_switch_good::kernel 0.181844 # fraction of useful protection mode switches
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.kern.mode_switch_good::total 0.307812 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1903707301000 99.90% 99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 1943282500 0.10% 100.00% # number of ticks spent at the given mode
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.kern.swap_context 3530 # number of times the context was actually changed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.kern.inst.quiesce 2439 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 54740 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 16948 36.40% 36.40% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1925 4.13% 40.53% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 277 0.59% 41.13% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 27412 58.87% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 46562 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 16579 47.26% 47.26% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1925 5.49% 52.74% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 277 0.79% 53.53% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 16302 46.47% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 35083 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1874130150000 98.36% 98.36% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 532183000 0.03% 98.39% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 125676500 0.01% 98.40% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 30535391000 1.60% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1905323400500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.978228 # fraction of swpipl calls that actually changed the ipl
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.kern.ipl_used::31 0.594703 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.753468 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed
system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed
system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed
system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed
system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed
system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed
system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed
system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed
system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed
system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed
system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed
system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed
system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed
system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed
system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed
system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed
system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed
system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 115 # number of syscalls executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.kern.callpal::wripir 186 0.39% 0.39% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.39% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed
system.cpu1.kern.callpal::swpctx 1067 2.22% 2.61% # number of callpals executed
system.cpu1.kern.callpal::tbi 6 0.01% 2.63% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 2.64% # number of callpals executed
system.cpu1.kern.callpal::swpipl 41329 85.97% 88.61% # number of callpals executed
system.cpu1.kern.callpal::rdps 2224 4.63% 93.23% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 93.23% # number of callpals executed
system.cpu1.kern.callpal::wrusp 3 0.01% 93.24% # number of callpals executed
system.cpu1.kern.callpal::rdusp 1 0.00% 93.24% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.01% 93.25% # number of callpals executed
system.cpu1.kern.callpal::rti 3030 6.30% 99.55% # number of callpals executed
system.cpu1.kern.callpal::callsys 172 0.36% 99.91% # number of callpals executed
system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.kern.callpal::total 48076 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 1341 # number of protection mode switches
system.cpu1.kern.mode_switch::user 460 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2398 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 662
system.cpu1.kern.mode_good::user 460
system.cpu1.kern.mode_good::idle 202
system.cpu1.kern.mode_switch_good::kernel 0.493661 # fraction of useful protection mode switches
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.kern.mode_switch_good::idle 0.084237 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.315313 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 4271038500 0.22% 0.22% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 809340000 0.04% 0.27% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1900232555000 99.73% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1068 # number of times the context was actually changed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink