2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
2015-09-25 13:27:03 +02:00
sim_seconds 0.058181 # Number of seconds simulated
sim_ticks 58181475500 # Number of ticks simulated
final_tick 58181475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-09-25 13:27:03 +02:00
host_inst_rate 122946 # Simulator instruction rate (inst/s)
host_op_rate 123559 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 78962453 # Simulator tick rate (ticks/s)
host_mem_usage 448784 # Number of bytes of host memory used
host_seconds 736.82 # Real time elapsed on the host
2015-04-30 21:17:43 +02:00
sim_insts 90589799 # Number of instructions simulated
sim_ops 91041030 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 50176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 933312 # Number of bytes read from this memory
system.physmem.bytes_read::total 1027904 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 28672 # Number of bytes written to this memory
system.physmem.bytes_written::total 28672 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 784 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 14583 # Number of read requests responded to by this memory
system.physmem.num_reads::total 16061 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 448 # Number of write requests responded to by this memory
system.physmem.num_writes::total 448 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 763404 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 862405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 16041394 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 17667204 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 763404 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 763404 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 492803 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 492803 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 492803 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 763404 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 862405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 16041394 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18160007 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 16061 # Number of read requests accepted
system.physmem.writeReqs 448 # Number of write requests accepted
system.physmem.readBursts 16061 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 448 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 1014144 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 13760 # Total number of bytes read from write queue
system.physmem.bytesWritten 26688 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 1027904 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 28672 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 215 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one
2015-07-03 16:15:03 +02:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2015-09-25 13:27:03 +02:00
system.physmem.perBankRdBursts::0 1015 # Per bank write bursts
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::1 876 # Per bank write bursts
2015-09-25 13:27:03 +02:00
system.physmem.perBankRdBursts::2 960 # Per bank write bursts
system.physmem.perBankRdBursts::3 1024 # Per bank write bursts
system.physmem.perBankRdBursts::4 1064 # Per bank write bursts
system.physmem.perBankRdBursts::5 1138 # Per bank write bursts
system.physmem.perBankRdBursts::6 1126 # Per bank write bursts
system.physmem.perBankRdBursts::7 1116 # Per bank write bursts
system.physmem.perBankRdBursts::8 1048 # Per bank write bursts
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::9 962 # Per bank write bursts
2015-09-25 13:27:03 +02:00
system.physmem.perBankRdBursts::10 947 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
system.physmem.perBankRdBursts::12 909 # Per bank write bursts
system.physmem.perBankRdBursts::13 891 # Per bank write bursts
system.physmem.perBankRdBursts::14 939 # Per bank write bursts
system.physmem.perBankRdBursts::15 932 # Per bank write bursts
system.physmem.perBankWrBursts::0 39 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
2015-09-25 13:27:03 +02:00
system.physmem.perBankWrBursts::2 11 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 10 # Per bank write bursts
system.physmem.perBankWrBursts::5 33 # Per bank write bursts
system.physmem.perBankWrBursts::6 78 # Per bank write bursts
system.physmem.perBankWrBursts::7 51 # Per bank write bursts
system.physmem.perBankWrBursts::8 44 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
2015-09-25 13:27:03 +02:00
system.physmem.perBankWrBursts::10 13 # Per bank write bursts
system.physmem.perBankWrBursts::11 2 # Per bank write bursts
system.physmem.perBankWrBursts::12 8 # Per bank write bursts
system.physmem.perBankWrBursts::13 25 # Per bank write bursts
system.physmem.perBankWrBursts::14 64 # Per bank write bursts
system.physmem.perBankWrBursts::15 39 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2015-09-25 13:27:03 +02:00
system.physmem.totGap 58181318500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::6 16061 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.writePktSize::6 448 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 10962 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::1 2513 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::3 396 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::4 299 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::5 294 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::7 275 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 295 # What read queue length does an incoming req see
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::15 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 24 # What write queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.wrQLenPdf::17 24 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::18 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 23 # What write queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see
2015-07-30 09:42:27 +02:00
system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 23 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.bytesPerActivate::samples 1956 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 531.533742 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 297.285521 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 435.040107 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 621 31.75% 31.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 232 11.86% 43.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 86 4.40% 48.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 69 3.53% 51.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 49 2.51% 54.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 52 2.66% 56.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 53 2.71% 59.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 46 2.35% 61.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 748 38.24% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1956 # Bytes accessed per row activation
2015-07-30 09:42:27 +02:00
system.physmem.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes
2015-09-25 13:27:03 +02:00
system.physmem.rdPerTurnAround::mean 686.869565 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 31.250235 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 3138.483903 # Reads before turning the bus around for writes
2015-07-30 09:42:27 +02:00
system.physmem.rdPerTurnAround::0-511 22 95.65% 95.65% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359 1 4.35% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 23 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads
2015-09-25 13:27:03 +02:00
system.physmem.wrPerTurnAround::mean 18.130435 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.125203 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.457697 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 21 91.30% 91.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 1 4.35% 95.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 1 4.35% 100.00% # Writes before turning the bus around for reads
2015-07-30 09:42:27 +02:00
system.physmem.wrPerTurnAround::total 23 # Writes before turning the bus around for reads
2015-09-25 13:27:03 +02:00
system.physmem.totQLat 162337192 # Total ticks spent queuing
system.physmem.totMemAccLat 459449692 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 79230000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10244.68 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgMemAccLat 28994.68 # Average memory access latency per DRAM burst
2015-07-30 09:42:27 +02:00
system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.avgWrBW 0.46 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 17.67 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.49 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2014-12-23 15:31:20 +01:00
system.physmem.busUtil 0.14 # Data bus utilization in percentage
system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2015-09-25 13:27:03 +02:00
system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing
system.physmem.avgWrQLen 20.72 # Average write queue length when enqueuing
system.physmem.readRowHits 14167 # Number of row buffer hits during reads
system.physmem.writeRowHits 131 # Number of row buffer hits during writes
2015-07-30 09:42:27 +02:00
system.physmem.readRowHitRate 89.40 # Row buffer hit rate for reads
2015-09-25 13:27:03 +02:00
system.physmem.writeRowHitRate 29.57 # Row buffer hit rate for writes
system.physmem.avgGap 3524218.21 # Average gap between requests
system.physmem.pageHitRate 87.78 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 7983360 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 4356000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 64662000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 1438560 # Energy for write commands per rank (pJ)
2015-07-30 09:42:27 +02:00
system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ)
2015-09-25 13:27:03 +02:00
system.physmem_0.actBackEnergy 2503358775 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 32711543250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 39093302265 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.947294 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 54407827569 # Time in different power states
2015-07-30 09:42:27 +02:00
system.physmem_0.memoryStateTime::REF 1942720000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.physmem_0.memoryStateTime::ACT 1828586181 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.physmem_1.actEnergy 6788880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3704250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 58663800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 1263600 # Energy for write commands per rank (pJ)
2015-07-30 09:42:27 +02:00
system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ)
2015-09-25 13:27:03 +02:00
system.physmem_1.actBackEnergy 2462347845 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 32747517750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 39080246445 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.722887 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 54468275483 # Time in different power states
2015-07-30 09:42:27 +02:00
system.physmem_1.memoryStateTime::REF 1942720000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.physmem_1.memoryStateTime::ACT 1768727017 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.cpu.branchPred.lookups 28257355 # Number of BP lookups
system.cpu.branchPred.condPredicted 23279453 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 837859 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 11842476 # Number of BTB lookups
system.cpu.branchPred.BTBHits 11784812 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-09-25 13:27:03 +02:00
system.cpu.branchPred.BTBHitPct 99.513075 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 75760 # Number of times the RAS was used to get a target.
2015-07-03 16:15:03 +02:00
system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
2015-09-25 13:27:03 +02:00
system.cpu.numCycles 116362952 # number of cpu cycles simulated
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-25 13:27:03 +02:00
system.cpu.fetch.icacheStallCycles 748921 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 134986415 # Number of instructions fetch has processed
system.cpu.fetch.Branches 28257355 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11860572 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 114720736 # Number of cycles fetch has run and was not squashing or blocked
2015-07-30 09:42:27 +02:00
system.cpu.fetch.SquashCycles 1679131 # Number of cycles fetch has spent squashing
2015-09-25 13:27:03 +02:00
system.cpu.fetch.MiscStallCycles 953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 835 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 32301690 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 580 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 116311010 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.165818 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.319039 # Number of instructions fetched each cycle (Total)
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu.fetch.rateDist::0 58740461 50.50% 50.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 13941673 11.99% 62.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 9230825 7.94% 70.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 34398051 29.57% 100.00% # Number of instructions fetched each cycle (Total)
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu.fetch.rateDist::total 116311010 # Number of instructions fetched each cycle (Total)
2015-07-30 09:42:27 +02:00
system.cpu.fetch.branchRate 0.242838 # Number of branch fetches per cycle
2015-09-25 13:27:03 +02:00
system.cpu.fetch.rate 1.160046 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8839998 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 64050748 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 33034874 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9558063 # Number of cycles decode is unblocking
2015-07-30 09:42:27 +02:00
system.cpu.decode.SquashCycles 827327 # Number of cycles decode is squashing
2015-09-25 13:27:03 +02:00
system.cpu.decode.BranchResolved 4101313 # Number of times decode resolved a branch
2015-07-30 09:42:27 +02:00
system.cpu.decode.BranchMispred 12342 # Number of times decode detected a branch misprediction
2015-09-25 13:27:03 +02:00
system.cpu.decode.DecodedInsts 114429656 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1996969 # Number of squashed instructions handled by decode
2015-07-30 09:42:27 +02:00
system.cpu.rename.SquashCycles 827327 # Number of cycles rename is squashing
2015-09-25 13:27:03 +02:00
system.cpu.rename.IdleCycles 15281198 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 49893829 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 109582 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 35425015 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 14774059 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 110898152 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 1415674 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 11131476 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1144261 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1527056 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 488175 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 129955893 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 483270095 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 119473614 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 428 # Number of floating rename lookups
2014-09-03 13:42:59 +02:00
system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
2015-09-25 13:27:03 +02:00
system.cpu.rename.UndoneMaps 22642974 # Number of HB maps that are undone due to squashing
2014-12-23 15:31:20 +01:00
system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed
2014-09-20 23:18:53 +02:00
system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed
2015-09-25 13:27:03 +02:00
system.cpu.rename.skidInsts 21507084 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26812785 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5349554 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 517855 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 254082 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 109689870 # Number of instructions added to the IQ (excludes non-spec)
2015-07-03 16:15:03 +02:00
system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ
2015-09-25 13:27:03 +02:00
system.cpu.iq.iqInstsIssued 101387714 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1074676 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 18657087 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 41688114 # Number of squashed operands that are examined and possibly removed from graph
2015-07-03 16:15:03 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
2015-09-25 13:27:03 +02:00
system.cpu.iq.issued_per_cycle::samples 116311010 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.871695 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.989305 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-09-25 13:27:03 +02:00
system.cpu.iq.issued_per_cycle::0 54670243 47.00% 47.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 31362294 26.96% 73.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 22008143 18.92% 92.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7072499 6.08% 98.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1197518 1.03% 100.00% # Number of insts issued each cycle
2015-07-30 09:42:27 +02:00
system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2015-09-25 13:27:03 +02:00
system.cpu.iq.issued_per_cycle::total 116311010 # Number of insts issued each cycle
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-09-25 13:27:03 +02:00
system.cpu.iq.fu_full::IntAlu 9794091 48.69% 48.69% # attempts to use FU when none available
2015-07-03 16:15:03 +02:00
system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available
2015-09-25 13:27:03 +02:00
system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.69% # attempts to use FU when none available
2015-07-03 16:15:03 +02:00
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available
2015-09-25 13:27:03 +02:00
system.cpu.iq.fu_full::MemRead 9615955 47.81% 96.50% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 703739 3.50% 100.00% # attempts to use FU when none available
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::IntAlu 71984145 71.00% 71.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::SimdFloatCvt 52 0.00% 71.01% # Type of FU issued
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued
2015-07-30 09:42:27 +02:00
system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued
2015-03-02 11:04:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::MemRead 24343095 24.01% 95.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5049585 4.98% 100.00% # Type of FU issued
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::total 101387714 # Type of FU issued
system.cpu.iq.rate 0.871306 # Inst issue rate
system.cpu.iq.fu_busy_cnt 20113848 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.198385 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 340274513 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 128355901 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 99625297 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 449 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 614 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 111 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 121501328 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 234 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 290500 # Number of loads that had data forwarded from stores
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-09-25 13:27:03 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 4336874 # Number of loads squashed
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed
2015-09-25 13:27:03 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 1345 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 604710 # Number of stores squashed
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-09-25 13:27:03 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 7564 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 130574 # Number of times an access to memory failed due to the cache being blocked
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-07-30 09:42:27 +02:00
system.cpu.iew.iewSquashCycles 827327 # Number of cycles IEW is squashing
2015-09-25 13:27:03 +02:00
system.cpu.iew.iewBlockCycles 8118136 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 109710785 # Number of instructions dispatched to IQ
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2015-09-25 13:27:03 +02:00
system.cpu.iew.iewDispLoadInsts 26812785 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5349554 # Number of dispatched store instructions
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions
2015-09-25 13:27:03 +02:00
system.cpu.iew.iewIQFullEvents 179049 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 342646 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1345 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 436655 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 412870 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 849525 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 100126849 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 23806470 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1260865 # Number of squashed instructions skipped in execute
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-09-25 13:27:03 +02:00
system.cpu.iew.exec_nop 12668 # number of nop insts executed
system.cpu.iew.exec_refs 28724380 # number of memory reference insts executed
system.cpu.iew.exec_branches 20624234 # Number of branches executed
system.cpu.iew.exec_stores 4917910 # Number of stores executed
system.cpu.iew.exec_rate 0.860470 # Inst execution rate
system.cpu.iew.wb_sent 99710000 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 99625408 # cumulative count of insts written-back
system.cpu.iew.wb_producers 59703416 # num instructions producing a value
system.cpu.iew.wb_consumers 95544446 # num instructions consuming a value
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2015-09-25 13:27:03 +02:00
system.cpu.iew.wb_rate 0.856161 # insts written-back per cycle
2015-07-30 09:42:27 +02:00
system.cpu.iew.wb_fanout 0.624876 # average fanout of values written-back
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2015-09-25 13:27:03 +02:00
system.cpu.commit.commitSquashedInsts 17385130 # The number of squashed insts skipped by commit
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
2015-09-25 13:27:03 +02:00
system.cpu.commit.branchMispredicts 825621 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 113618734 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.801396 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.737990 # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-09-25 13:27:03 +02:00
system.cpu.commit.committed_per_cycle::0 77195687 67.94% 67.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 18614563 16.38% 84.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 7151371 6.29% 90.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3466253 3.05% 93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1641564 1.44% 95.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 544784 0.48% 95.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 704352 0.62% 96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 179993 0.16% 96.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4120167 3.63% 100.00% # Number of insts commited each cycle
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-09-25 13:27:03 +02:00
system.cpu.commit.committed_per_cycle::total 113618734 # Number of insts commited each cycle
2015-04-30 21:17:43 +02:00
system.cpu.commit.committedInsts 90602408 # Number of instructions committed
system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 27220755 # Number of memory references committed
system.cpu.commit.loads 22475911 # Number of loads committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 3888 # Number of memory barriers committed
2015-04-30 21:17:43 +02:00
system.cpu.commit.branches 18732305 # Number of branches committed
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 56148 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
2015-09-25 13:27:03 +02:00
system.cpu.commit.bw_lim_events 4120167 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 217931602 # The number of ROB reads
system.cpu.rob.rob_writes 219570402 # The number of ROB writes
system.cpu.timesIdled 589 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51942 # Total number of cycles that the CPU has spent unscheduled due to idling
2015-04-30 21:17:43 +02:00
system.cpu.committedInsts 90589799 # Number of Instructions Simulated
system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
2015-09-25 13:27:03 +02:00
system.cpu.cpi 1.284504 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.284504 # CPI: Total CPI of All Threads
system.cpu.ipc 0.778511 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.778511 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 108111563 # number of integer regfile reads
system.cpu.int_regfile_writes 58701013 # number of integer regfile writes
system.cpu.fp_regfile_reads 59 # number of floating regfile reads
2015-07-30 09:42:27 +02:00
system.cpu.fp_regfile_writes 92 # number of floating regfile writes
2015-09-25 13:27:03 +02:00
system.cpu.cc_regfile_reads 369063684 # number of cc regfile reads
system.cpu.cc_regfile_writes 58693489 # number of cc regfile writes
system.cpu.misc_regfile_reads 28414952 # number of misc regfile reads
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.replacements 5470194 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.787648 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 18251935 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 5470706 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 3.336303 # Average number of references to valid blocks.
2015-07-30 09:42:27 +02:00
system.cpu.dcache.tags.warmup_cycle 35373500 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.787648 # Average occupied blocks per requestor
2015-07-30 09:42:27 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999585 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999585 # Average percentage of cache occupancy
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.tag_accesses 61908668 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 61908668 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13889868 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13889868 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4353786 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4353786 # number of WriteReq hits
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_hits::cpu.data 18243654 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 18243654 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 18244176 # number of overall hits
system.cpu.dcache.overall_hits::total 18244176 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 9585829 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 9585829 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 381195 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 381195 # number of WriteReq misses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_misses::cpu.data 9967024 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9967024 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9967031 # number of overall misses
system.cpu.dcache.overall_misses::total 9967031 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721011000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 88721011000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4006916840 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 4006916840 # number of WriteReq miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 92727927840 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 92727927840 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 92727927840 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 92727927840 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23475697 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23475697 # number of ReadReq accesses(hits+misses)
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
2014-09-20 23:18:53 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_accesses::cpu.data 28210678 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 28210678 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 28211207 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 28211207 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408330 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.408330 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080506 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.080506 # miss rate for WriteReq accesses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.353307 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.353307 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.353300 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.353300 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.434350 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.434350 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.462218 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.462218 # average WriteReq miss latency
2015-07-03 16:15:03 +02:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.471913 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 9303.471913 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.465379 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 9303.465379 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 329844 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 111014 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 121439 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12836 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716129 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 8.648644 # average number of cycles each access was blocked
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu.dcache.writebacks::writebacks 5433212 # number of writebacks
system.cpu.dcache.writebacks::total 5433212 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337614 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4337614 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158708 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 158708 # number of WriteReq MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 4496322 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4496322 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4496322 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4496322 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248215 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5248215 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 5470702 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 5470702 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 5470706 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 5470706 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43247632500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 43247632500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285123725 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285123725 # number of WriteReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532756225 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 45532756225 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45532970725 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 45532970725 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223559 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223559 # mshr miss rate for ReadReq accesses
2015-07-30 09:42:27 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses
2015-03-02 11:04:20 +01:00
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193923 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses
2015-07-03 16:15:03 +02:00
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.446037 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.446037 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.819082 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.819082 # average WriteReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.018915 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.018915 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.052038 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.052038 # average overall mshr miss latency
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.replacements 451 # number of replacements
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.tagsinuse 428.507470 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 32300517 # Total number of references to valid blocks.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.avg_refs 35495.073626 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 428.507470 # Average occupied blocks per requestor
2015-07-30 09:42:27 +02:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.836929 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.836929 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.tag_accesses 64604262 # Number of tag accesses
system.cpu.icache.tags.data_accesses 64604262 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 32300517 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 32300517 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 32300517 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 32300517 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 32300517 # number of overall hits
system.cpu.icache.overall_hits::total 32300517 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1159 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1159 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1159 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1159 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1159 # number of overall misses
system.cpu.icache.overall_misses::total 1159 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 62258984 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 62258984 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 62258984 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 62258984 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 62258984 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 62258984 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 32301676 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 32301676 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 32301676 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 32301676 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 32301676 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 32301676 # number of overall (read+write) accesses
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53717.846419 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 53717.846419 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53717.846419 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53717.846419 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 18998 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 136 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 221 # number of cycles access was blocked
2015-03-02 11:04:20 +01:00
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 85.963801 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50293988 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 50293988 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50293988 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 50293988 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50293988 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 50293988 # number of overall MSHR miss cycles
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55268.118681 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55268.118681 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.prefetcher.num_hwpf_issued 4980719 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 5295706 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 273829 # number of redundant prefetches already in prefetch queue
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.prefetcher.pfSpanPage 14074518 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 620 # number of replacements
system.cpu.l2cache.tags.tagsinuse 12071.188165 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 10691146 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 16060 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 665.700249 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 11063.420038 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 575.029353 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 219.514162 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 213.224612 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.675258 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035097 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.013398 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013014 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.736767 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 266 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15174 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 22 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 9 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 224 # Occupied blocks per task id
2015-07-30 09:42:27 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1064 # Occupied blocks per task id
2015-07-30 09:42:27 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13065 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016235 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.926147 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 175272147 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 175272147 # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks 5433212 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 5433212 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 226010 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 226010 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 215 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 215 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243682 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 5243682 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 215 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 5469692 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 5469907 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 215 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 5469692 # number of overall hits
system.cpu.l2cache.overall_hits::total 5469907 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 509 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 509 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 695 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 695 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 505 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 505 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1014 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1709 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1014 # number of overall misses
system.cpu.l2cache.overall_misses::total 1709 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42306000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 42306000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47939000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47939000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30597000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 30597000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 47939000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 72903000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 120842000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 47939000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 72903000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 120842000 # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks 5433212 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 5433212 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 910 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 910 # number of ReadCleanReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244187 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 5244187 # number of ReadSharedReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 910 # number of demand (read+write) accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_accesses::cpu.data 5470706 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 5471616 # number of demand (read+write) accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_accesses::cpu.inst 910 # number of overall (read+write) accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_accesses::cpu.data 5470706 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 5471616 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002247 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.002247 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.763736 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.763736 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000096 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000096 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.763736 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.000185 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.000312 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.763736 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.000185 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.000312 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83115.913556 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83115.913556 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68976.978417 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68976.978417 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60588.118812 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60588.118812 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68976.978417 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71896.449704 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70709.186659 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68976.978417 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71896.449704 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70709.186659 # average overall miss latency
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.writebacks::writebacks 448 # number of writebacks
system.cpu.l2cache.writebacks::total 448 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 166 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 166 # number of ReadExReq MSHR hits
2015-07-30 09:42:27 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 64 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 64 # number of ReadSharedReq MSHR hits
2015-07-30 09:42:27 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 230 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 231 # number of demand (read+write) MSHR hits
2015-07-30 09:42:27 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 230 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 231 # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20740 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 20740 # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 694 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 694 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 441 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 441 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 784 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1478 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 784 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20740 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 22218 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 848794725 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 848794725 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32842000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32842000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43715500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43715500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24991500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24991500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43715500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 57833500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 101549000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43715500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 57833500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 848794725 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 950343725 # number of overall MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.762637 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.000270 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for overall accesses
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.004061 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 40925.493009 # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95749.271137 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95749.271137 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62990.634006 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62990.634006 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56670.068027 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56670.068027 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68707.036536 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42773.594608 # average overall mshr miss latency
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 10942261 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470659 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 6201 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 6201 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 5245097 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 5433660 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 34692 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 22620 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244187 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408705 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 16410964 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697850752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 697908992 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 23240 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 10965501 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001098 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.033119 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::0 10953460 99.89% 99.89% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 12041 0.11% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 10965501 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10904342500 # Layer occupancy (ticks)
2015-07-30 09:42:27 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1367495 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 8206062992 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadResp 15718 # Transaction distribution
system.membus.trans_dist::Writeback 448 # Transaction distribution
system.membus.trans_dist::CleanEvict 139 # Transaction distribution
system.membus.trans_dist::ReadExReq 343 # Transaction distribution
system.membus.trans_dist::ReadExResp 343 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 15718 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32709 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 32709 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1056576 # Cumulative packet size per connected master and slave (bytes)
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::samples 16648 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::0 16648 100.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::total 16648 # Request fanout histogram
system.membus.reqLayer0.occupancy 28374711 # Layer occupancy (ticks)
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.respLayer1.occupancy 84025804 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
