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gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
sim_seconds 0.634728 # Number of seconds simulated
sim_ticks 634728078000 # Number of ticks simulated
final_tick 634728078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
host_inst_rate 97161 # Simulator instruction rate (inst/s)
host_op_rate 132320 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44547849 # Simulator tick rate (ticks/s)
host_mem_usage 267228 # Number of bytes of host memory used
host_seconds 14248.23 # Real time elapsed on the host
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.bytes_read::cpu.inst 156032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 30243456 # Number of bytes read from this memory
system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 156032 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 156032 # Number of instructions bytes read from this memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.num_reads::cpu.inst 2438 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 472554 # Number of read requests responded to by this memory
system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.bw_read::cpu.inst 245825 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 47647894 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 47893719 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 245825 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 245825 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 6664700 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 6664700 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 6664700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 245825 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47647894 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54558418 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 474992 # Number of read requests accepted
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 66098 # Number of write requests accepted
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.readBursts 474992 # Number of DRAM read bursts, including those serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.bytesReadDRAM 30375808 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 23680 # Total number of bytes read from write queue
system.physmem.bytesWritten 4229120 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 30399488 # Total read bytes from the system interface side
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.servicedByWrQ 370 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.neitherReadNorWriteReqs 4530 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 29868 # Per bank write bursts
system.physmem.perBankRdBursts::1 29664 # Per bank write bursts
system.physmem.perBankRdBursts::2 29737 # Per bank write bursts
system.physmem.perBankRdBursts::3 29712 # Per bank write bursts
system.physmem.perBankRdBursts::4 29799 # Per bank write bursts
system.physmem.perBankRdBursts::5 29810 # Per bank write bursts
system.physmem.perBankRdBursts::6 29625 # Per bank write bursts
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.perBankRdBursts::7 29426 # Per bank write bursts
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankRdBursts::8 29475 # Per bank write bursts
system.physmem.perBankRdBursts::9 29463 # Per bank write bursts
system.physmem.perBankRdBursts::10 29528 # Per bank write bursts
system.physmem.perBankRdBursts::11 29636 # Per bank write bursts
system.physmem.perBankRdBursts::12 29682 # Per bank write bursts
system.physmem.perBankRdBursts::13 29788 # Per bank write bursts
system.physmem.perBankRdBursts::14 29619 # Per bank write bursts
system.physmem.perBankRdBursts::15 29790 # Per bank write bursts
system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankWrBursts::2 4137 # Per bank write bursts
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankWrBursts::3 4147 # Per bank write bursts
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.perBankWrBursts::6 4171 # Per bank write bursts
system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankWrBursts::9 4090 # Per bank write bursts
system.physmem.perBankWrBursts::10 4093 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.totGap 634728009000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.readPktSize::6 474992 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::0 407642 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 66616 # What read queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::15 981 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrQLenPdf::17 3992 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4007 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::20 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4014 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4013 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.bytesPerActivate::samples 192766 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 179.514147 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 129.738688 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 208.062403 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 72454 37.59% 37.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 88147 45.73% 83.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 20712 10.74% 94.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 450 0.23% 94.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 454 0.24% 94.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 512 0.27% 94.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 512 0.27% 95.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 605 0.31% 95.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8920 4.63% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 192766 # Bytes accessed per row activation
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.rdPerTurnAround::mean 48.628151 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 36.096624 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 506.030557 # Reads before turning the bus around for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrPerTurnAround::mean 16.491141 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.469437 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.863273 # Writes before turning the bus around for reads
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.wrPerTurnAround::17 2 0.05% 75.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 974 24.31% 99.85% # Writes before turning the bus around for reads
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrPerTurnAround::19 6 0.15% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.totQLat 4985394000 # Total ticks spent queuing
system.physmem.totMemAccLat 13884556500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2373110000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10503.93 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.avgMemAccLat 29253.93 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 47.86 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 6.66 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 47.89 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 6.66 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.avgWrQLen 19.25 # Average write queue length when enqueuing
system.physmem.readRowHits 298015 # Number of row buffer hits during reads
system.physmem.writeRowHits 49917 # Number of row buffer hits during writes
system.physmem.readRowHitRate 62.79 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes
system.physmem.avgGap 1173054.41 # Average gap between requests
system.physmem.pageHitRate 64.35 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 171675355500 # Time in different power states
system.physmem.memoryStateTime::REF 21194940000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.physmem.memoryStateTime::ACT 441857292000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.membus.throughput 54558418 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 408916 # Transaction distribution
system.membus.trans_dist::ReadResp 408916 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::Writeback 66098 # Transaction distribution
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4530 # Transaction distribution
system.membus.trans_dist::ReadExReq 66076 # Transaction distribution
system.membus.trans_dist::ReadExResp 66076 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1025142 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1025142 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34629760 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 34629760 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 34629760 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.membus.reqLayer0.occupancy 1216030000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.membus.respLayer1.occupancy 4441818720 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.branchPred.lookups 478607550 # Number of BP lookups
system.cpu.branchPred.condPredicted 378292816 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 30666231 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 334166811 # Number of BTB lookups
system.cpu.branchPred.BTBHits 254063804 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.branchPred.BTBHitPct 76.029036 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 60780885 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2806336 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.numCycles 1269456157 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.fetch.icacheStallCycles 382172768 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2398528075 # Number of instructions fetch has processed
system.cpu.fetch.Branches 478607550 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 314844689 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 646500630 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 176126555 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 55590458 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 12318 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 120 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 358033766 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6993732 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1229682095 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.711139 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.182068 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.fetch.rateDist::0 583226842 47.43% 47.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 47324489 3.85% 51.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 105202734 8.56% 59.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 59348034 4.83% 64.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 82117278 6.68% 71.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 49221552 4.00% 75.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 36109976 2.94% 78.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 30221135 2.46% 80.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 236910055 19.27% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.fetch.rateDist::total 1229682095 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.377018 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.889414 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 407354221 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 47938688 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 625726372 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3270610 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 145392204 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 52977001 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 97525 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3244658117 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 31782 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 145392204 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 431843071 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 21602754 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 464275 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 603219561 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 27160230 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3179170609 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6664902 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 18155043 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 78588 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 2271 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 3142601872 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 15333387016 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13133730346 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 83988681 # Number of floating rename lookups
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.rename.UndoneMaps 1149461782 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 21762 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 19092 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 48856011 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1039047790 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 516447707 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 54890431 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 57377876 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2969017113 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 28780 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2494321710 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 29655363 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 1083496611 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2947742555 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 7396 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1229682095 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.028428 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.901891 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.issued_per_cycle::0 391713450 31.85% 31.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 177167826 14.41% 46.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 194208889 15.79% 62.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 164750014 13.40% 75.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 152000166 12.36% 87.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 91333270 7.43% 95.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 42323460 3.44% 98.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 13601870 1.11% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2583150 0.21% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.issued_per_cycle::total 1229682095 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.fu_full::IntAlu 1141867 1.24% 1.24% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 24392 0.03% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.27% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 58632065 63.67% 64.94% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 32290785 35.06% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.FU_type_0::IntAlu 1135683319 45.53% 45.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11247917 0.45% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 5502263 0.22% 46.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 23390431 0.94% 47.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 860090981 34.48% 81.95% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 450155032 18.05% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iq.FU_type_0::total 2494321710 # Type of FU issued
system.cpu.iq.rate 1.964874 # Inst issue rate
system.cpu.iq.fu_busy_cnt 92089109 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.036919 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6216205899 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3969996640 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2305202146 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 123864088 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 82618605 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 56425277 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2521728263 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 64682556 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 98529432 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 407660609 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5276533 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 2500816 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 239452410 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 420 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.iewSquashCycles 145392204 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 15914893 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1611898 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2969058590 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2618613 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 1039047790 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 516447707 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 18794 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1555522 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 56228 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 2500816 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 33181152 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1519240 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 34700392 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2424200983 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 818208051 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 70120727 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.exec_nop 12697 # number of nop insts executed
system.cpu.iew.exec_refs 1248100004 # number of memory reference insts executed
system.cpu.iew.exec_branches 329019811 # Number of branches executed
system.cpu.iew.exec_stores 429891953 # Number of stores executed
system.cpu.iew.exec_rate 1.909637 # Inst execution rate
system.cpu.iew.wb_sent 2388820620 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2361627423 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1389701712 # num instructions producing a value
system.cpu.iew.wb_consumers 2644997142 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.iew.wb_rate 1.860346 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.525408 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.commitSquashedInsts 1083730173 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.branchMispredicts 30653233 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1084289891 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.738775 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.404247 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.committed_per_cycle::0 445713482 41.11% 41.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 287271007 26.49% 67.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 94862412 8.75% 76.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 69719327 6.43% 82.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 46233776 4.26% 87.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 22314720 2.06% 89.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 15854088 1.46% 90.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 11019318 1.02% 91.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 91301761 8.42% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.committed_per_cycle::total 1084289891 # Number of insts commited each cycle
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.refs 908382478 # Number of memory references committed
system.cpu.commit.loads 631387181 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 9986 # Number of memory barriers committed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.commit.branches 298259106 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 930022484 49.33% 49.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 11168279 0.59% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 1375288 0.07% 49.99% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.99% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 6876469 0.36% 50.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 5501172 0.29% 50.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 22010188 1.17% 51.82% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.82% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.82% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.82% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 631387181 33.49% 85.31% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 276995297 14.69% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1885336358 # Class of committed instruction
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.commit.bw_lim_events 91301761 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.rob.rob_reads 3962036316 # The number of ROB reads
system.cpu.rob.rob_writes 6083536675 # The number of ROB writes
system.cpu.timesIdled 355726 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 39774062 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.cpi 0.916992 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.916992 # CPI: Total CPI of All Threads
system.cpu.ipc 1.090523 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.090523 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12060176633 # number of integer regfile reads
system.cpu.int_regfile_writes 2272688052 # number of integer regfile writes
system.cpu.fp_regfile_reads 68797676 # number of floating regfile reads
system.cpu.fp_regfile_writes 49536165 # number of floating regfile writes
system.cpu.misc_regfile_reads 1701422665 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.toL2Bus.throughput 167841675 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1495790 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1495789 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 96290 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 4533 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 4533 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72512 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72512 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57900 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179527 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3237427 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1707776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 106243776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 106243776 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 290048 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 930852999 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 47253245 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 2371526007 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.tags.replacements 24993 # number of replacements
system.cpu.icache.tags.tagsinuse 1647.783456 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 357995053 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 26684 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 13416.094026 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1647.783456 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.804582 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.804582 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1691 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.825684 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 716098748 # Number of tag accesses
system.cpu.icache.tags.data_accesses 716098748 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 357999320 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 357999320 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 357999320 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 357999320 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 357999320 # number of overall hits
system.cpu.icache.overall_hits::total 357999320 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 34446 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 34446 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 34446 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 34446 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 34446 # number of overall misses
system.cpu.icache.overall_misses::total 34446 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 570147243 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 570147243 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 570147243 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 570147243 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 570147243 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 570147243 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 358033766 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 358033766 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 358033766 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 358033766 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 358033766 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 358033766 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16551.914388 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16551.914388 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16551.914388 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16551.914388 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16551.914388 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1683 # number of cycles access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 60.107143 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3230 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 3230 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 3230 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 3230 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 3230 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 3230 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31216 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 31216 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 31216 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 31216 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 31216 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 31216 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 454582253 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 454582253 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 454582253 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 454582253 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 454582253 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 454582253 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14562.476070 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14562.476070 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14562.476070 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14562.476070 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14562.476070 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14562.476070 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.tags.replacements 442210 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32678.682015 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1111317 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 474958 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.339822 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 1315.086004 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.777344 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31312.818667 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.040133 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001550 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.955591 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.997274 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32748 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4974 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27020 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999390 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 13864217 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 13864217 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 24244 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1058074 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1082318 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 96290 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 96290 # number of Writeback hits
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 6436 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 6436 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 24244 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1064510 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1088754 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 24244 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1064510 # number of overall hits
system.cpu.l2cache.overall_hits::total 1088754 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2440 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 406500 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 408940 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4530 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 4530 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 66076 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66076 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2440 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 472576 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 475016 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2440 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 472576 # number of overall misses
system.cpu.l2cache.overall_misses::total 475016 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 176349750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29369544500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 29545894250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756102500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4756102500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 176349750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 34125647000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 34301996750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 176349750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 34125647000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 34301996750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 26684 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1464574 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1491258 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 96290 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 96290 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4533 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 4533 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72512 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72512 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 26684 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1537086 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1563770 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 26684 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1537086 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1563770 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.091441 # miss rate for ReadReq accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277555 # miss rate for ReadReq accesses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.274225 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999338 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999338 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911242 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911242 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.091441 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.307449 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.303763 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.091441 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.307449 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.303763 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72274.487705 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72249.801968 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72249.949259 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71979.273866 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71979.273866 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72274.487705 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.976486 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72212.297586 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72274.487705 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.976486 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72212.297586 # average overall miss latency
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2438 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406478 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 408916 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4530 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4530 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66076 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66076 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2438 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 472554 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 474992 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2438 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 472554 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 474992 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145569750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24308392500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24453962250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45304530 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45304530 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3923643500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3923643500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145569750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28232036000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 28377605750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145569750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28232036000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 28377605750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277540 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274209 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999338 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999338 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911242 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911242 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.303748 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091366 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307435 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.303748 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59708.675144 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59802.480085 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59801.920810 # average ReadReq mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59380.766088 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59380.766088 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59708.675144 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59743.512911 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59743.334098 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.tags.replacements 1532989 # number of replacements
system.cpu.dcache.tags.tagsinuse 4094.399228 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 981387634 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1537085 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 638.473236 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 399634250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.399228 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999609 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999609 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 980 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2382 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 428 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.tags.tag_accesses 1969885597 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1969885597 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 705264252 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 705264252 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276089331 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 276089331 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.demand_hits::cpu.data 981353583 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 981353583 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 981353583 # number of overall hits
system.cpu.dcache.overall_hits::total 981353583 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1954339 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1954339 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 846347 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 846347 # number of WriteReq misses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.demand_misses::cpu.data 2800686 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2800686 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2800686 # number of overall misses
system.cpu.dcache.overall_misses::total 2800686 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78948283141 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 78948283141 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 58782925343 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 58782925343 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 464000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 464000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 137731208484 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 137731208484 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 137731208484 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 137731208484 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 707218591 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 707218591 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.demand_accesses::cpu.data 984154269 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 984154269 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 984154269 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 984154269 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002763 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002763 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003056 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003056 # miss rate for WriteReq accesses
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.002846 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002846 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002846 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002846 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40396.411851 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40396.411851 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69454.875297 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69454.875297 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 154666.666667 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 154666.666667 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 49177.668787 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49177.668787 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 49177.668787 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2986 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 861 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 60 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 79 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.766667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 10.898734 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.writebacks::writebacks 96290 # number of writebacks
system.cpu.dcache.writebacks::total 96290 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489763 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 489763 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769304 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 769304 # number of WriteReq MSHR hits
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 1259067 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1259067 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1259067 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1259067 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464576 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1464576 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77043 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 77043 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1541619 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1541619 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1541619 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1541619 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41415183522 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 41415183522 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4998292971 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4998292971 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46413476493 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 46413476493 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46413476493 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 46413476493 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002071 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002071 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001566 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001566 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001566 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28277.934038 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28277.934038 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64876.665901 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64876.665901 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.969681 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.969681 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
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