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gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
sim_seconds 0.633885 # Number of seconds simulated
sim_ticks 633884897500 # Number of ticks simulated
final_tick 633884897500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
host_inst_rate 87779 # Simulator instruction rate (inst/s)
host_op_rate 119542 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 40192628 # Simulator tick rate (ticks/s)
host_mem_usage 283676 # Number of bytes of host memory used
host_seconds 15771.17 # Real time elapsed on the host
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 30242944 # Number of bytes read from this memory
system.physmem.bytes_read::total 30398080 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 472546 # Number of read requests responded to by this memory
system.physmem.num_reads::total 474970 # Number of read requests responded to by this memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bw_read::cpu.inst 244738 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 47710466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 47955205 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 244738 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 244738 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 6673565 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 6673565 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 6673565 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 244738 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47710466 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54628770 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 474970 # Number of read requests accepted
system.physmem.writeReqs 66098 # Number of write requests accepted
system.physmem.readBursts 474970 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 30392000 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue
system.physmem.bytesWritten 4230080 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 30398080 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4324 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 29875 # Per bank write bursts
system.physmem.perBankRdBursts::1 29673 # Per bank write bursts
system.physmem.perBankRdBursts::2 29745 # Per bank write bursts
system.physmem.perBankRdBursts::3 29707 # Per bank write bursts
system.physmem.perBankRdBursts::4 29817 # Per bank write bursts
system.physmem.perBankRdBursts::5 29835 # Per bank write bursts
system.physmem.perBankRdBursts::6 29655 # Per bank write bursts
system.physmem.perBankRdBursts::7 29450 # Per bank write bursts
system.physmem.perBankRdBursts::8 29485 # Per bank write bursts
system.physmem.perBankRdBursts::9 29492 # Per bank write bursts
system.physmem.perBankRdBursts::10 29547 # Per bank write bursts
system.physmem.perBankRdBursts::11 29655 # Per bank write bursts
system.physmem.perBankRdBursts::12 29700 # Per bank write bursts
system.physmem.perBankRdBursts::13 29805 # Per bank write bursts
system.physmem.perBankRdBursts::14 29629 # Per bank write bursts
system.physmem.perBankRdBursts::15 29805 # Per bank write bursts
system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
system.physmem.perBankWrBursts::2 4138 # Per bank write bursts
system.physmem.perBankWrBursts::3 4148 # Per bank write bursts
system.physmem.perBankWrBursts::4 4226 # Per bank write bursts
system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
system.physmem.perBankWrBursts::9 4094 # Per bank write bursts
system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4140 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 633884833500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 474970 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 407902 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 66613 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 276 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 3004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 3008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesPerActivate::samples 190556 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 181.682403 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 122.345891 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 377.529861 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64 76623 40.21% 40.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 50018 26.25% 66.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 37571 19.72% 86.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 19599 10.29% 96.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 202 0.11% 96.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 233 0.12% 96.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 93 0.05% 96.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 219 0.11% 96.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 79 0.04% 96.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 59 0.03% 97.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768 225 0.12% 97.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832 74 0.04% 97.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896 178 0.09% 97.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960 61 0.03% 97.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024 176 0.09% 97.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088 47 0.02% 97.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152 188 0.10% 97.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216 71 0.04% 97.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280 186 0.10% 97.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344 71 0.04% 97.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408 3176 1.67% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472 17 0.01% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536 14 0.01% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600 12 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664 11 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728 7 0.00% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792 10 0.01% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856 16 0.01% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920 14 0.01% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048 23 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112 18 0.01% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176 9 0.00% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304 13 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368 10 0.01% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432 12 0.01% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496 24 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560 8 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624 18 0.01% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688 22 0.01% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752 22 0.01% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816 14 0.01% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944 11 0.01% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008 10 0.01% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072 8 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136 14 0.01% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200 4 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264 19 0.01% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328 19 0.01% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392 21 0.01% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456 17 0.01% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520 18 0.01% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584 12 0.01% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648 19 0.01% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712 10 0.01% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776 12 0.01% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840 10 0.01% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904 12 0.01% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968 16 0.01% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032 16 0.01% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096 16 0.01% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160 31 0.02% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224 17 0.01% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288 10 0.01% 99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352 9 0.00% 99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416 11 0.01% 99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480 6 0.00% 99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544 17 0.01% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672 16 0.01% 99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736 14 0.01% 99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800 19 0.01% 99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864 17 0.01% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928 16 0.01% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992 3 0.00% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056 13 0.01% 99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120 6 0.00% 99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184 7 0.00% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248 7 0.00% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312 10 0.01% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376 14 0.01% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440 20 0.01% 99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504 16 0.01% 99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632 12 0.01% 99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696 34 0.02% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760 69 0.04% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824 58 0.03% 99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888 3 0.00% 99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952 1 0.00% 99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016 3 0.00% 99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144 59 0.03% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 190556 # Bytes accessed per row activation
system.physmem.totQLat 3723849000 # Total ticks spent queuing
system.physmem.totMemAccLat 15162897750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2374375000 # Total ticks spent in databus transfers
system.physmem.totBankLat 9064673750 # Total ticks spent accessing banks
system.physmem.avgQLat 7841.75 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 19088.55 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 31930.29 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 47.95 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 6.67 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 47.96 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 6.67 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 4.41 # Average write queue length when enqueuing
system.physmem.readRowHits 301072 # Number of row buffer hits during reads
system.physmem.writeRowHits 49342 # Number of row buffer hits during writes
system.physmem.readRowHitRate 63.40 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.65 # Row buffer hit rate for writes
system.physmem.avgGap 1171543.75 # Average gap between requests
system.physmem.pageHitRate 64.77 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 24.91 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 54628770 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 408895 # Transaction distribution
system.membus.trans_dist::ReadResp 408895 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::Writeback 66098 # Transaction distribution
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.trans_dist::UpgradeReq 4324 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4324 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024686 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1024686 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34628352 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 34628352 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 34628352 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.reqLayer0.occupancy 1216897000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.membus.respLayer1.occupancy 4442648676 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.branchPred.lookups 445875274 # Number of BP lookups
system.cpu.branchPred.condPredicted 355714891 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 31013117 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 262160312 # Number of BTB lookups
system.cpu.branchPred.BTBHits 234316871 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.branchPred.BTBHitPct 89.379231 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 52540791 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2805997 # Number of incorrect RAS predictions.
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.numCycles 1267769796 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.icacheStallCycles 359604051 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2297734506 # Number of instructions fetch has processed
system.cpu.fetch.Branches 445875274 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 286857662 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 606667357 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 159378109 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 130943287 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11360 # Number of stall cycles due to pending traps
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.CacheLines 340050056 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 11891209 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1225539818 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.573745 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.170795 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.rateDist::0 618917347 50.50% 50.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 42971146 3.51% 54.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 97897325 7.99% 62.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 56071890 4.58% 66.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 75061628 6.12% 72.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 45063261 3.68% 76.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 31435951 2.57% 78.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 31903606 2.60% 81.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 226217664 18.46% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.fetch.rateDist::total 1225539818 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.351701 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.812423 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 410024939 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 104223819 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 567090713 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 15899066 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 128301281 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 47087821 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 11947 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3044373258 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 26488 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 128301281 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 445072814 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 37752394 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 469546 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 545867989 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 68075794 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2962731385 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 107 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4402501 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 53439360 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 9 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2946792223 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 14100168268 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 12232464769 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 87261724 # Number of floating rename lookups
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.rename.UndoneMaps 953652133 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 20387 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 17854 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 175792199 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 972804227 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 491413736 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 36509550 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 42116928 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2808310459 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27673 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2443543142 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 13552705 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 910455744 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2345608138 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 6289 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1225539818 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.993850 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.871016 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.issued_per_cycle::0 386142313 31.51% 31.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 183212489 14.95% 46.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 204921233 16.72% 63.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 171581285 14.00% 77.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 134431508 10.97% 88.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 92278264 7.53% 95.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 37194117 3.03% 98.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 12766594 1.04% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 3012015 0.25% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.issued_per_cycle::total 1225539818 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.fu_full::IntAlu 692354 0.79% 0.79% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 24381 0.03% 0.81% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.fu_full::MemRead 55108221 62.64% 63.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 32145057 36.54% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.FU_type_0::IntAlu 1110380096 45.44% 45.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11223911 0.46% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.28% 46.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 5502670 0.23% 46.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 23408416 0.96% 47.42% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.42% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.42% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.42% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 840781219 34.41% 81.83% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 443995061 18.17% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iq.FU_type_0::total 2443543142 # Type of FU issued
system.cpu.iq.rate 1.927434 # Inst issue rate
system.cpu.iq.fu_busy_cnt 87970013 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.036001 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6090822143 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3633185531 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2257760958 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 123326677 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 85675338 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 56498576 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2467787139 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 63726016 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 85165626 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 341417046 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 38150 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1428012 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 214418439 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 322 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.iewSquashCycles 128301281 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 16032166 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1560767 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2808350603 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 961806 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 972804227 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 491413736 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 17687 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1557116 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1428012 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 32911757 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1861954 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 34773711 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2367002070 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 794874980 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 76541072 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.exec_nop 12471 # number of nop insts executed
system.cpu.iew.exec_refs 1219940656 # number of memory reference insts executed
system.cpu.iew.exec_branches 321608336 # Number of branches executed
system.cpu.iew.exec_stores 425065676 # Number of stores executed
system.cpu.iew.exec_rate 1.867060 # Inst execution rate
system.cpu.iew.wb_sent 2340031230 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2314259534 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1351078205 # num instructions producing a value
system.cpu.iew.wb_consumers 2527156960 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.iew.wb_rate 1.825457 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.534624 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.commit.commitSquashedInsts 923014366 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.commit.branchMispredicts 31001379 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1097238537 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.718256 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.389874 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.commit.committed_per_cycle::0 455331878 41.50% 41.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 289999556 26.43% 67.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 95581485 8.71% 76.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 70096070 6.39% 83.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 46571745 4.24% 87.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 22195585 2.02% 89.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 15856765 1.45% 90.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 11363497 1.04% 91.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 90241956 8.22% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.commit.committed_per_cycle::total 1097238537 # Number of insts commited each cycle
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.refs 908382478 # Number of memory references committed
system.cpu.commit.loads 631387181 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 9986 # Number of memory barriers committed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.commit.branches 298259106 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.commit.bw_lim_events 90241956 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.rob.rob_reads 3815328960 # The number of ROB reads
system.cpu.rob.rob_writes 5745013824 # The number of ROB writes
system.cpu.timesIdled 352945 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 42229978 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.cpi 0.915773 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.915773 # CPI: Total CPI of All Threads
system.cpu.ipc 1.091973 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.091973 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 11799440532 # number of integer regfile reads
system.cpu.int_regfile_writes 2227507770 # number of integer regfile writes
system.cpu.fp_regfile_reads 68853045 # number of floating regfile reads
system.cpu.fp_regfile_writes 49554235 # number of floating regfile writes
system.cpu.misc_regfile_reads 1367872939 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.throughput 167773046 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1492868 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1492867 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 96315 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 4328 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 4328 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52441 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178974 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3231415 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1539648 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104532224 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 106071872 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 106071872 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 276928 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 929329999 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 42995247 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 2368559798 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.tags.replacements 22373 # number of replacements
system.cpu.icache.tags.tagsinuse 1644.727747 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 340012575 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 24056 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 14134.210800 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1644.727747 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.803090 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.803090 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 340019150 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 340019150 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 340019150 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 340019150 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 340019150 # number of overall hits
system.cpu.icache.overall_hits::total 340019150 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 30904 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 30904 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 30904 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 30904 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 30904 # number of overall misses
system.cpu.icache.overall_misses::total 30904 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 530577244 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 530577244 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 530577244 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 530577244 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 530577244 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 530577244 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 340050054 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 340050054 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 340050054 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 340050054 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 340050054 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 340050054 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000091 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000091 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000091 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17168.562128 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17168.562128 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17168.562128 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17168.562128 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17168.562128 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1738 # number of cycles access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.blocked::no_mshrs 31 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 56.064516 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2520 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2520 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2520 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2520 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2520 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2520 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28384 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 28384 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 28384 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 28384 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 28384 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 28384 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 424232750 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 424232750 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 424232750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 424232750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 424232750 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 424232750 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000083 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000083 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000083 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000083 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14946.193278 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14946.193278 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14946.193278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14946.193278 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.tags.replacements 442189 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32678.484609 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1109448 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 474936 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.335995 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 1308.214481 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.900676 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31321.369452 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.039924 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001492 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.955852 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.997268 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 21631 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1057987 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1079618 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 96315 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 96315 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 6443 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 6443 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 21631 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1064430 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1086061 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 21631 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1064430 # number of overall hits
system.cpu.l2cache.overall_hits::total 1086061 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2426 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 406497 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 408923 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4324 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 4324 # number of UpgradeReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 2426 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 472572 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 474998 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2426 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 472572 # number of overall misses
system.cpu.l2cache.overall_misses::total 474998 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175176750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 30663807500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 30838984250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4756616500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4756616500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 175176750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 35420424000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 35595600750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 175176750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 35420424000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 35595600750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 24057 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1464484 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1488541 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 96315 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 96315 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4328 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 4328 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72518 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72518 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 24057 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1537002 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1561059 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 24057 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1537002 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1561059 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100844 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277570 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.274714 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999076 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999076 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911153 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911153 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100844 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.307463 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.304279 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100844 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.307463 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.304279 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72208.058533 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75434.277498 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75415.137446 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71988.142263 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71988.142263 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74938.422372 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72208.058533 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74952.438993 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74938.422372 # average overall miss latency
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2424 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406471 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 408895 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4324 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4324 # number of UpgradeReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 472546 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 474970 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 472546 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 474970 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 144597750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25603608250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25748206000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43244324 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43244324 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3924227000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3924227000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 144597750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29527835250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 29672433000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 144597750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29527835250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 29672433000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277552 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274695 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999076 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999076 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911153 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911153 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.304261 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100761 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307447 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.304261 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59652.537129 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62989.999902 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62970.214847 # average ReadReq mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.495649 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.495649 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59652.537129 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62486.689656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62472.225614 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.tags.replacements 1532905 # number of replacements
system.cpu.dcache.tags.tagsinuse 4094.387385 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 971436889 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1537001 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 632.033999 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 400661250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.387385 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999606 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999606 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 695310256 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 695310256 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276092959 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 276092959 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.demand_hits::cpu.data 971403215 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 971403215 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 971403215 # number of overall hits
system.cpu.dcache.overall_hits::total 971403215 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1954136 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1954136 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 842719 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 842719 # number of WriteReq misses
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.demand_misses::cpu.data 2796855 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2796855 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2796855 # number of overall misses
system.cpu.dcache.overall_misses::total 2796855 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 80332980069 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 80332980069 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 58617620770 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 58617620770 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 225000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 138950600839 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 138950600839 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 138950600839 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 138950600839 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 697264392 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 697264392 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.demand_accesses::cpu.data 974200070 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 974200070 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 974200070 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 974200070 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41109.206355 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 41109.206355 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69557.730121 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69557.730121 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 49681.017013 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49681.017013 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 49681.017013 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2430 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 892 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 86 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.392857 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 10.372093 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.writebacks::writebacks 96315 # number of writebacks
system.cpu.dcache.writebacks::total 96315 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489650 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 489650 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765875 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 765875 # number of WriteReq MSHR hits
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.cpu.dcache.demand_mshr_hits::cpu.data 1255525 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1255525 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1255525 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1255525 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464486 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1464486 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76844 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 76844 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1541330 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1541330 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1541330 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1541330 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42708562776 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 42708562776 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4994223926 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4994223926 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47702786702 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 47702786702 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47702786702 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 47702786702 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002100 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002100 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29162.834452 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29162.834452 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64991.722529 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64991.722529 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30949.106747 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30949.106747 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink