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gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt

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Added a SPARC_SE simple timing mcf regression. --HG-- extra : convert_revision : d8fea11c37bd3f0b5f5e8880c92b711892ee8125
2007-03-30 00:39:34 +02:00
---------- Begin Simulation Statistics ----------
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
sim_seconds 0.361489 # Number of seconds simulated
sim_ticks 361488530000 # Number of ticks simulated
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sparc: update long regressions
2011-06-13 03:35:03 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_inst_rate 1070091 # Simulator instruction rate (inst/s)
host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1586487053 # Simulator tick rate (ticks/s)
host_mem_usage 406976 # Number of bytes of host memory used
host_seconds 227.85 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.throughput 2762444 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1036 # Transaction distribution
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.data_through_bus 998592 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.workload.num_syscalls 443 # Number of system calls
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.numCycles 722977060 # number of cpu cycles simulated
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.committedInsts 243825150 # Number of instructions committed
system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726494 # number of integer instructions
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.num_fp_insts 11630 # number of float instructions
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.num_mem_refs 105711441 # number of memory refs
system.cpu.num_load_insts 82803521 # Number of load instructions
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.num_busy_cycles 722977060 # Number of busy cycles
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
stats: updates due to branch predictor warming
2014-02-16 18:40:34 +01:00
system.cpu.Branches 29302884 # Number of branches fetched
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction
system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 244431613 # Class of executed instruction
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 25 # number of replacements
system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
system.cpu.icache.overall_hits::total 244420617 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
system.cpu.icache.overall_misses::total 882 # number of overall misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15068052 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15068052 # Number of data accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Added a SPARC_SE simple timing mcf regression. --HG-- extra : convert_revision : d8fea11c37bd3f0b5f5e8880c92b711892ee8125
2007-03-30 00:39:34 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
sparc: update long regressions
2011-06-13 03:35:03 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.replacements 935475 # number of replacements
system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
system.cpu.dcache.writebacks::total 935266 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
Added a SPARC_SE simple timing mcf regression. --HG-- extra : convert_revision : d8fea11c37bd3f0b5f5e8880c92b711892ee8125
2007-03-30 00:39:34 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink