2007-03-30 00:39:34 +02:00
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|
---------- Begin Simulation Statistics ----------
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2010-09-22 08:07:35 +02:00
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|
sim_seconds 0.362431 # Number of seconds simulated
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|
|
|
|
sim_ticks 362430887000 # Number of ticks simulated
|
2012-01-25 18:19:50 +01:00
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|
|
final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-06-13 03:35:03 +02:00
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|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2012-05-09 20:52:14 +02:00
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|
|
host_inst_rate 628265 # Simulator instruction rate (inst/s)
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|
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|
host_op_rate 628291 # Simulator op (including micro ops) rate (op/s)
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|
host_tick_rate 933876298 # Simulator tick rate (ticks/s)
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|
host_mem_usage 354916 # Number of bytes of host memory used
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|
|
|
|
host_seconds 388.09 # Real time elapsed on the host
|
2012-02-12 23:07:43 +01:00
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sim_insts 243825163 # Number of instructions simulated
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|
sim_ops 243835278 # Number of ops (including micro ops) simulated
|
2012-01-25 18:19:50 +01:00
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|
|
system.physmem.bytes_read 1001472 # Number of bytes read from this memory
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|
system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 2560 # Number of bytes written to this memory
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|
system.physmem.num_reads 15648 # Number of read requests responded to by this memory
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system.physmem.num_writes 40 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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|
|
|
|
system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s)
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|
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|
system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s)
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|
system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s)
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|
system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s)
|
2011-06-13 03:35:03 +02:00
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|
|
system.cpu.workload.num_syscalls 443 # Number of system calls
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|
|
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|
system.cpu.numCycles 724861774 # number of cpu cycles simulated
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|
|
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|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-02-12 23:07:43 +01:00
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|
system.cpu.committedInsts 243825163 # Number of instructions committed
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|
|
|
|
system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
|
2011-06-13 03:35:03 +02:00
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|
|
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
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|
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
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system.cpu.num_func_calls 4252956 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
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system.cpu.num_int_insts 194726506 # number of integer instructions
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|
system.cpu.num_fp_insts 11630 # number of float instructions
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system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
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2011-12-01 00:57:11 +01:00
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system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written
|
2011-06-13 03:35:03 +02:00
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system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
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|
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|
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
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system.cpu.num_mem_refs 105711442 # number of memory refs
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|
system.cpu.num_load_insts 82803522 # Number of load instructions
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|
system.cpu.num_store_insts 22907920 # Number of store instructions
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|
system.cpu.num_idle_cycles 0 # Number of idle cycles
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|
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|
system.cpu.num_busy_cycles 724861774 # Number of busy cycles
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|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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|
system.cpu.idle_fraction 0 # Percentage of idle cycles
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|
|
system.cpu.icache.replacements 25 # number of replacements
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|
|
|
|
system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use
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|
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|
system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
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|
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
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|
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
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|
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|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
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|
|
system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor
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|
system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
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|
|
|
|
system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
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|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
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|
|
|
|
system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits
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|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits
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|
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|
|
system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits
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|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits
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|
|
|
|
system.cpu.icache.overall_hits::total 244420630 # number of overall hits
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|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
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|
|
|
|
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
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|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
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|
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
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|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
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|
|
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|
system.cpu.icache.overall_misses::total 882 # number of overall misses
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|
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|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles
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|
system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles
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|
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|
system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles
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|
system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles
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|
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|
system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles
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|
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|
system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses)
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|
|
|
|
system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses)
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|
|
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|
system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses
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|
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|
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system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses
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|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses
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|
|
|
|
system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses
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|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
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|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
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|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
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|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
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|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
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|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
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|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-13 03:35:03 +02:00
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|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
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|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
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|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
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|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
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|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
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|
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|
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
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|
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
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|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
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|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
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|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
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|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 935475 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
|
|
|
|
|
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 104182818 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
|
|
|
|
|
system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2007-03-30 00:39:34 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 935237 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 865 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 924805 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 15648 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2007-03-30 00:39:34 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 40 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
2011-06-13 03:35:03 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-03-30 00:39:34 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
