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gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[root]
type=Root
children=system
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
full_system=false
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
sim_quantum=0
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system]
type=System
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
boot_osflags=a
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
cache_line_size=64
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
init_param=0
kernel=
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
kernel_addr_check=true
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
load_addr_mask=1099511627775
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
load_offset=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
mem_mode=timing
mem_ranges=
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
memories=system.physmem
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
mmap_using_noreserve=false
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
num_work_ids=16
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
readfile=
symbolfile=
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
system_port=system.membus.slave[0]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.clk_domain]
type=SrcClockDomain
clock=1000
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu]
type=DerivO3CPU
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
LFSTSize=1024
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
LQEntries=16
ARM: Update stats for previous changes.
2011-04-04 18:42:31 +02:00
LSQCheckLoads=true
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
LSQDepCheckShift=0
SQEntries=16
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
SSITSize=1024
activity=0
backComSize=5
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
branchPred=system.cpu.branchPred
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
cachePorts=200
checker=Null
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
decodeToRenameDelay=2
decodeWidth=3
dispatchWidth=6
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
do_checkpoint_insts=true
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
do_quiesce=true
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
do_statistics_insts=true
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
dstage2_mmu=system.cpu.dstage2_mmu
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
dtb=system.cpu.dtb
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
fetchBufferSize=16
fetchQueueSize=32
fetchToDecodeDelay=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
fetchTrapLatency=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
fetchWidth=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
interrupts=system.cpu.interrupts
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
isa=system.cpu.isa
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueToExecuteDelay=1
issueWidth=8
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
istage2_mmu=system.cpu.istage2_mmu
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
needsTSO=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
numIQEntries=32
numPhysCCRegs=640
numPhysFloatRegs=192
numPhysIntRegs=128
numROBEntries=40
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
numRobs=1
numThreads=1
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
profile=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
renameToIEWDelay=1
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
renameToROBDelay=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
renameWidth=3
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
simpoint_start_insts=
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
socket_id=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
squashWidth=8
StoreSet: Update stats for store-set clearing
2011-08-19 22:08:08 +02:00
store_set_clear_period=250000
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
switched_out=false
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system=system
tracer=system.cpu.tracer
trapLatency=13
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
[system.cpu.branchPred]
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
type=BiModeBP
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
BTBEntries=2048
BTBTagSize=18
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
numThreads=1
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.dcache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
addr_ranges=0:18446744073709551615
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
forward_snoops=true
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
hit_latency=2
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
is_top_level=true
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
max_miss_count=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mshrs=6
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
response_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.dcache.tags
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tgts_per_mshr=8
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
two_queue=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
write_buffers=16
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
cpu_side=system.cpu.dcache_port
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
mem_side=system.cpu.toL2Bus.slave[1]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
hit_latency=2
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
size=32768
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.dtb]
type=ArmTLB
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
size=64
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
sys=system
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
port=system.cpu.toL2Bus.slave[3]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.fuPool]
type=FUPool
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=FUList0 FUList1 FUList2 FUList3 FUList4
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=opList0 opList1 opList2
count=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=12
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
opClass=IntDiv
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=12
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList1.opList2]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=IprAccess
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList2]
type=FUDesc
children=opList
count=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opList=system.cpu.fuPool.FUList2.opList
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList2.opList]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=MemRead
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
children=opList
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
count=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opList=system.cpu.fuPool.FUList3.opList
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList3.opList]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=MemWrite
opLat=2
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=FUDesc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
count=2
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList00]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdAdd
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=4
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList01]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdAddAcc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=4
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList02]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdAlu
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=4
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList03]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdCmp
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=4
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList04]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdCvt
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList05]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdMisc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList06]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdMult
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=5
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList07]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdMultAcc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=5
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList08]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdShift
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList09]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdShiftAcc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList10]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdSqrt
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=9
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList11]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdFloatAdd
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=5
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList12]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdFloatAlu
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=5
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList13]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdFloatCmp
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList14]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdFloatCvt
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList15]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdFloatDiv
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList16]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdFloatMisc
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList17]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdFloatMult
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=3
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList18]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList19]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
opClass=SimdFloatSqrt
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opLat=9
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList20]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=FloatAdd
opLat=5
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList21]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=1
opClass=FloatCmp
opLat=5
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList22]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
issueLat=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
opClass=FloatCvt
opLat=5
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList23]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=9
opClass=FloatDiv
opLat=9
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList24]
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=33
opClass=FloatSqrt
opLat=33
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.fuPool.FUList4.opList25]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
type=OpDesc
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
issueLat=1
opClass=FloatMult
opLat=4
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.icache]
type=BaseCache
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
children=tags
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
addr_ranges=0:18446744073709551615
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
assoc=2
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
forward_snoops=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
hit_latency=1
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
is_top_level=true
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
max_miss_count=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mshrs=2
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
prefetch_on_access=false
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
prefetcher=Null
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
response_latency=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
size=32768
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.icache.tags
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tgts_per_mshr=8
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
mem_side=system.cpu.toL2Bus.slave[0]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
hit_latency=1
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
size=32768
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
[system.cpu.interrupts]
type=ArmInterrupts
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
[system.cpu.isa]
type=ArmISA
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
fpsid=1090793632
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr0=270536963
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_mmfr1=0
id_mmfr2=19070976
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_mmfr3=34611729
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
id_pfr0=49
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
id_pfr1=4113
midr=1091551472
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
pmu=Null
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
sys=system
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.itb]
type=ArmTLB
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
children=walker
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
size=64
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
is_stage2=false
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
num_squash_per_cycle=2
Regressions: Update stats due to O3 CPU changes
2012-02-10 16:51:37 +01:00
sys=system
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
port=system.cpu.toL2Bus.slave[2]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.l2cache]
type=BaseCache
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
children=prefetcher tags
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
addr_ranges=0:18446744073709551615
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
assoc=16
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
demand_mshr_reserve=1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
forward_snoops=true
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
hit_latency=12
ARM: Update stats for the previous changes and add ARM_FS/O3 regression.
2011-03-18 01:20:22 +01:00
is_top_level=false
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
max_miss_count=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
mshrs=16
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
response_latency=12
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
size=1048576
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system=system
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
tags=system.cpu.l2cache.tags
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tgts_per_mshr=8
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
two_queue=false
write_buffers=8
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
cache_snoop=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
clk_domain=system.cpu_clk_domain
degree=8
eventq_index=0
latency=1
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
max_conf=7
min_conf=0
on_data=true
on_inst=true
on_miss=false
on_read=true
on_write=true
queue_filter=true
queue_size=32
queue_squash=true
start_conf=4
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
sys=system
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
table_assoc=4
table_sets=16
tag_prefetch=true
thresh_conf=4
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
use_master_id=true
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu.l2cache.tags]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=RandomRepl
assoc=16
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
block_size=64
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
hit_latency=12
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
sequential_access=false
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
size=1048576
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.toL2Bus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.cpu_clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
forward_latency=0
frontend_latency=1
response_latency=1
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
snoop_filter=Null
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
snoop_response_latency=1
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system=system
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
use_default_range=false
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
width=32
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
master=system.cpu.l2cache.cpu_side
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.tracer]
type=ExeTracer
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
drivers=
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
egid=100
env=
errout=cerr
euid=100
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
gid=100
input=cin
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
kvmInSE=false
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
useArchPT=false
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
domain_id=-1
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
init_perf_level=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage_domain=system.voltage_domain
stats: updates due to recent ruby and x86 changes Also updates many out of date config files.
2014-09-01 23:55:52 +02:00
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.membus]
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
type=CoherentXBar
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
forward_latency=4
frontend_latency=3
response_latency=2
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
snoop_filter=Null
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
snoop_response_latency=4
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system=system
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
use_default_range=false
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
width=16
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
master=system.physmem.port
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
slave=system.system_port system.cpu.l2cache.mem_side
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
[system.physmem]
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
type=DRAMCtrl
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
IDD0=0.075000
IDD02=0.000000
IDD2N=0.050000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
IDD2P1=0.000000
IDD2P12=0.000000
IDD3N=0.057000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
IDD3P1=0.000000
IDD3P12=0.000000
IDD4R=0.187000
IDD4R2=0.000000
IDD4W=0.165000
IDD4W2=0.000000
IDD5=0.220000
IDD52=0.000000
IDD6=0.000000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
activation_limit=4
stats: update for previous changeset Very small differences in IQ-specific O3 stats.
2015-04-23 05:22:29 +02:00
addr_mapping=RoRaBaCoCh
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
bank_groups_per_rank=0
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
banks_per_rank=8
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
burst_length=8
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
channels=1
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
device_size=536870912
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
devices_per_rank=8
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
dll=true
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
in_addr_map=true
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
max_accesses_per_row=16
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
mem_sched_policy=frfcfs
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
min_writes_per_switch=16
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
null=false
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
page_policy=open_adaptive
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
range=0:134217727
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
ranks_per_channel=2
read_buffer_size=32
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
static_backend_latency=10000
static_frontend_latency=10000
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
tBURST=5000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tCCD_L=0
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tCK=1250
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
tCL=13750
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tCS=2500
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
tRAS=35000
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
tRCD=13750
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
tREFI=7800000
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tRFC=260000
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
tRP=13750
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tRRD=6000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tRRD_L=0
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tRTP=7500
tRTW=2500
tWR=15000
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
tWTR=7500
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
tXAW=30000
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
tXP=0
tXPDLL=0
tXS=0
tXSDLL=0
stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-06-22 23:33:09 +02:00
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
ARM: Update stats for CBNZ fix.
2012-03-09 21:33:07 +01:00
port=system.membus.master[0]
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
[system.voltage_domain]
type=VoltageDomain
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
eventq_index=0
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
voltage=1.000000
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