2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
2014-06-22 23:33:09 +02:00
|
|
|
sim_seconds 0.023058 # Number of seconds simulated
|
|
|
|
|
sim_ticks 23058360500 # Number of ticks simulated
|
|
|
|
|
final_tick 23058360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2011-06-21 00:57:14 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2014-06-22 23:33:09 +02:00
|
|
|
host_inst_rate 185322 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_op_rate 185322 # Simulator op (including micro ops) rate (op/s)
|
|
|
|
|
host_tick_rate 50763012 # Simulator tick rate (ticks/s)
|
|
|
|
|
host_mem_usage 226392 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 454.24 # Real time elapsed on the host
|
2011-06-21 00:57:14 +02:00
|
|
|
sim_insts 84179709 # Number of instructions simulated
|
2012-02-12 23:07:43 +01:00
|
|
|
sim_ops 84179709 # Number of ops (including micro ops) simulated
|
2014-01-24 22:29:33 +01:00
|
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
|
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.bytes_read::cpu.inst 196416 # Number of bytes read from this memory
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.bytes_read::total 334848 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read::cpu.inst 196416 # Number of instructions bytes read from this memory
|
|
|
|
|
system.physmem.bytes_inst_read::total 196416 # Number of instructions bytes read from this memory
|
|
|
|
|
system.physmem.num_reads::cpu.inst 3069 # Number of read requests responded to by this memory
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory
|
|
|
|
|
system.physmem.bw_read::cpu.inst 8518212 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::cpu.data 6003549 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_read::total 14521761 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read::cpu.inst 8518212 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read::total 8518212 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::cpu.inst 8518212 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::cpu.data 6003549 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_total::total 14521761 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.physmem.readReqs 5232 # Number of read requests accepted
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.bytesReadDRAM 334848 # Total number of bytes read from DRAM
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
|
|
|
|
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.bytesReadSys 334848 # Total read bytes from the system interface side
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
|
|
|
|
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
|
|
|
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
|
|
|
|
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.perBankRdBursts::0 471 # Per bank write bursts
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.perBankRdBursts::1 291 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankRdBursts::2 302 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankRdBursts::3 524 # Per bank write bursts
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.perBankRdBursts::4 220 # Per bank write bursts
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.perBankRdBursts::5 225 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankRdBursts::6 219 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankRdBursts::7 286 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankRdBursts::8 240 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankRdBursts::9 278 # Per bank write bursts
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.perBankRdBursts::10 248 # Per bank write bursts
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.perBankRdBursts::11 253 # Per bank write bursts
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.perBankRdBursts::12 398 # Per bank write bursts
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.perBankRdBursts::13 338 # Per bank write bursts
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.perBankRdBursts::14 491 # Per bank write bursts
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.perBankRdBursts::15 448 # Per bank write bursts
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
|
|
|
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
|
|
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
|
|
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.totGap 23058233500 # Total gap between requests
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
|
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
|
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
|
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
|
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
|
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.readPktSize::6 5232 # Read request sizes (log2)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
|
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
|
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
|
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
|
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
|
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
|
|
|
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.rdQLenPdf::0 3262 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::2 633 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::3 105 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
2012-10-30 14:35:32 +01:00
|
|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.bytesPerActivate::samples 871 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::mean 381.722158 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::gmean 229.044875 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::stdev 356.837953 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::0-127 257 29.51% 29.51% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::128-255 194 22.27% 51.78% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::256-383 84 9.64% 61.42% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::384-511 65 7.46% 68.89% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::512-639 35 4.02% 72.90% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::640-767 36 4.13% 77.04% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::768-895 31 3.56% 80.60% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::896-1023 43 4.94% 85.53% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::1024-1151 126 14.47% 100.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::total 871 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.totQLat 38517250 # Total ticks spent queuing
|
|
|
|
|
system.physmem.totMemAccLat 136617250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
|
|
|
system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers
|
|
|
|
|
system.physmem.avgQLat 7361.86 # Average queueing delay per DRAM burst
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.avgMemAccLat 26111.86 # Average memory access latency per DRAM burst
|
|
|
|
|
system.physmem.avgRdBW 14.52 # Average DRAM read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.avgRdBWSys 14.52 # Average system read bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
|
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
2013-01-31 13:49:16 +01:00
|
|
|
system.physmem.busUtil 0.11 # Data bus utilization in percentage
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
|
|
|
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.readRowHits 4353 # Number of row buffer hits during reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads
|
2012-10-25 19:14:42 +02:00
|
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.avgGap 4407154.72 # Average gap between requests
|
|
|
|
|
system.physmem.pageHitRate 83.20 # Row buffer hit rate, read and write combined
|
|
|
|
|
system.physmem.memoryStateTime::IDLE 21416461750 # Time in different power states
|
|
|
|
|
system.physmem.memoryStateTime::REF 769860000 # Time in different power states
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
2014-06-22 23:33:09 +02:00
|
|
|
system.physmem.memoryStateTime::ACT 869038750 # Time in different power states
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
2014-06-22 23:33:09 +02:00
|
|
|
system.membus.throughput 14521761 # Throughput (bytes/s)
|
|
|
|
|
system.membus.trans_dist::ReadReq 3525 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 3525 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 1707 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 1707 # Transaction distribution
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.data_through_bus 334848 # Total data (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.membus.reqLayer0.occupancy 6496500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.membus.respLayer1.occupancy 48985000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.branchPred.lookups 15361032 # Number of BP lookups
|
|
|
|
|
system.cpu.branchPred.condPredicted 11166301 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.branchPred.condIncorrect 940671 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.branchPred.BTBLookups 8650721 # Number of BTB lookups
|
|
|
|
|
system.cpu.branchPred.BTBHits 7195754 # Number of BTB hits
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.branchPred.BTBHitPct 83.180974 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branchPred.usedRAS 1505004 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.branchPred.RASInCorrect 3205 # Number of incorrect RAS predictions.
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dtb.read_hits 23573955 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 207074 # DTB read misses
|
|
|
|
|
system.cpu.dtb.read_acv 4 # DTB read access violations
|
|
|
|
|
system.cpu.dtb.read_accesses 23781029 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_hits 7120317 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 1134 # DTB write misses
|
|
|
|
|
system.cpu.dtb.write_acv 4 # DTB write access violations
|
|
|
|
|
system.cpu.dtb.write_accesses 7121451 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.data_hits 30694272 # DTB hits
|
|
|
|
|
system.cpu.dtb.data_misses 208208 # DTB misses
|
|
|
|
|
system.cpu.dtb.data_acv 8 # DTB access violations
|
|
|
|
|
system.cpu.dtb.data_accesses 30902480 # DTB accesses
|
|
|
|
|
system.cpu.itb.fetch_hits 15234213 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 102 # ITB misses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.itb.fetch_accesses 15234315 # ITB accesses
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 389 # Number of system calls
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.numCycles 46116722 # number of cpu cycles simulated
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.fetch.icacheStallCycles 15940932 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.Insts 131589057 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.Branches 15361032 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.predictedBranches 8700758 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.Cycles 22892353 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.SquashCycles 5007718 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.BlockedCycles 2994752 # Number of cycles fetch has spent blocked
|
|
|
|
|
system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu.fetch.PendingTrapStallCycles 2134 # Number of stall cycles due to pending traps
|
2014-03-23 16:12:19 +01:00
|
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.fetch.CacheLines 15234213 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 364576 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.rateDist::samples 45860852 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.869311 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.407633 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.fetch.rateDist::0 22968499 50.08% 50.08% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1 2435887 5.31% 55.39% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 1214898 2.65% 58.04% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3 1783514 3.89% 61.93% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4 2844070 6.20% 68.13% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5 1193047 2.60% 70.74% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6 1264346 2.76% 73.49% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7 807487 1.76% 75.25% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 11349104 24.75% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.fetch.rateDist::total 45860852 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.branchRate 0.333090 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.rate 2.853391 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.decode.IdleCycles 16942268 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.BlockedCycles 2554020 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.RunCycles 21969696 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.UnblockCycles 376134 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.decode.SquashCycles 4018734 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.BranchResolved 2597948 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.BranchMispred 12434 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DecodedInsts 128314772 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.SquashedInsts 36360 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.rename.SquashCycles 4018734 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.IdleCycles 17696753 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.BlockCycles 830389 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.serializeStallCycles 7936 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RunCycles 21575239 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.UnblockCycles 1731801 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RenamedInsts 125347310 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.ROBFullEvents 9609 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.IQFullEvents 982853 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.LQFullEvents 675750 # Number of times rename has blocked due to LQ full
|
|
|
|
|
system.cpu.rename.SQFullEvents 22720 # Number of times rename has blocked due to SQ full
|
|
|
|
|
system.cpu.rename.RenamedOperands 92019426 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RenameLookups 162776933 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.int_rename_lookups 155390791 # Number of integer rename lookups
|
|
|
|
|
system.cpu.rename.fp_rename_lookups 7386141 # Number of floating rename lookups
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.rename.UndoneMaps 23592065 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.serializingInsts 733 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.tempSerializingInsts 723 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.rename.skidInsts 3333773 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.memDep0.insertedLoads 26203423 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 8541215 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.conflictingLoads 2901793 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 1268500 # Number of conflicting stores.
|
|
|
|
|
system.cpu.iq.iqInstsAdded 108868755 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 1841 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqInstsIssued 97966771 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 305092 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 24205687 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 18927840 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1452 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.issued_per_cycle::samples 45860852 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::mean 2.136174 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::stdev 1.932064 # Number of insts issued each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::0 12004778 26.18% 26.18% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::1 8735781 19.05% 45.22% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::2 7795942 17.00% 62.22% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::3 6187579 13.49% 75.72% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::4 4939987 10.77% 86.49% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::5 3238381 7.06% 93.55% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::6 1831298 3.99% 97.54% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::7 880120 1.92% 99.46% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::8 246986 0.54% 100.00% # Number of insts issued each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::total 45860852 # Number of insts issued each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.fu_full::IntAlu 202355 11.05% 11.05% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 11.05% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.05% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 107 0.01% 11.05% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.05% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 8618 0.47% 11.52% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 9498 0.52% 12.04% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 955023 52.14% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.18% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemRead 532552 29.07% 93.25% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::MemWrite 123630 6.75% 100.00% # attempts to use FU when none available
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 59518834 60.75% 60.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 484423 0.49% 61.25% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 2816502 2.87% 64.12% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 115449 0.12% 64.24% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 2407923 2.46% 66.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 312382 0.32% 67.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 763359 0.78% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 24335343 24.84% 92.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 7212230 7.36% 100.00% # Type of FU issued
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 97966771 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.124322 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 1831783 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.018698 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 228533724 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 123769088 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 88239146 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 15397545 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 9344200 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 7119957 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 91612691 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 8185856 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 1667830 # Number of loads that had data forwarded from stores
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 6207225 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 16318 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 37199 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 2040112 # Number of stores squashed
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 40236 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 2728 # Number of times an access to memory failed due to the cache being blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 4018734 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 14986 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 580703 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 119442937 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 327587 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 26203423 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 8541215 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 1841 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 22416 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 558101 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 37199 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 549687 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 504581 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 1054268 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 96742235 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 23781507 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1224536 # Number of squashed instructions skipped in execute
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.exec_nop 10572341 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 30903185 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 12219901 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 7121678 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.097769 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 95961828 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 95359103 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 65705546 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 92226364 # num instructions consuming a value
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.iew.wb_rate 2.067777 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.712438 # average fanout of values written-back
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 27540320 # The number of squashed insts skipped by commit
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 928822 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 41842118 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.196425 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.812600 # Number of insts commited each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 16239554 38.81% 38.81% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 9401519 22.47% 61.28% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 4137637 9.89% 71.17% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 2136234 5.11% 76.27% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 1534088 3.67% 79.94% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 1088589 2.60% 82.54% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 699410 1.67% 84.21% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 798893 1.91% 86.12% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 5806194 13.88% 100.00% # Number of insts commited each cycle
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 41842118 # Number of insts commited each cycle
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 26497301 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 19996198 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 10240685 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntAlu 51001542 55.49% 63.90% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatAdd 2732464 2.97% 67.37% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::MemRead 19996198 21.76% 92.93% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
|
|
|
system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 5806194 # number cycles where commit BW limit reached
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.rob.rob_reads 155478259 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 242937786 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 5286 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 255870 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.cpi 0.547837 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.547837 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 1.825362 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.825362 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 130779467 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 71543363 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 6233836 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 6101151 # number of floating regfile writes
|
|
|
|
|
system.cpu.misc_regfile_reads 718857 # number of misc regfile reads
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.toL2Bus.throughput 37986395 # Throughput (bytes/s)
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 11847 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 11847 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1732 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1732 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22674 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4591 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 27265 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725568 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150336 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.tot_pkt_size::total 875904 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.data_through_bus 875904 # Total data (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 17583000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3542750 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.tags.replacements 9401 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 1598.407560 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 15220036 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 11337 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 1342.510011 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1598.407560 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.780472 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.780472 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 931 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.icache.tags.tag_accesses 30479761 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 30479761 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 15220036 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 15220036 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 15220036 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 15220036 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 15220036 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 15220036 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 14176 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 14176 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 14176 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 14176 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 14176 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 14176 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 411369250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 411369250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 411369250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 411369250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 411369250 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 411369250 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 15234212 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 15234212 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 15234212 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 15234212 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 15234212 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 15234212 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000931 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000931 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000931 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.000931 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000931 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.000931 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29018.711202 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 29018.711202 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 29018.711202 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29018.711202 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 29018.711202 # average overall miss latency
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2839 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2839 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2839 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 2839 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2839 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 2839 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11337 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 11337 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 11337 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 11337 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 11337 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 11337 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302662500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 302662500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302662500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 302662500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302662500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 302662500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000744 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000744 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000744 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000744 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26696.877481 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26696.877481 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26696.877481 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 26696.877481 # average overall mshr miss latency
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.tags.tagsinuse 2409.556828 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 8337 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 2.321637 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 17.688406 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2013.956930 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 377.911492 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061461 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011533 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.073534 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109589 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 114811 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 114811 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 8268 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 54 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 8322 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 25 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 25 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 8268 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 8347 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 8268 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 8347 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3069 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 456 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 3525 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1707 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 1707 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3069 # number of demand (read+write) misses
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 2163 # number of demand (read+write) misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.demand_misses::total 5232 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3069 # number of overall misses
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 2163 # number of overall misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.overall_misses::total 5232 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 208636250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35488000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 244124250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122872750 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 122872750 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 208636250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 158360750 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 366997000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 208636250 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 158360750 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 366997000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11337 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 510 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 11847 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1732 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1732 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 11337 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2242 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 13579 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 11337 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2242 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 13579 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.270707 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.894118 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.297544 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985566 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985566 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.270707 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964764 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.385301 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.270707 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964764 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.385301 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67981.834474 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77824.561404 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69255.106383 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71981.693029 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71981.693029 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67981.834474 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73213.476653 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 70144.686544 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67981.834474 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73213.476653 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 70144.686544 # average overall miss latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3069 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 456 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3525 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1707 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1707 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3069 # number of demand (read+write) MSHR misses
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2163 # number of demand (read+write) MSHR misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 5232 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3069 # number of overall MSHR misses
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2163 # number of overall MSHR misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 169758750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29825000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199583750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101974750 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101974750 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169758750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131799750 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 301558500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169758750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131799750 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 301558500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270707 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.894118 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.297544 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985566 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985566 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.270707 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.385301 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.270707 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964764 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.385301 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55314.027370 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65405.701754 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56619.503546 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59739.162273 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59739.162273 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55314.027370 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60933.772538 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57637.327982 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55314.027370 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60933.772538 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57637.327982 # average overall mshr miss latency
|
2012-11-02 17:50:06 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.tags.replacements 157 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 1456.621503 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 28355724 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 2242 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 12647.512935 # Average number of references to valid blocks.
|
2013-08-19 09:52:36 +02:00
|
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 1456.621503 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.355620 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.355620 # Average percentage of cache occupancy
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.tags.tag_accesses 56732342 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 56732342 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 21862715 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 21862715 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 6492763 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 6492763 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 246 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 246 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 28355478 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 28355478 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 28355478 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 28355478 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 985 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 985 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 8340 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 8340 # number of WriteReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 9325 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 9325 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 9325 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 9325 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 61174750 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 61174750 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 507348010 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 507348010 # number of WriteReq miss cycles
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 568522760 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 568522760 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 568522760 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 568522760 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 21863700 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 21863700 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 247 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 28364803 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 28364803 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 28364803 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 28364803 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001283 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001283 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004049 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004049 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000329 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.000329 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000329 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.000329 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62106.345178 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 62106.345178 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60833.094724 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 60833.094724 # average WriteReq miss latency
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 60967.588204 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60967.588204 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 60967.588204 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 27950 # number of cycles access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.942857 # average number of cycles each access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 476 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 476 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6608 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 6608 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 7084 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 7084 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 7084 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 7084 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 509 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 509 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2241 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 2241 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2241 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 2241 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36463750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36463750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124994997 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 124994997 # number of WriteReq MSHR miss cycles
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161458747 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 161458747 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161458747 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 161458747 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004049 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004049 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000079 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71638.015717 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71638.015717 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72168.012125 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72168.012125 # average WriteReq mshr miss latency
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
|
2014-06-22 23:33:09 +02:00
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72047.633646 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72047.633646 # average overall mshr miss latency
|
2011-06-21 00:57:14 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
