Andreas Hansson
74553c7d3f
stats: Update the stats to reflect bus and memory changes
...
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00
Nilay Vaish
4646369afd
regressions: update due to cache latency fix
2013-03-27 18:36:21 -05:00
Andreas Hansson
cb9e208a4c
stats: Update stats to reflect SimpleDRAM changes
...
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
2013-03-01 13:20:30 -05:00
Nilay Vaish
1962e9262d
regressions: update stats due to changes to ruby
2013-02-10 21:43:23 -06:00
Andreas Hansson
fce3433b2e
stats: Update stats for regressions using SimpleDDR3
...
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
2013-01-31 07:49:16 -05:00
Nilay Vaish
9bc132e473
regressions: update stats due to branch predictor changes
...
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
2013-01-24 12:29:00 -06:00
Ali Saidi
fbeced6135
stats: update stats for previous six changes
2013-01-08 08:54:16 -05:00
Ali Saidi
9f15510c2c
stats: update stats for previous changes.
2013-01-07 13:05:54 -05:00
Nilay Vaish
5ebe3210d8
regressions: stats update due to decoder changes
2013-01-04 19:00:48 -06:00
Ali Saidi
1dbf9bb4ca
update stats for preceeding changes
2012-11-02 11:50:06 -05:00
Andreas Hansson
10b70d5452
stats: Update stats for unified cache configuration
...
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
2012-10-30 09:35:32 -04:00
Andreas Hansson
8fe556338d
stats: Update stats to reflect use of SimpleDRAM
...
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
2012-10-25 13:14:42 -04:00
Andreas Hansson
54227f9e57
Stats: Update stats for new default L1-to-L2 bus clock and width
...
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
2012-10-15 08:09:54 -04:00
Ali Saidi
91e74beee6
ARM: update stats for bp and squash fixes.
2012-09-25 11:49:41 -05:00
Andreas Hansson
ae1652b813
Stats: Remove the reference stats that are no longer present
...
This patch simply removes the commitCommittedInsts and
commitCommittedOps from the reference statistics, following their
removal from the CPU.
2012-09-13 08:02:55 -04:00
Andreas Hansson
fda338f8d3
Stats: Updates due to bus changes
...
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
2012-07-09 12:35:41 -04:00
Ali Saidi
3965ecc36b
Stats: Update stats for RAS and LRU fixes.
2012-06-29 11:19:03 -04:00
Ali Saidi
c49e739352
all: Update stats for memory per master and total fix.
2012-06-05 01:23:16 -04:00
Nathan Binkert
4a644767c5
stats: update stats for no_value -> nan
...
Lots of accumulated older changes too.
2012-05-09 11:52:14 -07:00
Ali Saidi
3c666083c6
ARM: Update stats for IT and conditional branch changes
2012-03-21 10:36:45 -05:00
Ali Saidi
470051345a
ARM: Update stats for CBNZ fix.
2012-03-09 15:33:07 -05:00
Geoffrey Blake
da0d67c3d6
CheckerCPU: Make some basic regression tests for CheckerCPU
...
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
2012-03-09 09:59:28 -05:00
