Commit graph

228 commits

Author SHA1 Message Date
Brad Beckmann
6f9bd33b73 ruby: remove the cpu assumptions for the random tester 2012-07-10 22:51:54 -07:00
Brad Beckmann
11b725c19d ruby: changes how Topologies are created
Instead of just passing a list of controllers to the makeTopology function
in src/mem/ruby/network/topologies/<Topo>.py we pass in a function pointer
which knows how to make the topology, possibly with some extra state set
in the configs/ruby/<protocol>.py file. Thus, we can move all of the files
from network/topologies to configs/topologies. A new class BaseTopology
is added which all topologies in configs/topologies must inheirit from and
follow its API.

--HG--
rename : src/mem/ruby/network/topologies/Crossbar.py => configs/topologies/Crossbar.py
rename : src/mem/ruby/network/topologies/Mesh.py => configs/topologies/Mesh.py
rename : src/mem/ruby/network/topologies/MeshDirCorners.py => configs/topologies/MeshDirCorners.py
rename : src/mem/ruby/network/topologies/Pt2Pt.py => configs/topologies/Pt2Pt.py
rename : src/mem/ruby/network/topologies/Torus.py => configs/topologies/Torus.py
2012-07-10 22:51:53 -07:00
Nilay Vaish
abb85a68f4 Config: call to setWorkCountOptions() for all ISAs 2012-06-07 08:05:31 -05:00
Nilay Vaish
51c23e601e Config: Remove setMipsOptions
As status matrix, MIPS fs does not work. Hence, these options are not
required. Secondly, the function is setting param values for a CPU class.
This seems strange, should probably be done in a different way.
2012-06-07 08:05:30 -05:00
Nilay Vaish
78a72d6972 Config: changes to a couple of error msgs 2012-06-07 08:05:30 -05:00
Andreas Hansson
0d32940711 Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.

--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 13:30:04 -04:00
Andreas Hansson
7f14ea0c00 Config: Fix a typo in the se.py script for setting fastmem
This patch changes a hardcoded index 0 to the appropriate CPU index so
that fastmem is set correctly for all the CPUs in the system.
2012-05-16 12:37:08 -04:00
Jayneel Gandhi
7aa57ac882 SE Config: Changed se.py to support multithreaded mode
Multithreaded programs did not run by just specifying the binary once on the
command line of SE mode.The default mode is multi-programmed mode. Added
check in SE mode to run multi-threaded programs in case only one program is
specified with multiple CPUS. Default mode is still multi-programmed mode.
2012-04-17 16:12:41 -05:00
Jayneel Gandhi
b5b9d2ad3e Config: Add command line options for disk image and memory size
Added the options to Options.py for FS mode with backward compatibility. It is
good to provide an option to specify the disk image and the memory size from
command line since a lot of disk images are created to support different
benchmark suites as well as per user needs. Change in program also leads to
change in memory requirements. These options provide the interface to provide
both disk image and memory size from the command line and gives more
flexibility.
2012-04-16 17:51:26 -05:00
Brad Beckmann
0a9f4b950f rubytest: seperated read and write ports.
This patch allows the ruby tester to support protocols where the i-cache and d-cache
are managed by seperate controllers.
2012-04-06 13:47:06 -07:00
Andreas Hansson
b00949d88b MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.

--HG--
rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py
rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py
rename : src/mem/physical.cc => src/mem/abstract_mem.cc
rename : src/mem/physical.hh => src/mem/abstract_mem.hh
rename : src/mem/physical.cc => src/mem/simple_mem.cc
rename : src/mem/physical.hh => src/mem/simple_mem.hh
2012-04-06 13:46:31 -04:00
Nilay Vaish
4f4a710457 Config: corrects the way Ruby attaches to the DMA ports
With recent changes to the memory system, a port cannot be assigned a peer
port twice. While making use of the Ruby memory system in FS mode, DMA
ports were assigned peer twice, once for the classic memory system
and once for the Ruby memory system. This patch removes this double
assignment of peer ports.
2012-04-05 11:09:19 -05:00
Andreas Hansson
f1a6090613 Ruby: Fix the example configurations option parsing
This patch fixes the, currently broken, Ruby example scripts to
reflect the changes in the parsing of command-line options.
2012-04-05 10:45:26 -04:00
Andreas Hansson
a8e6adb0b1 Atomic: Remove the physmem_port and access memory directly
This patch removes the physmem_port from the Atomic CPU and instead
uses the system pointer to access the physmem when using the fastmem
option. The system already keeps track of the physmem and the valid
memory address ranges, and with this patch we merely make use of that
existing functionality. As a result of this change, the overloaded
getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
2012-04-03 03:50:14 -04:00
Nilay Vaish
390cfc7be9 Config: Change the way options are added
I am not too happy with the way options are added in files se.py and fs.py
currently. This patch moves all the options to the file Options.py, functions
from which are called when required.
2012-03-28 11:01:53 -05:00
Nilay Vaish
6ca3af8ecf Config: Move setWorkCountOptions() to Simulation.py
The function is presently defined in FSConfig.py, which does not seem to be
the correct place for it.
2012-03-27 18:23:21 -05:00
Nilay Vaish
f02eec93d6 ruby_fs.py: Add call to createInterruptController() 2012-03-16 07:47:03 -05:00
Nilay Vaish
bb7be54d73 se.py: Changes to ruby portion due to SE/FS merge
With the SE/FS merge, interrupt controller is created irrespective of the
mode. This patch creates the interrupt controller when Ruby is used and
connects its ports.
2012-03-11 16:51:38 -05:00
Ali Saidi
d2a0db7fe9 ARM: Fix memory starting at non-zero address and exceeding max mem for a system. 2012-03-09 16:45:47 -05:00
Geoffrey Blake
043709fdfa CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files.  Also merges with the SE/FS changes.
2012-03-09 09:59:27 -05:00
Ali Saidi
eaa994e7f6 cache: Allow main memory to be at disjoint address ranges. 2012-03-09 09:59:25 -05:00
Ali Saidi
91b737ed48 ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
2012-03-01 17:26:31 -06:00
Nilay Vaish
c80af04d7d x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for
cpus that will be switched in later
2012-03-01 11:37:02 -06:00
Nilay Vaish
e11847bfa9 Config: make option ruby available always 2012-03-01 11:36:59 -06:00
Andreas Hansson
6cf9f182f6 MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.
2012-02-14 14:15:30 -05:00
Andreas Hansson
00978170f3 MEM: Fix master/slave ports in Ruby and non-regression scripts
This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.
2012-02-14 03:41:53 -05:00
Andreas Hansson
5a9a743cfc MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
2012-02-13 06:43:09 -05:00
Ali Saidi
0a26883296 configs: More fixes for the memory system updates 2012-02-01 09:48:28 -08:00
Gabe Black
e88165a431 Merge with main repository. 2012-01-30 21:07:57 -08:00
Andreas Hansson
ade53def92 Ruby: Connect system port in Ruby network test
This patch moves the connection of the system port to create_system in
Ruby.py. Thereby it allows the failing Ruby test (and other Ruby
systems) to run again.
2012-01-30 09:37:06 -05:00
Gabe Black
39f314cc15 Yet another merge with the main repository.
--HG--
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simout => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
2012-01-29 03:27:15 -08:00
Nilay Vaish
ce336fae6a Config: Enable O3 CPU and Ruby in FS mode 2012-01-28 19:33:37 -06:00
Gabe Black
d7f71bf424 SE/FS: Get rid of FULL_SYSTEM in the configs directory 2012-01-28 07:24:50 -08:00
Gabe Black
ec20ee2f7c SE/FS: Make SE vs. FS mode a runtime parameter. 2012-01-28 07:24:34 -08:00
Andreas Hansson
53c130bf2f MEM: Fix fs.py by specifying the range size rather than end
This patch fixes the currently broken fs.py by specifying the size of
the bridge range rather than the end address. This effectively
subtracts one when determining the address range for the IO bridge
(from IO bus to membus), and thus avoids the overlapping ranges.
2012-01-25 12:44:43 -05:00
Nilay Vaish
24c2300998 Config: Enable using O3 CPU and Ruby in SE mode 2012-01-23 11:33:52 -06:00
Andreas Hansson
2208ea049f MEM: Make the bus bridge unidirectional and fixed address range
This patch makes the bus bridge uni-directional and specialises the
bus ports to be a master port and a slave port. This greatly
simplifies the assumptions on both sides as either port only has to
deal with requests or responses. The following patches introduce the
notion of master and slave ports, and would not be possible without
this split of responsibilities.

In making the bridge unidirectional, the address range mechanism of
the bridge is also changed. For the cases where communication is
taking place both ways, an additional bridge is needed. This causes
issues with the existing mechanism, as the busses cannot determine
when to stop iterating the address updates from the two bridges. To
avoid this issue, and also greatly simplify the specification, the
bridge now has a fixed set of address ranges, specified at creation
time.
2012-01-17 12:55:09 -06:00
Andreas Hansson
f85286b3de MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort      > PortProxy
TranslatingPort     > SETranslatingPortProxy
VirtualPort         > FSTranslatingPortProxy

--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17 12:55:08 -06:00
Ali Saidi
bcb71963eb ARM: Add support for running multiple systems 2012-01-09 18:08:20 -06:00
Ali Saidi
80a6907927 ARM: Add support for initparam m5 op 2012-01-09 18:08:20 -06:00
Nilay Vaish
a88ec980a4 Config: Add an option of type 'choice' for cpu type
This patch adds a new option for cpu type. This option is of type 'choice'
which is similar to a C++ enum, except that it takes string values as
possible choices. Following options are being removed -- detailed, timing,
inorder.

--HG--
extra : rebase_source : 58885e2e8a88b6af8e6ff884a5922059dbb1a6cb
2012-01-05 11:04:25 -06:00
Chris Emmons
9aea847f58 VNC: Add support for capturing frame buffer to file each time it is changed.
When a change in the frame buffer from the VNC server is detected, the new
frame is stored out to the m5out/frames_*/ directory.  Specifiy the flag
"--frame-capture" when running configs/example/fs.py to enable this behavior.

--HG--
extra : rebase_source : d4e08e83f4fa6ff79f3dc9c433fc1f0487e057fc
2011-12-01 00:15:26 -08:00
Nilay Vaish
9344480480 Ruby FS: Add the options for kernel and simulation script
These options were missing from the script ruby_fs.py. This patch adds these
options to the script.
2011-10-29 16:54:57 -05:00
Nilay Vaish
1b49c56679 Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
2011-08-02 00:10:08 -05:00
Nilay Vaish
d919930c3c se.py: Fixes the way ruby's options are added 2011-07-11 19:57:10 -05:00
Brad Beckmann
0b7b3766af config: removed unnecessary slashes
This patch removes unnecessary slashes from a couple of python scripts.
2011-06-30 19:54:02 -05:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
c86f849d5a Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
2011-06-30 19:49:26 -05:00
Gedare Bloom
3f1f16703d ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. 2011-06-17 12:20:10 -05:00
Steve Reinhardt
8a652f9871 config: tweak ruby configs to clean up hierarchy
Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings.  This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
   caches children of the sequencer rather than the controller; these
   config ciles are rewritten to assign the L1 caches to the
   controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
   causes the sequencers to be children of system.ruby, generating
   warnings because they are already parented to their respective
   controllers.  Changing this attribute to _cpu_ruby_ports fixes this
   because the leading underscore means this is now treated as a plain
   Python attribute rather than a child assignment. As a result, the
   configuration hierarchy changes such that, e.g.,
   system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
   internal link node rather than direct children of the topology.
   The topology classes are rewritten to assign the routers to the
   topology object first.
2011-05-23 14:29:23 -07:00
Tushar Krishna
de97d75965 configs: remove -p from ruby_network_test.py
A recent patch broke the ruby network tester by adding -p inside Options.py
which conflicts with the -p inside ruby_network_test.py.
Have removed -p from ruby_network_test.py
2011-05-21 00:00:54 -04:00
Tushar Krishna
1267ff5949 NetworkTest: added sim_cycles parameter to the network tester.
The network tester terminates after injecting for sim_cycles
(default=1000), instead of having to explicitly pass --maxticks from the
command line as before. If fixed_pkts is enabled, the tester only
injects maxpackets number of packets, else it keeps injecting till sim_cycles.
The tester also works with zero command line arguments now.
2011-05-07 17:43:30 -04:00
Somayeh Sardashti
c8bbfed937 This patch supports cache flushing in MOESI_hammer 2011-03-28 10:49:45 -05:00
Tushar Krishna
09c3a97a4c This patch adds the network tester for simple and garnet networks.
The tester code is in testers/networktest.
The tester can be invoked by configs/example/ruby_network_test.py.
A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.
2011-03-21 22:51:58 -04:00
Lisa Hsu
8957b09da1 configs: combine ruby_se.py and se.py to avoid all that code duplication 2011-03-19 21:13:04 -07:00
Lisa Hsu
0e75e3fd5f enable x86 workloads on se.py 2011-03-19 21:13:02 -07:00
Lisa Hsu
5103c6fe88 se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 and it will
set up a simulation that instantiates those three workloads.  Only caveat is that now,
for sanity checking, your -n X must match the number of benches in the list.
2011-03-19 21:12:59 -07:00
Ali Saidi
79dac89552 ARM: Clarifies creation of Linux and baremetal ARM systems.
makeArmSystem creates both bare-metal and Linux systems more cleanly.
machine_type was never optional though listed as an optional argument; a system
such as "RealView_PBX" must now be explicitly specified.  Now that it is a
required argument, the placement of the arguments has changed slightly
requiring some changes to calls that create ARM systems.
2011-02-23 15:10:48 -06:00
Brad Beckmann
ea9d4c3a97 memtest: due to contention increase, increased deadlock threshold 2011-02-08 15:53:33 -08:00
Brad Beckmann
6ebd7c390b config: fixed minor bug connecting dma devices to ruby 2011-02-08 15:52:44 -08:00
Gabe Black
f8fc0419c5 X86, Config: Move the setting of work count options to a separate function.
This way things that don't care about work count options and/or aren't called
by something that has those command line options set up doesn't have to build
a fake object to carry in inert values.
2011-02-07 01:22:15 -08:00
Brad Beckmann
dfa8cbeb06 m5: added work completed monitoring support 2011-02-06 22:14:19 -08:00
Brad Beckmann
17b4ef52bb ruby: x86 fs config support 2011-02-06 22:14:18 -08:00
Gabe Black
fd26707731 Mem,X86: Make the IO bridge pass APIC messages back towards the CPU. 2011-02-03 20:56:27 -08:00
Gabe Black
00f24ae92c Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
2011-02-03 20:23:00 -08:00
Gabe Black
a368fba7d4 Time: Add a mechanism to prevent M5 from running faster than real time.
M5 skips over any simulated time where it doesn't have any work to do. When
the simulation is active, the time skipped is short and the work done at any
point in time is relatively substantial. If the time between events is long
and/or the work to do at each event is small, it's possible for simulated time
to pass faster than real time. When running a benchmark that can be good
because it means the simulation will finish sooner in real time. When
interacting with the real world through, for instance, a serial terminal or
bridge to a real network, this can be a problem. Human or network response time
could be greatly exagerated from the perspective of the simulation and make
simulated events happen "too soon" from an external perspective.

This change adds the capability to force the simulation to run no faster than
real time. It does so by scheduling a periodic event that checks to see if
its simulated period is shorter than its real period. If it is, it stalls the
simulation until they're equal. This is called time syncing.

A future change could add pseudo instructions which turn time syncing on and
off from within the simulation. That would allow time syncing to be used for
the interactive parts of a session but then turned off when running a
benchmark using the m5 utility program inside a script. Time syncing would
probably not happen anyway while running a benchmark because there would be
plenty of work for M5 to do, but the event overhead could be avoided.
2011-01-19 11:48:00 -08:00
Ali Saidi
18555c1b56 Configs: Automatically choose the correct hello world binary. 2010-12-07 16:19:57 -08:00
Steve Reinhardt
6d9fc4175e memtest: scale associativity and mshrs according to config
Use the actual fanouts in the tree specification to scale
cache associativity and mshrs instead of dumb constants.
2010-08-25 21:55:42 -07:00
Brad Beckmann
d4318457d1 config: changed ruby config file names to be consistent 2010-08-24 14:08:23 -07:00
Brad Beckmann
0e610290d0 config: remove ruby's requirement on the timing cmd line param
Since ruby only works in timing mode, explicitly requiring the timing cmd line
param to be specified is not necessary.
2010-08-24 13:20:32 -07:00
Brad Beckmann
8572d8fd91 config: fixed ruby dma device connections 2010-08-24 13:20:31 -07:00
Brad Beckmann
e983ef9e8c testers: move testers to a new directory
This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.

--HG--
rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py
rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc
rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh
rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc
rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh
rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc
rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh
rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py
rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript
rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc
rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh
rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py
rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript
rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc
rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh
rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc
rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh
rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc
rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh
rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc
rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh
rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py
rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-24 12:07:22 -07:00
Ali Saidi
330fada1aa ARM: Add configuration for Linux/Full System 2010-08-23 11:18:40 -05:00
Brad Beckmann
6a4f99899b ruby: Resurrected Ruby's deterministic tests
Added the request series and invalidate deterministic tests as new cpu models
and removed the no longer needed ruby tests

--HG--
rename : configs/example/rubytest.py => configs/example/determ_test.py
rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/DirectedGenerator.cc
rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/DirectedGenerator.hh
rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/InvalidateGenerator.cc
rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/InvalidateGenerator.hh
rename : src/cpu/rubytest/RubyTester.cc => src/cpu/directedtest/RubyDirectedTester.cc
rename : src/cpu/rubytest/RubyTester.hh => src/cpu/directedtest/RubyDirectedTester.hh
rename : src/mem/ruby/tester/DetermGETXGenerator.cc => src/cpu/directedtest/SeriesRequestGenerator.cc
rename : src/mem/ruby/tester/DetermGETXGenerator.hh => src/cpu/directedtest/SeriesRequestGenerator.hh
2010-08-20 11:46:13 -07:00
Brad Beckmann
29c45ccd23 ruby: Reduced ruby latencies
The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system.  Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks.  The result was many cpus were idle for large periods of time.

These changes fix the latency mismatch.
2010-08-20 11:46:12 -07:00
Brad Beckmann
808701a10c memtest: Memtester support for DMA
This patch adds DMA testing to the Memtester and is inherits many changes from
Polina's old tester_dma_extension patch.  Since Ruby does not work in atomic
mode, the atomic mode options are removed.
2010-08-20 11:46:12 -07:00
Brad Beckmann
10e25cb1d0 config: Improve ruby simobject names
This patch attaches ruby objects to the system before the topology is
created so that their simobject names read their meaningful variable
names instead of their topology name.
2010-08-20 11:46:11 -07:00
Brad Beckmann
5c801090a3 config: reorganized how ruby specifies command-line options 2010-08-20 11:44:09 -07:00
Steve Reinhardt
1fbe466345 sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once.  The C++ Root object already panics if more than one is
created.  This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists).  It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone.  Users who use
configs/common/Simulate.py should not notice.
2010-08-17 05:06:22 -07:00
Brad Beckmann
c67bddc84a ruby: removed ruby.config from configs/example 2010-03-21 21:22:20 -07:00
Brad Beckmann
d8e1e5abd0 ruby: fixed how ruby_fs creates phsyical memory
Now ruby_fs creates physical memory of the right size.
2010-03-21 21:22:20 -07:00
Gabe Black
b1cbd7841a Config: Fix fs.py's call to CacheConfig.config_cache. 2010-02-27 18:52:57 -08:00
Lisa Hsu
a70f70ccbf configs: pull out cache configuration code from se.py and fs.py.
Most of these frontend configurations share cache configuration code, pull it out so that
changes to caches don't have to require changing multiple config files.
2010-02-25 10:13:40 -08:00
Lisa Hsu
1d3228481f cache: Make caches sharing aware and add occupancy stats.
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).
2010-02-23 09:34:22 -08:00
Brad Beckmann
057f5898ca ruby: ruby_se.py updated to new config system 2010-01-29 20:29:33 -08:00
Brad Beckmann
26cce73e97 ruby: memtest-ruby updated to the new config system 2010-01-29 20:29:33 -08:00
Brad Beckmann
134cc3d48d ruby: convert to M5 MemorySize
Converted both ruby caches and directory memory to use the M5 MemorySize python
type.
2010-01-29 20:29:23 -08:00
Brad Beckmann
45230a4f6b ruby: added the GEMS ruby tester 2010-01-29 20:29:23 -08:00
Brad Beckmann
ce2d13195b ruby: FS support using the new configuration system 2010-01-29 20:29:21 -08:00
Brad Beckmann
dc758641c9 ruby: reorganized ruby python configuration
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester).  This
code works for memory tester, but have not tested fs mode.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2c9ca672df ruby: Memory Controller Profiler with new config system
This patch includes a rather substantial change to the memory controller
profiler in order to work with the new configuration system.  Most
noteably, the mem_cntrl_profiler no longer uses a string map, but instead
a vector.  Eventually this support should be removed from the main
profiler and go into a separate object.  Each memory controller should have
a pointer to that new mem_cntrl profile object.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2a0555470c ruby: Converted MOESI_hammer dma cntrl to new config system 2010-01-29 20:29:19 -08:00
Brad Beckmann
3b290a35ac ruby: Added the cache profiler to the new config system 2010-01-29 20:29:19 -08:00
Brad Beckmann
12daaed84a ruby: Added clock to ruby system
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
ed81489954 ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system.  Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects.  This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
42bebab779 ruby: connects sm queues to the network 2010-01-29 20:29:18 -08:00
Steve Reinhardt
a8ea70dac6 ruby: Calculate system total memory capacity in Python
rather than in RubySystem object.
2010-01-29 20:29:18 -08:00
Steve Reinhardt
0b54f1db8e ruby: Add support for generating topologies in Python. 2010-01-29 20:29:17 -08:00
Steve Reinhardt
98c94cfe3c ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
2010-01-29 20:29:17 -08:00
Brad Beckmann
c6182199c5 m5: improvements to the ruby_fs.py file 2009-11-18 16:34:32 -08:00
Brad Beckmann
90d6e2652f ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of ports
per core.  CPUs have two ports: icache + dcache.  MemTester has one port.
2009-11-18 13:55:58 -08:00