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Config: Remove setMipsOptions

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As status matrix, MIPS fs does not work. Hence, these options are not
required. Secondly, the function is setting param values for a CPU class.
This seems strange, should probably be done in a different way.
This commit is contained in:
Nilay Vaish 2012-06-07 08:05:30 -05:00
parent 78a72d6972
commit 51c23e601e
2 changed files with 0 additions and 73 deletions
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70
configs/common/FSConfig.py
View file

@ -559,73 +559,3 @@ def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
self.etherlink.dump = Parent.etherdump
return self
def setMipsOptions(TestCPUClass):
#CP0 Configuration
TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
TestCPUClass.CoreParams.CP0_PRId_Revision = 0
#CP0 Interrupt Control
TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
# Config Register
#TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
#TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
#TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
#Config 1 Register
TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
# ***VERY IMPORTANT***
# Remember to modify CP0_Config1 according to cache specs
# Examine file ../common/Cache.py
TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
#Config 2 Register
TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
#Config 3 Register
TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
#SRS Ctl - HSS
TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
#TestCPUClass.CoreParams.tlb = TLB()
#TestCPUClass.CoreParams.UnifiedTLB = 1

3
configs/example/fs.py
View file

@ -145,9 +145,6 @@ for i in xrange(np):
CacheConfig.config_cache(options, test_sys)
if buildEnv['TARGET_ISA'] == 'mips':
setMipsOptions(TestCPUClass)
if len(bm) == 2:
if buildEnv['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])