Config: corrects the way Ruby attaches to the DMA ports
With recent changes to the memory system, a port cannot be assigned a peer port twice. While making use of the Ruby memory system in FS mode, DMA ports were assigned peer twice, once for the classic memory system and once for the Ruby memory system. This patch removes this double assignment of peer ports.
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f1a6090613
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4f4a710457
12 changed files with 36 additions and 55 deletions
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@ -134,16 +134,14 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
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self.tsunami.attachIO(self.piobus)
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self.tsunami.ide.pio = self.piobus.master
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self.tsunami.ide.config = self.piobus.master
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self.tsunami.ide.dma = self.piobus.slave
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self.tsunami.ethernet.pio = self.piobus.master
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self.tsunami.ethernet.config = self.piobus.master
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self.tsunami.ethernet.dma = self.piobus.slave
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#
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# Store the dma devices for later connection to dma ruby ports.
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# Append an underscore to dma_devices to avoid the SimObjectVector check.
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#
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self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
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self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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@ -408,8 +406,10 @@ def connectX86RubySystem(x86_sys):
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# the piobus a direct connection to physical memory
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#
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x86_sys.piobus.master = x86_sys.physmem.port
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x86_sys.pc.attachIO(x86_sys.piobus)
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# add the ide to the list of dma devices that later need to attach to
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# dma controllers
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x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
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x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
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def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
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@ -432,9 +432,6 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
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# Create and connect the busses required by each memory system
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if Ruby:
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connectX86RubySystem(self)
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# add the ide to the list of dma devices that later need to attach to
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# dma controllers
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self._dma_devices = [self.pc.south_bridge.ide]
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else:
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connectX86ClassicSystem(self, numCPUs)
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@ -96,7 +96,7 @@ if options.script is not None:
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system.readfile = options.script
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
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Ruby.create_system(options, system, system.piobus, system._dma_devices)
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Ruby.create_system(options, system, system.piobus, system._dma_ports)
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for (i, cpu) in enumerate(system.cpu):
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#
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@ -115,13 +115,17 @@ if options.num_dmas > 0:
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percent_functional = 0,
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percent_uncacheable = 0,
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progress_interval = options.progress,
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warn_on_failure = options.warn_on_failure) \
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suppress_func_warnings =
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not options.suppress_func_warnings) \
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for i in xrange(options.num_dmas) ]
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system.dma_devices = dmas
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else:
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dmas = []
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Ruby.create_system(options, system, dma_devices = dmas)
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dma_ports = []
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for (i, dma) in enumerate(dmas):
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dma_ports.append(dma.test)
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Ruby.create_system(options, system, dma_ports = dma_ports)
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#
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# The tester is most effective when randomization is turned on and
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@ -47,7 +47,7 @@ class L2Cache(RubyCache):
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def define_options(parser):
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return
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def create_system(options, system, piobus, dma_devices, ruby_system):
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def create_system(options, system, piobus, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
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panic("This script requires the MESI_CMP_directory protocol to be built.")
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@ -162,7 +162,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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cntrl_count += 1
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for i, dma_device in enumerate(dma_devices):
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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@ -175,12 +175,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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ruby_system = ruby_system)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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if dma_device.type == 'MemTest':
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
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else:
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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cntrl_count += 1
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all_cntrls = l1_cntrl_nodes + \
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@ -41,7 +41,7 @@ class Cache(RubyCache):
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def define_options(parser):
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return
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def create_system(options, system, piobus, dma_devices, ruby_system):
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def create_system(options, system, piobus, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'MI_example':
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panic("This script requires the MI_example protocol to be built.")
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@ -135,7 +135,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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cntrl_count += 1
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for i, dma_device in enumerate(dma_devices):
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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@ -148,13 +148,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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ruby_system = ruby_system)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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if dma_device.type == 'MemTest':
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
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else:
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
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dma_cntrl.dma_sequencer.slave = dma_device.dma
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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cntrl_count += 1
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all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
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@ -47,7 +47,7 @@ class L2Cache(RubyCache):
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def define_options(parser):
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return
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def create_system(options, system, piobus, dma_devices, ruby_system):
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def create_system(options, system, piobus, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
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panic("This script requires the MOESI_CMP_directory protocol to be built.")
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@ -159,7 +159,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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cntrl_count += 1
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for i, dma_device in enumerate(dma_devices):
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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@ -172,12 +172,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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ruby_system = ruby_system)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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if dma_device.type == 'MemTest':
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
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else:
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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cntrl_count += 1
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all_cntrls = l1_cntrl_nodes + \
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@ -54,7 +54,7 @@ def define_options(parser):
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parser.add_option("--allow-atomic-migration", action="store_true",
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help="allow migratory sharing for atomic only accessed blocks")
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def create_system(options, system, piobus, dma_devices, ruby_system):
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def create_system(options, system, piobus, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
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panic("This script requires the MOESI_CMP_token protocol to be built.")
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@ -183,7 +183,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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cntrl_count += 1
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for i, dma_device in enumerate(dma_devices):
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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@ -196,12 +196,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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ruby_system = ruby_system)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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if dma_device.type == 'MemTest':
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
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else:
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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cntrl_count += 1
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all_cntrls = l1_cntrl_nodes + \
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@ -58,7 +58,7 @@ def define_options(parser):
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parser.add_option("--dir-on", action="store_true",
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help="Hammer: enable Full-bit Directory")
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def create_system(options, system, piobus, dma_devices, ruby_system):
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def create_system(options, system, piobus, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'MOESI_hammer':
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panic("This script requires the MOESI_hammer protocol to be built.")
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@ -195,7 +195,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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cntrl_count += 1
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for i, dma_device in enumerate(dma_devices):
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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@ -208,10 +208,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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ruby_system = ruby_system)
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exec("system.dma_cntrl%d = dma_cntrl" % i)
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if dma_device.type == 'MemTest':
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
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else:
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
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exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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if options.recycle_latency:
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@ -41,7 +41,7 @@ class Cache(RubyCache):
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def define_options(parser):
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return
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def create_system(options, system, piobus, dma_devices, ruby_system):
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def create_system(options, system, piobus, dma_ports, ruby_system):
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if buildEnv['PROTOCOL'] != 'Network_test':
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panic("This script requires the Network_test protocol to be built.")
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@ -52,7 +52,7 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
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# The Garnet tester protocol does not support fs nor dma
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#
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assert(piobus == None)
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assert(dma_devices == [])
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assert(dma_ports == [])
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#
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# The ruby network creation expects the list of nodes in the system to be
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@ -76,7 +76,7 @@ def define_options(parser):
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exec "import %s" % protocol
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eval("%s.define_options(parser)" % protocol)
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def create_system(options, system, piobus = None, dma_devices = []):
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def create_system(options, system, piobus = None, dma_ports = []):
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system.ruby = RubySystem(clock = options.clock,
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stats_filename = options.ruby_stats,
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@ -87,8 +87,7 @@ def create_system(options, system, piobus = None, dma_devices = []):
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exec "import %s" % protocol
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try:
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(cpu_sequencers, dir_cntrls, all_cntrls) = \
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eval("%s.create_system(options, system, piobus, \
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dma_devices, ruby)" \
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eval("%s.create_system(options, system, piobus, dma_ports, ruby)"
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% protocol)
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except:
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print "Error: could not create sytem for ruby protocol %s" % protocol
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@ -69,8 +69,8 @@ class Pc(Platform):
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# A device to catch accesses to the non-existant floppy controller.
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fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
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def attachIO(self, bus):
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self.south_bridge.attachIO(bus)
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def attachIO(self, bus, dma_ports = []):
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self.south_bridge.attachIO(bus, dma_ports)
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self.i_dont_exist.pio = bus.master
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self.behind_pci.pio = bus.master
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self.com_1.pio = bus.master
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@ -85,7 +85,7 @@ class SouthBridge(SimObject):
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ide.InterruptLine = 14
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ide.InterruptPin = 1
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def attachIO(self, bus):
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def attachIO(self, bus, dma_ports):
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# Route interupt signals
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self.int_lines = \
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[X86IntLine(source=self.pic1.output, sink=self.io_apic.pin(0)),
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@ -106,7 +106,8 @@ class SouthBridge(SimObject):
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self.dma1.pio = bus.master
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self.ide.pio = bus.master
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self.ide.config = bus.master
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self.ide.dma = bus.slave
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if dma_ports.count(self.ide.dma) == 0:
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self.ide.dma = bus.slave
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self.keyboard.pio = bus.master
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self.pic1.pio = bus.master
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self.pic2.pio = bus.master
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