Commit graph

5150 commits

Author SHA1 Message Date
Ali Saidi
94ce971278 IO: Fix bug in DMA Device where receiving a snoop on DMA port would cause a panic.
--HG--
extra : rebase_source : 8152d4fa7d7354c9f150a450ae0710e95141ba4b
2011-12-15 00:09:46 -05:00
Nathan Binkert
6ef9691035 gcc: fix unused variable warnings from GCC 4.6.1
--HG--
extra : rebase_source : f9e22de341493a25ac6106c16ac35c61c128a080
2011-12-13 11:49:27 -08:00
Ali Saidi
9b52717a92 Trace: FIx issue with creation of trace file with output dir overhaul.
--HG--
extra : rebase_source : c1ab57ea8805703d97cdee4f32410821a2d2a9db
2011-12-01 17:36:22 -08:00
Brad Beckmann
8daad28a90 MOESI_hammer: fixed L2 to L1 infinite stalls and deadlock
--HG--
extra : rebase_source : 90f217f28e195a8cee5d64b25c913b452d818676
2011-12-01 10:08:52 -08:00
Brad Beckmann
cecbdb6d79 physmem: Improved fatal message for size mismatch
--HG--
extra : rebase_source : 16da1c63263f8fd6fef9a842c577343cd6246a35
2011-12-01 10:08:52 -08:00
Chris Emmons
9aea847f58 VNC: Add support for capturing frame buffer to file each time it is changed.
When a change in the frame buffer from the VNC server is detected, the new
frame is stored out to the m5out/frames_*/ directory.  Specifiy the flag
"--frame-capture" when running configs/example/fs.py to enable this behavior.

--HG--
extra : rebase_source : d4e08e83f4fa6ff79f3dc9c433fc1f0487e057fc
2011-12-01 00:15:26 -08:00
Chris Emmons
5bde1d359f Output: Add hierarchical output support and cleanup existing codebase.
--HG--
extra : rebase_source : 3301137733cdf5fdb471d56ef7990e7a3a865442
2011-12-01 00:15:25 -08:00
Ali Saidi
5d50ee420d SE: Don't warn when not extending stack as it's too noisy with O3.
--HG--
extra : rebase_source : e56d1551d42d46b5f357cd63f9891715b664f6fc
2011-12-01 00:15:25 -08:00
Chander Sudanthi
61c14da751 O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.

--HG--
extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-12-01 00:15:22 -08:00
Mitchell Hayenga
fa753c1454 Device: Make changes necessary to support a coherent page walker cache.
Adds the flag 'recvSnoops' which enables pagewalkers using DmaPorts,
to properly configure snoops.

--HG--
extra : rebase_source : 64207bef62c3268ddff2236ee4adae873812325f
2011-12-01 00:15:22 -08:00
Ali Saidi
946f7f0f55 ARM: Add support for having a TLB cache.
--HG--
extra : rebase_source : 7a5780ab74d7c294682738c7ccb3ce8d56c6fd63
2011-12-01 00:15:22 -08:00
Ali Saidi
5901c5223f ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .
Squashes the subsequent instructions in O3 pipe after the service call, so that
they see the effect of the system call when re-executed. This isn't really an issue
with FS mode, but can show up in SE mode.

--HG--
extra : rebase_source : 613a69fe1d9834261e25a8cd340aa6b47578e1fe
2011-12-01 00:15:22 -08:00
Ali Saidi
1444103998 O3: Add stat that counts how many cycles the O3 cpu was quiesced.
--HG--
extra : rebase_source : 043b9307eef3c5b87f8e6370765641e016ed1fa7
2011-12-01 00:15:22 -08:00
Gabe Black
93fb460fad X86: Fix a bad segmentation check for the stack segment.
--HG--
extra : rebase_source : 755f4f6eae52f88ed516a1f1ac9e2565725d89c1
2011-12-01 00:17:14 -05:00
Gabe Black
87b66c9ae3 SPARC: Minor style fix.
I forgot to fix this as well per Ali's feedback.

--HG--
extra : rebase_source : e70d031cb5f91e2212a1a73ea1769bf0549b826c
2011-11-28 04:35:55 -05:00
Andreas Hansson
64ccfecf95 SPARC: Fixing a minor copy-paste bug using the wrong variable
There was a bug in the mm_disk implementation where a copy paste error
resulted in the d32 variable not being initialised (as it incorrectly
was used instead of d16), and gcc 4.5 complaining.

--HG--
extra : rebase_source : 9515e87b188b9eac189da8034cb13c3bf7d9e20b
2011-11-28 04:34:18 -05:00
Gabe Black
e7d0c999a1 SPARC: Isolate FP operations enough to prevent code/rounding mode reordering.
--HG--
extra : rebase_source : ee79ab89c5a707c1294f38abb84c60f8ef64196c
2011-11-27 22:00:58 -05:00
Gabe Black
13552dc304 Compiler: Add an M5_NO_INLINE define.
--HG--
extra : rebase_source : 1f5e8b7bb6b0a8bb4f951b6d7189964d96ed5df1
2011-11-27 22:00:57 -05:00
Tushar Krishna
88e91cafc6 Topology: bug fix in external link initialization
--HG--
extra : rebase_source : c226cd1e5e5ed4d4c64fa9427de4905bd8335e34
2011-11-23 16:34:13 -05:00
Tushar Krishna
eff430a972 Remove standard_1level_CMP-protocol.sm include statement from Network
--HG--
extra : rebase_source : 51a2dd4bb643e3dc5b0218a6190cf5c1989f9691
2011-11-22 20:11:18 -05:00
Gabe Black
49a2d54e1a X86: Fix the constant detecting three byte opcodes in the predecoder.
--HG--
extra : rebase_source : b64c3d2348cb73177024695fb6e205d51bf1cda9
2011-11-20 05:10:05 -08:00
Gabe Black
85424bef19 SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
Gabe Black
de21bb93ea SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 2011-11-18 01:33:28 -08:00
Nilay Vaish
f3b4d10a05 Ruby: Process packet instead of RubyRequest in Sequencer
This patch changes the implementation of Ruby's recvTiming() function so
that it pushes a packet in to the Sequencer instead of a RubyRequest. This
requires changes in the Sequencer's makeRequest() and issueRequest()
functions, as they also need to operate on a Packet instead of RubyRequest.
2011-11-14 17:44:35 -06:00
Gabe Black
ec32d85f9d Power: Add a stubbed out stacktrace.cc 2011-11-13 12:40:15 -08:00
Gabe Black
ff4ba82610 POWER: Add a stub implementation of initCPU. 2011-11-13 12:40:15 -08:00
Gabe Black
1a8f1809fa Power: Add a stub kernel_stats.hh. 2011-11-13 12:40:15 -08:00
Gabe Black
5fcd11eaa5 SE/FS: Get rid of FULL_SYSTEM in dev. 2011-11-13 02:05:32 -08:00
Gabe Black
362a53e572 SE/FS: Get rid of FULL_SYSTEM in kern. 2011-11-13 02:05:32 -08:00
Gabe Black
6d68887c87 Power: Implement a stub for getArgument. 2011-11-13 02:05:27 -08:00
Gabe Black
2ee59cee1b GCC: Guard some gcc flags so they're used when available and needed. 2011-11-09 21:48:28 -08:00
Gabe Black
71c4534ce9 SE/FS: Get rid of FULL_SYSTEM in mem. 2011-11-07 01:13:43 -08:00
Gabe Black
812277ac6a SE/FS: Remove FULL_SYSTEM from swig. 2011-11-07 01:06:54 -08:00
Tushar Krishna
ac993964a9 GARNET: adding a fault model for resilient on-chip network research.
This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.
2011-11-04 18:40:22 -04:00
Nilay Vaish
5ff6e05ffd MESI Protocol: Add functions for profiling misses 2011-11-04 11:26:12 -05:00
Nilay Vaish
582ea4d543 x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.
2011-11-03 22:52:21 -05:00
Nilay Vaish
fb5c095cd5 Protocol: Remove standard one and two level files 2011-11-03 22:52:02 -05:00
Nilay Vaish
a547cf34b9 Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.
2011-11-03 22:46:45 -05:00
Gabe Black
8b4a3f4070 SE/FS: Get rid of FULL_SYSTEM in sim. 2011-11-02 02:11:14 -07:00
Gabe Black
fb15604f2c SE/FS: Get FULL_SYSTEM out of base/remote_gdb.cc. 2011-11-02 01:27:45 -07:00
Gabe Black
239b33e016 SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. 2011-11-02 01:25:15 -07:00
Gabe Black
7b417d4188 SE/FS: Get rid of the last use of FULL_SYSTEM in x86. 2011-11-01 04:01:15 -07:00
Gabe Black
b6da5e2086 SE/FS: Get rid of uses of FULL_SYSTEM in Alpha. 2011-11-01 04:01:14 -07:00
Gabe Black
1268e0df1f SE/FS: Expose the same methods on the CPUs in SE and FS modes. 2011-11-01 04:01:13 -07:00
Gabe Black
eeb85a8575 SE/FS: Remove the last uses of FULL_SYSTEM from SPARC. 2011-10-31 02:58:24 -07:00
Gabe Black
8ad2b8c559 SE/FS: Make the functions available from the TC consistent between SE and FS. 2011-10-31 02:58:22 -07:00
Gabe Black
d735abe5da GCC: Get everything working with gcc 4.6.1.
And by "everything" I mean all the quick regressions.
2011-10-31 01:09:44 -07:00
Gabe Black
ef097eb69c SE/FS: Build the solaris object in both SE and FS. 2011-10-30 18:52:30 -07:00
Gabe Black
248033f31e SE/FS: Get rid of FULL_SYSTEM in MIPS. 2011-10-30 18:39:38 -07:00
Gabe Black
8009b53c41 SE/FS: Compile in system events in SE mode. 2011-10-30 17:38:11 -07:00
Gabe Black
37a437893e System: Push boot_cpu_frequency down into the subclasses that actually use it.
This parameter depends on a number of coincidences to work properly. First,
there must be an array assigned to system called "cpu" even though there's no
parameter called that. Second, the items in the "cpu" array have to have a
"clock" parameter which has a "frequency" member. This is true of the normal
CPUs, but isn't true of the memory tester CPUs. This happened to work before
because the memory tester CPUs were only used in SE mode where this parameter
was being excluded. Since everything is being pulled into a common binary,
this won't work any more. Since the boot_cpu_frequency parameter is only used
by Alpha's Linux System object (and Mips's through copy and paste), the
definition of that parameter is moved down to those objects specifically.
2011-10-30 17:38:09 -07:00
Nilay Vaish
49c64731fa Python: Remove import for random 2011-10-30 15:55:32 -05:00
Gabe Black
b144f05b53 SE/FS: Remove the last references to FULL_SYSTEM from POWER. 2011-10-30 03:55:24 -07:00
Gabe Black
6dc3cedc4e X86: Build the same files in SE and FS. 2011-10-30 03:06:40 -07:00
Gabe Black
ca77249b0c SE/FS: Build syscall_emul.cc in FS mode. 2011-10-30 03:06:37 -07:00
Gabe Black
0c81db77f2 SE/FS: Make the system object more consistent between SE and FS. 2011-10-30 02:30:55 -07:00
Gabe Black
1d8822a364 X86: Get rid of more uses of FULL_SYSTEM. 2011-10-30 00:33:02 -07:00
Gabe Black
facb40f3ff SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. 2011-10-30 00:33:02 -07:00
Gabe Black
5b433568f0 SE/FS: Build the base process class in FS. 2011-10-30 00:32:54 -07:00
Nilay Vaish
706323fa21 Merged with recent changes. 2011-10-28 13:04:33 -05:00
Nilay Vaish
cbaebb3b5e Ruby: Reorganize mapping of components
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for
mapping MachineType to GenericMachineType. These '#define's are being
eliminated and the code will now be generated by SLICC instead. Also
are being eliminated some of the unused functions from
RubySlicc_ComponentMapping.sm.
2011-10-28 13:00:35 -05:00
Steve Reinhardt
6f9d294e86 SE: move page allocation from PageTable to Process
PageTable supported an allocate() call that called back
through the Process to allocate memory, but did not have
a method to map addresses without allocating new pages.
It makes more sense for Process to do the allocation, so
this method was renamed allocateMem() and moved to Process,
and uses a new map() call on PageTable.

The remaining uses of the process pointer in PageTable
were only to get the name and the PID, so by passing these
in directly in the constructor, we can make PageTable
completely independent of Process.
2011-10-22 22:30:08 -07:00
Steve Reinhardt
4d5f2c28a8 syscall_emul: implement MAP_FIXED option to mmap() 2011-10-22 22:30:07 -07:00
Steve Reinhardt
38aef4c4c7 dev: clean up PioDevice and DmaDevive getPort() methods.
Make DmaDevice::getPort() call PioDevice::getPort() instead
of just copying and pasting the code.

Also move definitions from .hh to .cc file.
2011-10-20 13:11:56 -07:00
Steve Reinhardt
7b500f56ca SimObject: add export_method* hooks to export C++ methods to Python
Replace the (broken as of previous changeset) swig_objdecl() method
that allowed/forced you to substitute a whole new C++ struct
definition for SWIG to wrap with a set of export_method* hooks
that let you just declare a set of C++ methods (or other declarations)
that get inserted in the auto-generated struct.

Restore the System get/setMemoryMode methods, and use this mechanism
to specialize SimObject as well, eliminating teh need for sim_object.i.
Needed bits of sim_object.i are moved to the new pyobject.i.
Also sucked a little SimObject specialization into cxx_param_decl()
allowing us to get rid of src/sim/sim_object_params.hh.  Now the
generation and wrapping of the base SimObject param struct is more
in line with how derived objects are handled.

--HG--
rename : src/python/swig/sim_object.i => src/python/swig/pyobject.i
2011-10-20 13:09:10 -07:00
Steve Reinhardt
45d14e02c4 scons/swig: refactor some of the scons/SWIG code
- Move the random bits of SWIG code generation out of src/SConscript
  file and into methods on the objects being wrapped.
- Cleaned up some variable naming and added some comments to make
  the process a little clearer.
- Did a little generated file/module renaming:
   - vptype_Foo now Foo_vector
   - init_Foo is now Foo_init
  This makes it easier to see all the Foo-related files in a
  sorted directory listing.
- Made cxx_predecls and swig_predecls normal SimObject classmethods.
- Got rid of swig_objdecls hook, even though this breaks the System
  objects get/setMemoryMode method exports.  Will be fixing this in
  a future changeset.
2011-10-20 13:08:49 -07:00
Nathan Binkert
d8cc8d3ab8 scons: fix building of shared objects 2011-10-17 17:06:40 -07:00
Gabe Black
ca36c01f7e SE/FS: Make some system funcs available in SE and FS. 2011-10-16 05:06:40 -07:00
Gabe Black
464c485d0c SE/FS: Include getMemPort in FS. 2011-10-16 05:06:40 -07:00
Gabe Black
bcf664e5f9 SE/FS: Turn on the page table class in FS. 2011-10-16 05:06:40 -07:00
Gabe Black
6ba3ebae43 SE/FS: Build in the tport in FS mode. 2011-10-16 05:06:40 -07:00
Gabe Black
3595b0c5a1 SE/FS: Build/expose vport in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
79ba4b6595 SPARC: Build vtophys into SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
5ee3f586bf Power: Add a stub implementation for vtophys in SE and FS. 2011-10-16 05:06:39 -07:00
Gabe Black
baae510b56 MIPS: Build vtophys in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
1eb459a79e ARM: Build vtophys in SE mode. 2011-10-16 05:06:39 -07:00
Gabe Black
b2af015b97 ARM: Turn on the page table walker on ARM in SE mode. 2011-10-16 05:06:38 -07:00
Gabe Black
dd8fed7387 Alpha: Turn on vtophys in SE mode. 2011-10-16 02:59:53 -07:00
Gabe Black
e8e9f97312 CPU: Make physPort and getPhysPort available in SE mode. 2011-10-16 02:59:53 -07:00
Gabe Black
85ca77d114 X86: Build vtophys in SE mode. 2011-10-13 02:26:21 -07:00
Gabe Black
8adc6781bf X86: Turn on the page table walker in SE mode. 2011-10-13 02:22:23 -07:00
Gabe Black
4b2e5ebead SPARC: Remove the last checks of FULL_SYSTEM. 2011-10-13 01:37:19 -07:00
Gabe Black
6b5ede5e39 SPARC: Narrow the scope of #if FULL_SYSTEM in SPARC's faults. 2011-10-13 01:11:00 -07:00
Nilay Vaish
b61e34fab8 mc146818: Correctly serialize tickEvent
'tickEvent' was not being serialized as in its place 'event' was being used.
This patch rectifies this error.
2011-10-10 17:01:33 -05:00
Gabe Black
afa7a34563 SPARC: Let the TLB have friends in FS mode. 2011-10-10 00:38:57 -07:00
Gabe Black
8eec565d0d SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC. 2011-10-10 00:31:51 -07:00
Gabe Black
5bab52d56d [mq]: sefssparcregfile.patch 2011-10-09 23:48:27 -07:00
Gabe Black
48b40cff65 Interrupts: Make the IO APIC go get the local APICs.
This is so they don't have to declare themselves to the IO APIC and don't have
to have a pointer to the platform object.
2011-10-09 04:44:02 -07:00
Gabe Black
f338d60930 SE/FS: Build the Interrupt objects in SE mode. 2011-10-09 00:15:50 -07:00
Gabe Black
bfec60ad3a Ports: Print the port name when a port is used but not attached to anything. 2011-10-08 23:24:32 -07:00
Gabe Black
d368344092 SE/FS: Put platform pointers in fewer objects.
Not all objects need a platform pointer, and having one creates a dependence
on their being a platform object. This change removes the platform pointer to
from the base device object and moves it into subclasses that actually need
it.
2011-10-04 02:26:03 -07:00
Gabe Black
e2dbe59f5d SE/FS: Remove System::platform and Platform::intrFrequency.
In order for a system object to work in SE mode and FS mode, it has to either
always require a platform object even in SE mode, or get rid of the
requirement all together. Making SE mode carry around unnecessary/unused bits
of FS seems less than ideal, so I decided to go with the second option. The
platform pointer in the System class was used for exactly one purpose, a path
for the Alpha Linux system object to get to the real time clock and read its
frequency so that it could short cut the loops_per_jiffy calculation. There
was also a copy and pasted implementation in MIPS, but since it was only there
because it was there in Alpha I still count that as one use.

This change reverses the mechanism that communicates the RTC frequency so that
the Tsunami platform object pushes it up to the AlphaSystem object. This is
slightly less specific than it could be because really only the
AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform
class was no longer necessary (and unimplemented on anything but Alpha) it was
eliminated.

After this change, a platform will need to have a system, but a system won't
have to have a platform.
2011-09-30 00:29:07 -07:00
Gabe Black
91dd72a99a X86: Remove FULL_SYSTEM from the x86 faults. 2011-09-30 00:28:40 -07:00
Gabe Black
51f7a66660 SE/FS: Build the devices in SE mode. 2011-09-30 00:28:33 -07:00
Gabe Black
35e20c7470 SE/FS: Use the new FullSystem constant where possible. 2011-09-30 00:27:16 -07:00
Gabe Black
4fcf8e9959 O3: Tidy up some DPRINTFs in the LSQ. 2011-09-27 00:25:26 -07:00
Gabe Black
44ed4849d4 Faults: Replace calls to genMachineCheckFault with M5PanicFault. 2011-09-27 00:24:43 -07:00
Gabe Black
2ed3eef9b0 Faults: Add in generic faults that work like panics, warns, etc.
These faults take varargs to their constructors which they print into a string
and pass to the M5DebugFault base class. They are basically faults wrapped
around panics, faults, warns, and warnonce-es so that they happen only at
commit.
2011-09-27 00:17:09 -07:00
Gabe Black
ea79850f90 Faults: Make the generic faults more consistent between SE and FS.
All of the classes will now be available in both modes, and only
GenericPageTableFault will continue to check the mode for conditional
compilation. It uses a process object to handle the fault in SE mode, and
for now those aren't available in FS mode.
2011-09-27 00:16:33 -07:00
Gabe Black
997cbe1c09 ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.
By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
2011-09-26 23:48:54 -07:00
Nilay Vaish
56bddab189 LSQ: Moved a couple of lines to enable O3 + Ruby
This patch makes O3 CPU work along with the Ruby memory model. Ruby
overwrites the senderState pointer with another pointer. The pointer
is restored only when Ruby gets done with the packet. LSQ makes use of
senderState just after sendTiming() returns. But the dynamic_cast returns
a NULL pointer since Ruby's senderState pointer is from a different class.
Storing the senderState pointer before calling sendTiming() does away with
the problem.
2011-09-26 12:18:32 -05:00
Gabe Black
16e0215d30 SE/FS: Define a const bool FullSystem which will equal FULL_SYSTEM.
This constant will have the same value as FULL_SYSTEM but will not be usable
by the preprocessor. It can be substituted into places where FULL_SYSTEM is
used in a C++ context and will make it easier to find which parts of the
simulator still use FULL_SYSTEM with the preprocessor using grep.
2011-09-26 02:09:04 -07:00
Gabe Black
7770239792 SCons: Add a comment I forgot to add in earlier.
This comment was supposed to be added to an earlier change as part of review
feedback, but I accidentally left it out when I pushed. Add it in now.
2011-09-24 17:03:18 -07:00
Gabe Black
9f26aaa7d7 SCons: Make the ISA parser a source for its output files like the comments say.
There was a change a while ago that refactored some scons stuff which got rid
of cpu_models.py but also accidentally got rid of the ISA parser as a source
for its target files. That meant that changes which affected the parser
wouldn't cause a rebuild unless they also changed one of the description
files. This change fixes that.
2011-09-24 16:59:11 -07:00
Gabe Black
40b6c9cb2e X86: Move the MSR lookup table out of the TLB and into its own file.
Translating MSR addresses into MSR register indices took a lot of space in the
TLB source and made looking around in that file awkward. This change moves
the lookup into its own file to get it out of the way. It also changes it from
a switch statement to a hash map which should hopefully be a little more
efficient.
2011-09-23 02:42:22 -07:00
Steve Reinhardt
84f0a1bd91 event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor.  I
forget exactly why, but this made life easier when implementing
multi-queue support.

Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.
2011-09-22 18:59:55 -07:00
Steve Reinhardt
ba79155d9d pseudo_inst: clean up workbegin/workend functions
Use exitSimLoop() function instead of explicitly scheduling
on mainEventQueue (which won't work once we go to multiple
event queues).  Also introduced a local params variable to
shorten a lot of expressions.
2011-09-22 18:59:54 -07:00
Steve Reinhardt
4a4bc2e18b params.py: enhance IpAddress param handling
Print IpAddress params in dot notation for readability.
Properly compare IpAddress objects (by value and not object identity).
Also fix up derived param classes (IpNetmask and IpWithPort)
similarly.
2011-09-22 18:58:14 -07:00
Gabe Black
9a38dc6194 MIPS: Final overhaul of MIPS faults to kill #if FULL_SYSTEM
This change is a significant reorganization of the MIPS fault code that gets
rid of duplication, fixes some bugs, doubtlessly introduces others, and adds
names for the exception code constants.
2011-09-19 06:17:21 -07:00
Gabe Black
4455fc484d MIPS, faults: Update how the PC is set. 2011-09-19 06:17:21 -07:00
Gabe Black
0d9ee17012 MIPS: Get rid of skipFaultInstruction and setRestartAddress.
Neither of these functions were used.
2011-09-19 06:17:21 -07:00
Gabe Black
5ea09771be MIPS: Use inheritance to consolidate class definitions. 2011-09-19 06:17:21 -07:00
Gabe Black
7d19ff170d MIPS: Always compile in setExceptionState, including in SE mode.
Also fix the newly exposed and preexisting compile errors. This code hasn't
been exposed in a while, and it's not up to date with the rest of gem5.
2011-09-19 06:17:21 -07:00
Gabe Black
48b6636d01 MIPS: Consolidate TLB related faults.
Pass in a bool to indicate if the fault is from a store instead of having two
different classes. The classes were also misleadingly named since loads are
also processed by the DTB but should return ITB faults since they aren't
stores. The TLB may be returning the wrong fault in this case, but I haven't
looked at it closely.
2011-09-19 06:17:20 -07:00
Gabe Black
efcded334c MIPS: Get rid of the unused "count" field in FaultVals. 2011-09-19 06:17:20 -07:00
Gabe Black
ffeab06378 MIPS: Move the genMachineCheckFault function near MachineCheckFault.
Since they're so closely linked, they should be next to each other in the
file.
2011-09-19 06:17:20 -07:00
Gabe Black
59d7fc6b26 MIPS: Consolidate the two AddressErrorFault variants. 2011-09-19 06:17:20 -07:00
Gabe Black
717d4ae930 Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.
These functions aren't called anywhere and are probably only theoretically
useful.
2011-09-19 06:17:20 -07:00
Gabe Black
110c59b414 MIPS: Get rid of cruft in the fault classes.
Get rid of Fault classes left over from when this file was copied from Alpha,
and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of
the old IntegerOverflowFault stub. The Integer version is what's actually in
the manual, but the Arithmetic version had the implementation.
2011-09-19 06:17:19 -07:00
Gabe Black
7e704c9f51 MIPS: Add constructors to the fault classes. 2011-09-19 06:17:19 -07:00
Gabe Black
27388c0fe0 MIPS: Use the CRTP to streamline the Fault class definitions.
CRTP stands for the curiously recurring template pattern.
2011-09-19 06:17:19 -07:00
Gabe Black
59a5605fff SPARC: Remove #if FULL_SYSTEMs from the ISA description. 2011-09-19 06:17:19 -07:00
Gabe Black
f21ae529fb MIPS: Get rid of #if style config checks in the ISA description. 2011-09-19 06:14:02 -07:00
Gabe Black
4ad36a4684 MIPS: Guard SystemCallFault::invoke consistently.
Make sure it's declared iff it's also defined.
2011-09-19 06:09:15 -07:00
Gabe Black
49967ed268 MIPS: Get rid of the unused (and partially defined) CacheError fault. 2011-09-19 05:53:54 -07:00
Gabe Black
3eca0a2bc9 Endianness: Make it easier to check the compiled in guest endianness.
It was technically possible but clumsy to determine what endianness a guest
was configured with using the state in byteswap.hh. This change makes that
information available more directly.

Also get rid of unused (and mildly redundant) ByteOrderDiffers constant.
2011-09-19 05:19:45 -07:00
Gabe Black
978e41eab0 Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.
The remaining ones are more complicated and may require adjustments in other
parts of the simulator.
2011-09-19 03:40:30 -07:00
Gabe Black
44659cb608 PseudoInst: Make all the pseudo insts available in SE and FS. 2011-09-19 03:39:58 -07:00
Gabe Black
7701c5b1ec X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.
The decoder now checks the value of FULL_SYSTEM in a switch statement to
decide whether to return a real syscall instruction or one that triggers
syscall emulation (or a panic in FS mode). The switch statement should devolve
into an if, and also should be optimized out since it's based on constant
input.
2011-09-19 02:53:37 -07:00
Gabe Black
10c2e37f60 Syscall: Make the syscall function available in both SE and FS modes.
In FS mode the syscall function will panic, but the interface will be
consistent and code which calls syscall can be compiled in. This will allow,
for instance, instructions that use syscall to be built unconditionally but
then not returned by the decoder.
2011-09-19 02:46:48 -07:00
Gabe Black
83aa47adca PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts. 2011-09-19 02:40:19 -07:00
Gabe Black
9eda6b1d88 Pseudoinst: Add an initParam pseudo inst function. 2011-09-18 23:26:39 -07:00
Ali Saidi
6caea472a9 IGbE: Clean up debug printing and proprly account for copied bytes.
Some DPRINTFs were printing uninitalized values because the DPRINTFs were
always being printed even when the features they were printing weren't
being used. This change moves the DPRINTFs into the appropriate if blocks
and initializes the state variables correctly.

There also is a case where the offset into the packet could be calculated
incorrectly during a DMA that is fixed.
2011-09-13 12:06:13 -05:00
Daniel Johnson
cbb23a1d3c ARM: update TLB to set request packet ASID field 2011-09-13 12:06:13 -05:00
Daniel Johnson
52d30813ca Mem: Allow ASID to be set after request is created. 2011-09-13 12:06:13 -05:00
Chander Sudanthi
7c479d7349 CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault.  This patch
enables accesses but prints out a warning, as the registers are not implemented.
2011-09-13 12:06:13 -05:00
Daniel Johnson
09a6e424ec ARM: Implement numcpus bits in L2CTLR register. 2011-09-13 12:06:13 -05:00
Ali Saidi
0c29a97ba9 Prefetch: Don't prefetch if address is in the write queue.
Check that we're not currently writing back an address the prefetcher is trying
to prefetch before issuing it. We previously checked the mshrQueue and the cache
itself, but forgot to check the writeBuffer. This fixes a memory corrucption
issue with an L2 prefetcher.
2011-09-13 12:06:13 -05:00
Ali Saidi
649c239cee LSQ: Only trigger a memory violation with a load/load if the value changes.
Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
2011-09-13 12:58:08 -04:00
Deyuan Guo
bb921b1459 MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.
So a mips-cross-gdb can connect with gem5(MIPS_SE), and do some remote
debugging.

Testing:

Build gem5 for MIPS_SE and make gem5 wait at beginning:
modify "rgdb_wait = -1" to "rgdb_wait = 0" in src/sim/system.cc;
scons build/MIPS_SE/gem5.opt CPU_MODELS=O3CPU
----
Build GDB-7.3 mips-cross:
./configure --target=mips-linux-gnu --prefix=xxx/gdb-7.3-install/
make
make install
----
Run:
./build/MIPS_SE/gem5.opt configs/example/se.py --detailed --caches
./mips-linux-gnu-gdb xxx/gem5/tests/test-progs/hello/bin/mips/linux/hello
(gdb) target remote :7000
(gdb) info registers
(gdb) disassemble
(gdb) si
(gdb) break main
(gdb) c
(gdb) quit
Testing done.
2011-09-10 03:45:25 -07:00
Gabe Black
6a2b223112 PseudoInst: Add compiler guards to pseudo_inst.hh. 2011-09-10 02:31:15 -07:00
Gabe Black
49a7ed0397 StaticInst: Merge StaticInst and StaticInstBase.
Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
2011-09-09 02:40:11 -07:00
Gabe Black
b7b545bc38 Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
2011-09-09 02:30:01 -07:00
Gabe Black
a1ad9e652a Stack: Tidy up some comments, a warning, and make stack extension consistent.
Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
2011-09-09 01:01:43 -07:00
Gabe Black
f370ac5c18 ISA parser: Don't look for operands in strings. 2011-09-08 03:21:14 -07:00
Gabe Black
f4dc64655f ISA parser: Match /* */ and // style comments.
Comments should not be scanned for operands, and we should look for both /* */
style and // style.
2011-09-08 03:20:05 -07:00
Gabe Black
87d687e242 X86: Make sure instruction flags are set properly even on 32 bit machines.
The way flag bits were being set for microops in x86 ended up implicitly
calling the bitset constructor which was truncating flags beyond the width of
an unsigned long. This change sets the bits in chunks which are always small
enough to avoid being truncated. On 64 bit machines this should reduce to be
the same as before, and on 32 bit machines it should work properly and not be
unreasonably inefficient.
2011-09-05 18:36:26 -07:00
Gabe Black
3bd0b9654c X86,TLB: Make sure the "delayedResponse" variable is always set.
When an instruction is translated in the x86 TLB, a variable called
delayedResponse is passed back and forth which tracks whether a translation
could be completed immediately, or if there's going to be callback that will
finish things up. If a read was to the internal memory space, memory mapped
registers used to implement things like MSRs, the function hadn't yet gotten
to where delayedResponse was set to false, it's default. That meant that the
value was never set, and the TLB could start waiting for a callback that would
never come. This change simply moves the assignment to above where control
can divert to translateInt().
2011-09-05 02:48:57 -07:00
Lisa Hsu
365966304e TLB: comments and a helpful warning.
Nothing big here, but when you have an address that is not in the page table request to be allocated, if it falls outside of the maximum stack range all you get is a page fault and you don't know why.  Add a little warn() to explain it a bit.  Also add some comments and alter logic a little so that you don't totally ignore the return value of checkAndAllocNextPage().
2011-09-02 17:04:00 -07:00
Lisa Hsu
f6a2ef22ff Fix build for gcc-4.2 opt/fast
Even though the code is safe, compiler flags a warning here, which are treated as errors for fast/opt. I know it's redundant but it has no side effects and fixes the compile.
2011-09-01 15:25:54 -07:00