src/python/m5/objects/BaseCPU.py:
Make mem parameter a MemObject, not just a PhysicalMemory
Fix a reference not using self
tests/configs/simple-atomic.py:
Set the mem paramter
tests/configs/simple-timing.py:
Set the mem parameter
--HG--
extra : convert_revision : 6bd9df36831a1c5bafc9e88ab945c2ebe91db785
Kinda port DRAM to new memory system. The code is *really* ugly (not my fault) and right now something about the stats it uses
causes a simulator segfault.
src/SConscript:
Add dram.cc to sconscript
src/mem/physical.cc:
src/mem/physical.hh:
Add params struct to physical memory, use params, make latency function be virtual
src/python/m5/objects/PhysicalMemory.py:
Add DRAMMemory python class
--HG--
extra : convert_revision : 5bd9f2e071c62da89e8efa46fa016f342c01535d
src/cpu/o3/fetch_impl.hh:
Fix ordering so dereference works
src/cpu/o3/lsq_impl.hh:
Check to make sure we didn't squash already
src/cpu/o3/lsq_unit.hh:
Fix for counting squashed retrys in the WB count
src/cpu/o3/lsq_unit_impl.hh:
Make sure to set retryID for stores, and clear it appropriately
--HG--
extra : convert_revision : 689765a1baea7b36f13eb177d65e97b52b6da09f
src/mem/cache/base_cache.cc:
Add in retry path for blocking with multi-level caches
src/mem/cache/base_cache.hh:
Pull more of the blocking fixes into head
src/mem/packet.hh:
Fix typo
--HG--
extra : convert_revision : d4d149adfa414136ebd2c4789b739bb065710f7a
Nate needs to fix sinic builder stuff
Gabe needs to verify my fixes to decoder.isa
OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset
README:
Fix the swig version in the readme
src/SConscript:
remove sinic until nate fixes the builder crap for it
src/arch/alpha/system.hh:
src/arch/mips/isa/includes.isa:
src/arch/sparc/isa/decoder.isa:
src/base/stats/visit.cc:
src/base/timebuf.hh:
src/dev/ide_disk.cc:
src/dev/sinic.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr_queue.cc:
src/mem/packet.hh:
src/mem/request.hh:
src/sim/builder.hh:
src/sim/system.hh:
fixes for gcc 4.1
--HG--
extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
-Basically removed the ASID from places it is no longer needed due to PageTable
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/miss_queue.hh:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/prefetch/base_prefetcher.hh:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
Remove asid where it wasn't neccesary anymore due to Page Table
--HG--
extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28
src/arch/sparc/process.cc:
All of the auxilliary vectors are now set like they are in the linux elf loader. This code should probably be moved to arch/sparc/linux/process.cc somehow.
--HG--
extra : convert_revision : 4a90cacf70b1032cad3f18b0f833a6df8237e0de
src/arch/alpha/regfile.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/cpu/exetrace.hh:
Added functions to start to support dumping register values once per cycle.
src/cpu/exetrace.cc:
Added some code to support printing the value of registers after each cycle.
src/python/m5/main.py:
Options to turn on output after every instruction. They are commented out.
--HG--
extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0
configs/common/FSConfig.py:
Clean up some code to make functions look less like classes. Also put makeList function (formerly listWrapper) into m5 itself.
configs/test/fs.py:
Update for changed code.
src/python/m5/__init__.py:
Put makeList into m5.
--HG--
extra : convert_revision : 731806a7486f9abf986f52926126df666b024b1d
src/arch/mips/isa/base.isa:
special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
change comment
--HG--
extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5
src/arch/sparc/isa/operands.isa:
Added the GSR register as a control register
--HG--
extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!
Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )
src/arch/alpha/isa/mem.isa:
spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
Gabe really authored this
src/arch/mips/isa/decoder.isa:
add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
Steven really did this file
src/arch/mips/isa/formats/branch.isa:
fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
update LoadStoreBase template
src/arch/mips/isa_traits.cc:
update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
add in nextNPC variable and supporting functions.
add isCondDelaySlot function
Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
init nextNPC
src/cpu/o3/SConscript:
add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
add some extra communication variables to aid in handling the
delay slots
src/cpu/o3/commit.hh:
minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
Update function interface ...
adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
update removeInstsNotInROB
src/cpu/o3/decode.hh:
declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
no need for my name here
src/cpu/o3/isa_specific.hh:
add in MIPS files
src/cpu/o3/scoreboard.hh:
dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
MIPS file for O3CPU...mirrors ALPHA definition
--HG--
extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
src/arch/sparc/isa/decoder.isa:
fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
Fixed some memory errors related to floating point.
--HG--
extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/fs.py:
Hand merge.
--HG--
extra : convert_revision : 78f7c46084f66d52ddfe0386fd7c08de8017331e
SConstruct:
Include an option to specify the CPUs being tested.
src/cpu/SConscript:
Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker.
src/python/m5/objects/O3CPU.py:
Include default options. Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used.
tests/SConscript:
Several minor updates (sorry for one commit). Updated the copyright and fixed some m5 style issues. Also added the ability to specify which CPUs to run the tests on.
--HG--
extra : convert_revision : b0b801115705544ea02e572e31314f7bb8b5f0f2
Make PioPort use it
Make Physical memory use it as well
src/SConscript:
Add timing port to sconscript
src/dev/io_device.cc:
src/dev/io_device.hh:
Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory
src/mem/physical.cc:
src/mem/physical.hh:
use a simple timing port stuff instead of rolling our own here
--HG--
extra : convert_revision : e5befbd295a572568cfdca533efb5ed1984c59d1
Add a max time option in seconds and a single system root clock be 1THz
configs/test/fs.py:
Add a max time option in seconds and a single system root clock be 1THz
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Enforce the timing cpu ticking at it's clock rate
--HG--
extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
src/python/m5/objects/Device.py:
src/python/m5/objects/Pci.py:
Change the default here to a latency rather than a Tick
--HG--
extra : convert_revision : b9366dd89646cea27a836baf249ac2da38c1809f
src/cpu/checker/cpu.hh:
Don't count checker's instructions towards total instructions committed.
src/python/m5/objects/Root.py:
Set default clock to 1 THz.
--HG--
extra : convert_revision : 0b5eaa197c860c361a3b00087e45ddc249ff1918
Right now only non-SMT SE regression tests have been added back in. The rest are pending getting SMT working, and consolidating the FS configuration files.
Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file.
Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work. The test itself should probably work once the code is fixed.
SConstruct:
Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again.
src/cpu/SConscript:
Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only.
--HG--
extra : convert_revision : 34e6286150aae8f316ae694f6c00be8f510522f2
src/cpu/o3/lsq_unit.hh:
LSQ needs to decrement the WB counter if the load is going to be replayed.
src/cpu/o3/lsq_unit_impl.hh:
LSQ needs to decrement the WB counter if the load is squashed.
--HG--
extra : convert_revision : 20a10baf0d6ab46065e561ddba231251865ebdbd
src/python/m5/config.py:
Formatting.
src/python/m5/main.py:
Slightly more useful output when you don't enter in a valid script file.
--HG--
extra : convert_revision : 5a71a6c94dbedeb000f83f57b0b575c2df924509
src/arch/SConscript:
Fixes for including the CheckerCPU if it's specified via command line. Previously the env variable was actually being modified.
src/cpu/SConscript:
Copy the CPU_MODELS from the env, don't create a proxy to it.
--HG--
extra : convert_revision : 7d069bd93a6834ccaa1c378b2bc76dce76745c19
suspend context will now take the thread off the activeThread list.
src/arch/mips/isa_traits.cc:
add in copy MiscRegs unimplemented function
--HG--
extra : convert_revision : 3ed5320b3786f84d4bb242e3a32b6f415339c3ba
src/arch/mips/isa_traits.hh:
MaxAddr is defined in config.py now
src/arch/mips/process.cc:
adjust process so SMT threads get their own stack space
src/arch/mips/process.hh:
add stack_start static variable
--HG--
extra : convert_revision : 73fdf3da9831d86536651835d209806c7f0d59da
into zeep.pool:/z/saidi/work/m5.newmem
src/python/m5/main.py:
merge two help fixes
--HG--
extra : convert_revision : b5c4a88bb84b726bebd3e357a4ef29acc0d95600
update scripts acordingly
configs/test/SysPaths.py:
new syspaths from nate, this one allows you to set script, binary, and disk paths like
system.dir = 'aouaou' in your script
configs/test/fs.py:
update for system mem_mode
Put small checkpoint example
Make clock 1THz
configs/test/test.py:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/system.cc:
src/arch/alpha/tru64/system.cc:
src/arch/sparc/system.cc:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
update for system mem_mode
src/dev/io_device.cc:
Use time returned from sendAtomic to delay
--HG--
extra : convert_revision : 67eedb3c84ab2584613faf88a534e793926fc92f
src/cpu/o3/lsq.hh:
Update to have LSQ work with only one dcache port for all LSQ Units. LSQ has the dcache port, and the LSQ Units must tell the LSQ if the cache has become blocked.
src/cpu/o3/lsq_impl.hh:
Updates to have the LSQ work with only one dcache port for all LSQUnits.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
Update for LSQ to create dcache port instead of LSQUnits. Now LSQUnits are given the dcache port from the LSQ, and also must check the LSQ if the cache is blocked prior to accessing the cache.
--HG--
extra : convert_revision : 2708adbf323f4e7647dc0c1e31ef5bb4596b89f8
States are now running, draining, or drained. memory state information moved into system object
system parameter is not fs only for cpus
Implement drain() support in devices
Update for drain() call that returns number of times drain_event->process() will be called
Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
Since se mode has a system, allow access to it
Verify that the atomic cpu is connected to an atomic system on resume
src/cpu/simple/base.cc:
Since se mode has a system, allow access to it
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system
Since se mode has a system, allow access to it
Verify that the timing cpu is connected to an timing system on resume
src/dev/ide_disk.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
src/dev/sinic.cc:
src/dev/sinic.hh:
Implement drain() support in devices
src/python/m5/config.py:
Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times
src/python/m5/objects/BaseCPU.py:
move system parameter out of fs to everyone
src/sim/sim_object.cc:
src/sim/sim_object.hh:
States are now running, draining, or drained. memory state information moved into system object
src/sim/system.cc:
src/sim/system.hh:
memory mode information now contained in system object
--HG--
extra : convert_revision : 1389c77e66ee6d9710bf77b4306fb47e107b21cf
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/test.py:
Hand merge.
--HG--
extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
src/SConscript:
It's no longer "ALPHA_ISA". I don't think we meant to leave out the EIO sources.
--HG--
extra : convert_revision : 1ca63ffb571d9021f1ced0bf0df1816b0b798edc
src/cpu/o3/commit_impl.hh:
Always set instruction. This is necessary for serialization as the instruction is also serialized.
src/cpu/o3/cpu.cc:
Change serialization so it matches other CPU's output. Also fix up some indexing.
--HG--
extra : convert_revision : 52f6e183132d177bed6e29dd7cf0c10aed6d8534
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/Tsunami.py:
Push more default options to the Python object level as they are rarely changed.
--HG--
extra : convert_revision : 963eb7a34cd04529b3c5f24b92904ab725c93efb
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
src/cpu/o3/fetch_impl.hh:
Hand merge.
--HG--
extra : convert_revision : 820dab2bc921cbadecaca51cd069327f984f5c74
src/python/m5/main.py:
Add a command line option to invoke pdb on your script
--HG--
extra : convert_revision : ef5a2860bd3f6e479fa80eccaae0cb5541a20b50
Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests).
src/cpu/o3/fetch_impl.hh:
Fix ordering issue with squashed Icache Fetches and Static data in packet.
--HG--
extra : convert_revision : a6adb87540b007ead0b4982cb3f31da8199fb5ca
src/python/m5/main.py:
Don't allow interspersed arguments, it messes things up
--HG--
extra : convert_revision : 8f1bcf4391f570741d92bf5420879862a48f6016
configs/test/fs.py:
configs/test/test.py:
update for the new way that m5 deals with options
src/python/SConscript:
Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the
python stuff.
src/python/m5/__init__.py:
redo the way options work.
Move them all to main.py
src/sim/main.cc:
Migrate more functionality for main() into python.
Namely option parsing
src/python/m5/attrdict.py:
A dictionary object that overrides attribute access to
do item access.
src/python/m5/main.py:
The new location for M5's option parsing, and the main()
routine to set up the simulation.
--HG--
extra : convert_revision : c86b87a9f508bde1994088e23fd470c7753ee4c1
src/mem/cache/base_cache.cc:
If we still have outstanding requests, need to schedule event again
src/mem/cache/miss/miss_queue.cc:
Need to use block size so overlapping requests match in the MSHR's
src/mem/cache/miss/mshr.cc:
Actually save the address, otherwise we can't match MSHR's
--HG--
extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
src/cpu/SConscript:
Change the error message to be slightly nicer.
src/cpu/o3/commit.hh:
Remove old code.
src/cpu/o3/commit_impl.hh:
Remove old unused code.
--HG--
extra : convert_revision : 48aa430e1f3554007dd5e4f3d9e89b5e4f124390
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : 9098d989832e2a5818b80771e3c02170c5c8cd5b
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/python/m5/objects/OzoneCPU.py:
Support Ron's recent port changes.
src/cpu/ozone/lw_back_end_impl.hh:
Support Ron's recent port changes. Also support handling faults in SE.
--HG--
extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891
src/cpu/checker/cpu.hh:
Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
Add ports to the parameters.
--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
