gem5/src
Ali Saidi efc06d0545 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

src/python/m5/main.py:
    merge two help fixes

--HG--
extra : convert_revision : b5c4a88bb84b726bebd3e357a4ef29acc0d95600
2006-07-13 15:50:09 -04:00
..
arch add system.mem_mode = ['timing', 'atomic'] 2006-07-13 15:48:17 -04:00
base Add parameters for backwards and forwards sizes for time buffers. 2006-07-10 15:40:28 -04:00
cpu Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recent changes, and using the O3CPU in SMT mode. 2006-07-13 13:12:51 -04:00
dev add system.mem_mode = ['timing', 'atomic'] 2006-07-13 15:48:17 -04:00
kern Merge zizzer.eecs.umich.edu:/bk/newmem 2006-06-17 18:28:21 -04:00
mem Some fixes so that MSHR's are matched and we don't issue overlapping requests with detailed cpu 2006-07-10 17:16:15 -04:00
python fix help when no arguments are passed to m5 2006-07-13 15:48:41 -04:00
sim add system.mem_mode = ['timing', 'atomic'] 2006-07-13 15:48:17 -04:00
unittest Merge iceaxe.:/Volumes/work/research/m5/head 2006-06-11 22:01:34 -04:00
Doxyfile New directory structure: 2006-05-22 14:29:33 -04:00
SConscript Remove sampler and serializer. Now they are handled through C++ interacting with Python. 2006-07-05 21:14:36 -04:00